[linux.git] / drivers / pci / pci.h

#ifndef DRIVERS_PCI_H
#define DRIVERS_PCI_H

#include <linux/workqueue.h>

#define PCI_CFG_SPACE_SIZE	256
#define PCI_CFG_SPACE_EXP_SIZE	4096

/* Functions internal to the PCI core code */

int pci_create_sysfs_dev_files(struct pci_dev *pdev);
void pci_remove_sysfs_dev_files(struct pci_dev *pdev);
#if !defined(CONFIG_DMI) && !defined(CONFIG_ACPI)
static inline void pci_create_firmware_label_files(struct pci_dev *pdev)
{ return; }
static inline void pci_remove_firmware_label_files(struct pci_dev *pdev)
{ return; }
#else
void pci_create_firmware_label_files(struct pci_dev *pdev);
void pci_remove_firmware_label_files(struct pci_dev *pdev);
#endif
void pci_cleanup_rom(struct pci_dev *dev);
#ifdef HAVE_PCI_MMAP
enum pci_mmap_api {
	PCI_MMAP_SYSFS,	/* mmap on /sys/bus/pci/devices/<BDF>/resource<N> */
	PCI_MMAP_PROCFS	/* mmap on /proc/bus/pci/<BDF> */
};
int pci_mmap_fits(struct pci_dev *pdev, int resno, struct vm_area_struct *vmai,
		  enum pci_mmap_api mmap_api);
#endif
int pci_probe_reset_function(struct pci_dev *dev);

/**
 * struct pci_platform_pm_ops - Firmware PM callbacks
 *
 * @is_manageable: returns 'true' if given device is power manageable by the
 *                 platform firmware
 *
 * @set_state: invokes the platform firmware to set the device's power state
 *
 * @choose_state: returns PCI power state of given device preferred by the
 *                platform; to be used during system-wide transitions from a
 *                sleeping state to the working state and vice versa
 *
 * @sleep_wake: enables/disables the system wake up capability of given device
 *
 * @run_wake: enables/disables the platform to generate run-time wake-up events
 *		for given device (the device's wake-up capability has to be
 *		enabled by @sleep_wake for this feature to work)
 *
 * If given platform is generally capable of power managing PCI devices, all of
 * these callbacks are mandatory.
 */
struct pci_platform_pm_ops {
	bool (*is_manageable)(struct pci_dev *dev);
	int (*set_state)(struct pci_dev *dev, pci_power_t state);
	pci_power_t (*choose_state)(struct pci_dev *dev);
	int (*sleep_wake)(struct pci_dev *dev, bool enable);
	int (*run_wake)(struct pci_dev *dev, bool enable);
};

int pci_set_platform_pm(struct pci_platform_pm_ops *ops);
void pci_update_current_state(struct pci_dev *dev, pci_power_t state);
void pci_power_up(struct pci_dev *dev);
void pci_disable_enabled_device(struct pci_dev *dev);
int pci_finish_runtime_suspend(struct pci_dev *dev);
int __pci_pme_wakeup(struct pci_dev *dev, void *ign);
void pci_wakeup_bus(struct pci_bus *bus);
void pci_config_pm_runtime_get(struct pci_dev *dev);
void pci_config_pm_runtime_put(struct pci_dev *dev);
void pci_pm_init(struct pci_dev *dev);
void pci_allocate_cap_save_buffers(struct pci_dev *dev);
void pci_free_cap_save_buffers(struct pci_dev *dev);

static inline void pci_wakeup_event(struct pci_dev *dev)
{
	/* Wait 100 ms before the system can be put into a sleep state. */
	pm_wakeup_event(&dev->dev, 100);
}

static inline bool pci_is_bridge(struct pci_dev *pci_dev)
{
	return !!(pci_dev->subordinate);
}

struct pci_vpd_ops {
	ssize_t (*read)(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
	ssize_t (*write)(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
	void (*release)(struct pci_dev *dev);
};

struct pci_vpd {
	unsigned int len;
	const struct pci_vpd_ops *ops;
	struct bin_attribute *attr; /* descriptor for sysfs VPD entry */
};

int pci_vpd_pci22_init(struct pci_dev *dev);
static inline void pci_vpd_release(struct pci_dev *dev)
{
	if (dev->vpd)
		dev->vpd->ops->release(dev);
}

/* PCI /proc functions */
#ifdef CONFIG_PROC_FS
int pci_proc_attach_device(struct pci_dev *dev);
int pci_proc_detach_device(struct pci_dev *dev);
int pci_proc_detach_bus(struct pci_bus *bus);
#else
static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; }
static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; }
static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; }
#endif

/* Functions for PCI Hotplug drivers to use */
int pci_hp_add_bridge(struct pci_dev *dev);

#ifdef HAVE_PCI_LEGACY
void pci_create_legacy_files(struct pci_bus *bus);
void pci_remove_legacy_files(struct pci_bus *bus);
#else
static inline void pci_create_legacy_files(struct pci_bus *bus) { return; }
static inline void pci_remove_legacy_files(struct pci_bus *bus) { return; }
#endif

/* Lock for read/write access to pci device and bus lists */
extern struct rw_semaphore pci_bus_sem;

extern raw_spinlock_t pci_lock;

extern unsigned int pci_pm_d3_delay;

#ifdef CONFIG_PCI_MSI
void pci_no_msi(void);
void pci_msi_init_pci_dev(struct pci_dev *dev);
#else
static inline void pci_no_msi(void) { }
static inline void pci_msi_init_pci_dev(struct pci_dev *dev) { }
#endif

void pci_realloc_get_opt(char *);

static inline int pci_no_d1d2(struct pci_dev *dev)
{
	unsigned int parent_dstates = 0;

	if (dev->bus->self)
		parent_dstates = dev->bus->self->no_d1d2;
	return (dev->no_d1d2 || parent_dstates);

}
extern struct device_attribute pci_dev_attrs[];
extern struct device_attribute pcibus_dev_attrs[];
extern struct device_type pci_dev_type;
extern struct bus_attribute pci_bus_attrs[];


/**
 * pci_match_one_device - Tell if a PCI device structure has a matching
 *                        PCI device id structure
 * @id: single PCI device id structure to match
 * @dev: the PCI device structure to match against
 *
 * Returns the matching pci_device_id structure or %NULL if there is no match.
 */
static inline const struct pci_device_id *
pci_match_one_device(const struct pci_device_id *id, const struct pci_dev *dev)
{
	if ((id->vendor == PCI_ANY_ID || id->vendor == dev->vendor) &&
	    (id->device == PCI_ANY_ID || id->device == dev->device) &&
	    (id->subvendor == PCI_ANY_ID || id->subvendor == dev->subsystem_vendor) &&
	    (id->subdevice == PCI_ANY_ID || id->subdevice == dev->subsystem_device) &&
	    !((id->class ^ dev->class) & id->class_mask))
		return id;
	return NULL;
}

/* PCI slot sysfs helper code */
#define to_pci_slot(s) container_of(s, struct pci_slot, kobj)

extern struct kset *pci_slots_kset;

struct pci_slot_attribute {
	struct attribute attr;
	ssize_t (*show)(struct pci_slot *, char *);
	ssize_t (*store)(struct pci_slot *, const char *, size_t);
};
#define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr)

enum pci_bar_type {
	pci_bar_unknown,	/* Standard PCI BAR probe */
	pci_bar_io,		/* An io port BAR */
	pci_bar_mem32,		/* A 32-bit memory BAR */
	pci_bar_mem64,		/* A 64-bit memory BAR */
};

bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl,
				int crs_timeout);
int pci_setup_device(struct pci_dev *dev);
int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
		    struct resource *res, unsigned int reg);
int pci_resource_bar(struct pci_dev *dev, int resno, enum pci_bar_type *type);
void pci_configure_ari(struct pci_dev *dev);
void __ref __pci_bus_size_bridges(struct pci_bus *bus,
			struct list_head *realloc_head);
void __ref __pci_bus_assign_resources(const struct pci_bus *bus,
				      struct list_head *realloc_head,
				      struct list_head *fail_head);

/**
 * pci_ari_enabled - query ARI forwarding status
 * @bus: the PCI bus
 *
 * Returns 1 if ARI forwarding is enabled, or 0 if not enabled;
 */
static inline int pci_ari_enabled(struct pci_bus *bus)
{
	return bus->self && bus->self->ari_enabled;
}

void pci_reassigndev_resource_alignment(struct pci_dev *dev);
void pci_disable_bridge_window(struct pci_dev *dev);

/* Single Root I/O Virtualization */
struct pci_sriov {
	int pos;		/* capability position */
	int nres;		/* number of resources */
	u32 cap;		/* SR-IOV Capabilities */
	u16 ctrl;		/* SR-IOV Control */
	u16 total_VFs;		/* total VFs associated with the PF */
	u16 initial_VFs;	/* initial VFs associated with the PF */
	u16 num_VFs;		/* number of VFs available */
	u16 offset;		/* first VF Routing ID offset */
	u16 stride;		/* following VF stride */
	u32 pgsz;		/* page size for BAR alignment */
	u8 link;		/* Function Dependency Link */
	u16 driver_max_VFs;	/* max num VFs driver supports */
	struct pci_dev *dev;	/* lowest numbered PF */
	struct pci_dev *self;	/* this PF */
	struct mutex lock;	/* lock for VF bus */
	struct work_struct mtask; /* VF Migration task */
	u8 __iomem *mstate;	/* VF Migration State Array */
};

#ifdef CONFIG_PCI_ATS
void pci_restore_ats_state(struct pci_dev *dev);
#else
static inline void pci_restore_ats_state(struct pci_dev *dev)
{
}
#endif /* CONFIG_PCI_ATS */

#ifdef CONFIG_PCI_IOV
int pci_iov_init(struct pci_dev *dev);
void pci_iov_release(struct pci_dev *dev);
int pci_iov_resource_bar(struct pci_dev *dev, int resno,
			 enum pci_bar_type *type);
resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno);
void pci_restore_iov_state(struct pci_dev *dev);
int pci_iov_bus_range(struct pci_bus *bus);

#else
static inline int pci_iov_init(struct pci_dev *dev)
{
	return -ENODEV;
}
static inline void pci_iov_release(struct pci_dev *dev)

{
}
static inline int pci_iov_resource_bar(struct pci_dev *dev, int resno,
				       enum pci_bar_type *type)
{
	return 0;
}
static inline void pci_restore_iov_state(struct pci_dev *dev)
{
}
static inline int pci_iov_bus_range(struct pci_bus *bus)
{
	return 0;
}

#endif /* CONFIG_PCI_IOV */

unsigned long pci_cardbus_resource_alignment(struct resource *);

static inline resource_size_t pci_resource_alignment(struct pci_dev *dev,
						     struct resource *res)
{
#ifdef CONFIG_PCI_IOV
	int resno = res - dev->resource;

	if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END)
		return pci_sriov_resource_alignment(dev, resno);
#endif
	if (dev->class >> 8  == PCI_CLASS_BRIDGE_CARDBUS)
		return pci_cardbus_resource_alignment(res);
	return resource_alignment(res);
}

void pci_enable_acs(struct pci_dev *dev);

struct pci_dev_reset_methods {
	u16 vendor;
	u16 device;
	int (*reset)(struct pci_dev *dev, int probe);
};

#ifdef CONFIG_PCI_QUIRKS
int pci_dev_specific_reset(struct pci_dev *dev, int probe);
#else
static inline int pci_dev_specific_reset(struct pci_dev *dev, int probe)
{
	return -ENOTTY;
}
#endif

#endif /* DRIVERS_PCI_H */
Commit	Line	Data
557848c3 ZY	1	#ifndef DRIVERS_PCI_H
	2	#define DRIVERS_PCI_H
	3
74bb1bcc YZ	4	#include <linux/workqueue.h>
74bb1bcc YZ	5
557848c3 ZY	6	#define PCI_CFG_SPACE_SIZE 256
	7	#define PCI_CFG_SPACE_EXP_SIZE 4096
	8
1da177e4 LT	9	/* Functions internal to the PCI core code */
1da177e4 LT	10
f39d5b72 BH	11	int pci_create_sysfs_dev_files(struct pci_dev *pdev);
f39d5b72 BH	12	void pci_remove_sysfs_dev_files(struct pci_dev *pdev);
6058989b	13	#if !defined(CONFIG_DMI) && !defined(CONFIG_ACPI)
911e1c9b	14	static inline void pci_create_firmware_label_files(struct pci_dev *pdev)
b879743f	15	{ return; }
911e1c9b	16	static inline void pci_remove_firmware_label_files(struct pci_dev *pdev)
b879743f	17	{ return; }
911e1c9b	18	#else
f39d5b72 BH	19	void pci_create_firmware_label_files(struct pci_dev *pdev);
f39d5b72 BH	20	void pci_remove_firmware_label_files(struct pci_dev *pdev);
911e1c9b	21	#endif
f39d5b72	22	void pci_cleanup_rom(struct pci_dev *dev);
9eff02e2	23	#ifdef HAVE_PCI_MMAP
3b519e4e MW	24	enum pci_mmap_api {
	25	PCI_MMAP_SYSFS, /* mmap on /sys/bus/pci/devices/<BDF>/resource<N> */
	26	PCI_MMAP_PROCFS /* mmap on /proc/bus/pci/<BDF> */
	27	};
f39d5b72 BH	28	int pci_mmap_fits(struct pci_dev pdev, int resno, struct vm_area_struct vmai,
f39d5b72 BH	29	enum pci_mmap_api mmap_api);
9eff02e2	30	#endif
711d5779	31	int pci_probe_reset_function(struct pci_dev *dev);
ce5ccdef	32
961d9120	33	/**
b33bfdef	34	* struct pci_platform_pm_ops - Firmware PM callbacks
961d9120	35	*
b33bfdef RD	36	* @is_manageable: returns 'true' if given device is power manageable by the
b33bfdef RD	37	* platform firmware
961d9120	38	*
b33bfdef	39	* @set_state: invokes the platform firmware to set the device's power state
961d9120	40	*
b33bfdef RD	41	* @choose_state: returns PCI power state of given device preferred by the
	42	* platform; to be used during system-wide transitions from a
	43	* sleeping state to the working state and vice versa
961d9120	44	*
b33bfdef	45	* @sleep_wake: enables/disables the system wake up capability of given device
eb9d0fe4	46	*
b67ea761 RW	47	* @run_wake: enables/disables the platform to generate run-time wake-up events
	48	* for given device (the device's wake-up capability has to be
	49	* enabled by @sleep_wake for this feature to work)
	50	*
961d9120 RW	51	* If given platform is generally capable of power managing PCI devices, all of
	52	* these callbacks are mandatory.
	53	*/
	54	struct pci_platform_pm_ops {
	55	bool (is_manageable)(struct pci_dev dev);
	56	int (set_state)(struct pci_dev dev, pci_power_t state);
	57	pci_power_t (choose_state)(struct pci_dev dev);
eb9d0fe4	58	int (sleep_wake)(struct pci_dev dev, bool enable);
b67ea761	59	int (run_wake)(struct pci_dev dev, bool enable);
961d9120 RW	60	};
961d9120 RW	61
f39d5b72 BH	62	int pci_set_platform_pm(struct pci_platform_pm_ops *ops);
	63	void pci_update_current_state(struct pci_dev *dev, pci_power_t state);
	64	void pci_power_up(struct pci_dev *dev);
	65	void pci_disable_enabled_device(struct pci_dev *dev);
	66	int pci_finish_runtime_suspend(struct pci_dev *dev);
	67	int __pci_pme_wakeup(struct pci_dev dev, void ign);
	68	void pci_wakeup_bus(struct pci_bus *bus);
	69	void pci_config_pm_runtime_get(struct pci_dev *dev);
	70	void pci_config_pm_runtime_put(struct pci_dev *dev);
	71	void pci_pm_init(struct pci_dev *dev);
	72	void pci_allocate_cap_save_buffers(struct pci_dev *dev);
f796841e	73	void pci_free_cap_save_buffers(struct pci_dev *dev);
aa8c6c93	74
b6e335ae RW	75	static inline void pci_wakeup_event(struct pci_dev *dev)
	76	{
	77	/* Wait 100 ms before the system can be put into a sleep state. */
	78	pm_wakeup_event(&dev->dev, 100);
	79	}
	80
aa8c6c93 RW	81	static inline bool pci_is_bridge(struct pci_dev *pci_dev)
	82	{
	83	return !!(pci_dev->subordinate);
	84	}
0f64474b	85
94e61088	86	struct pci_vpd_ops {
287d19ce SH	87	ssize_t (read)(struct pci_dev dev, loff_t pos, size_t count, void *buf);
287d19ce SH	88	ssize_t (write)(struct pci_dev dev, loff_t pos, size_t count, const void *buf);
94e61088 BH	89	void (release)(struct pci_dev dev);
	90	};
	91
	92	struct pci_vpd {
99cb233d	93	unsigned int len;
287d19ce	94	const struct pci_vpd_ops *ops;
94e61088 BH	95	struct bin_attribute attr; / descriptor for sysfs VPD entry */
	96	};
	97
f39d5b72	98	int pci_vpd_pci22_init(struct pci_dev *dev);
94e61088 BH	99	static inline void pci_vpd_release(struct pci_dev *dev)
	100	{
	101	if (dev->vpd)
	102	dev->vpd->ops->release(dev);
	103	}
	104
1da177e4 LT	105	/* PCI /proc functions */
1da177e4 LT	106	#ifdef CONFIG_PROC_FS
f39d5b72 BH	107	int pci_proc_attach_device(struct pci_dev *dev);
	108	int pci_proc_detach_device(struct pci_dev *dev);
	109	int pci_proc_detach_bus(struct pci_bus *bus);
1da177e4 LT	110	#else
	111	static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; }
	112	static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; }
1da177e4 LT	113	static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; }
	114	#endif
	115
	116	/* Functions for PCI Hotplug drivers to use */
a8e4b9c1	117	int pci_hp_add_bridge(struct pci_dev *dev);
1da177e4	118
f19aeb1f	119	#ifdef HAVE_PCI_LEGACY
f39d5b72 BH	120	void pci_create_legacy_files(struct pci_bus *bus);
f39d5b72 BH	121	void pci_remove_legacy_files(struct pci_bus *bus);
f19aeb1f BH	122	#else
	123	static inline void pci_create_legacy_files(struct pci_bus *bus) { return; }
	124	static inline void pci_remove_legacy_files(struct pci_bus *bus) { return; }
	125	#endif
1da177e4 LT	126
1da177e4 LT	127	/* Lock for read/write access to pci device and bus lists */
d71374da	128	extern struct rw_semaphore pci_bus_sem;
1da177e4	129
a2e27787 JK	130	extern raw_spinlock_t pci_lock;
a2e27787 JK	131
ffadcc2f	132	extern unsigned int pci_pm_d3_delay;
88187dfa	133
4b47b0ee	134	#ifdef CONFIG_PCI_MSI
309e57df	135	void pci_no_msi(void);
f39d5b72	136	void pci_msi_init_pci_dev(struct pci_dev *dev);
4b47b0ee	137	#else
309e57df	138	static inline void pci_no_msi(void) { }
4aa9bc95	139	static inline void pci_msi_init_pci_dev(struct pci_dev *dev) { }
4b47b0ee	140	#endif
8fed4b65	141
b55438fd	142	void pci_realloc_get_opt(char *);
f483d392	143
ffadcc2f KCA	144	static inline int pci_no_d1d2(struct pci_dev *dev)
	145	{
	146	unsigned int parent_dstates = 0;
4b47b0ee	147
ffadcc2f KCA	148	if (dev->bus->self)
	149	parent_dstates = dev->bus->self->no_d1d2;
	150	return (dev->no_d1d2 \|\| parent_dstates);
	151
	152	}
1da177e4	153	extern struct device_attribute pci_dev_attrs[];
b9d320fc	154	extern struct device_attribute pcibus_dev_attrs[];
4e15c46b	155	extern struct device_type pci_dev_type;
705b1aaa	156	extern struct bus_attribute pci_bus_attrs[];
705b1aaa	157
1da177e4 LT	158
	159	/**
	160	* pci_match_one_device - Tell if a PCI device structure has a matching
	161	* PCI device id structure
	162	* @id: single PCI device id structure to match
	163	* @dev: the PCI device structure to match against
367b09fe	164	*
1da177e4 LT	165	* Returns the matching pci_device_id structure or %NULL if there is no match.
	166	*/
	167	static inline const struct pci_device_id *
	168	pci_match_one_device(const struct pci_device_id id, const struct pci_dev dev)
	169	{
	170	if ((id->vendor == PCI_ANY_ID \|\| id->vendor == dev->vendor) &&
	171	(id->device == PCI_ANY_ID \|\| id->device == dev->device) &&
	172	(id->subvendor == PCI_ANY_ID \|\| id->subvendor == dev->subsystem_vendor) &&
	173	(id->subdevice == PCI_ANY_ID \|\| id->subdevice == dev->subsystem_device) &&
	174	!((id->class ^ dev->class) & id->class_mask))
	175	return id;
	176	return NULL;
	177	}
	178
f46753c5 AC	179	/* PCI slot sysfs helper code */
	180	#define to_pci_slot(s) container_of(s, struct pci_slot, kobj)
	181
	182	extern struct kset *pci_slots_kset;
	183
	184	struct pci_slot_attribute {
	185	struct attribute attr;
	186	ssize_t (show)(struct pci_slot , char *);
	187	ssize_t (store)(struct pci_slot , const char *, size_t);
	188	};
	189	#define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr)
	190
0b400c7e YZ	191	enum pci_bar_type {
	192	pci_bar_unknown, /* Standard PCI BAR probe */
	193	pci_bar_io, /* An io port BAR */
	194	pci_bar_mem32, /* A 32-bit memory BAR */
	195	pci_bar_mem64, /* A 64-bit memory BAR */
	196	};
	197
efdc87da YL	198	bool pci_bus_read_dev_vendor_id(struct pci_bus bus, int devfn, u32 pl,
efdc87da YL	199	int crs_timeout);
f39d5b72 BH	200	int pci_setup_device(struct pci_dev *dev);
	201	int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
	202	struct resource *res, unsigned int reg);
	203	int pci_resource_bar(struct pci_dev dev, int resno, enum pci_bar_type type);
	204	void pci_configure_ari(struct pci_dev *dev);
d66ecb72 JL	205	void __ref __pci_bus_size_bridges(struct pci_bus *bus,
	206	struct list_head *realloc_head);
	207	void __ref __pci_bus_assign_resources(const struct pci_bus *bus,
	208	struct list_head *realloc_head,
	209	struct list_head *fail_head);
939de1d6	210
58c3a727 YZ	211	/**
58c3a727 YZ	212	* pci_ari_enabled - query ARI forwarding status
6a49d812	213	* @bus: the PCI bus
58c3a727 YZ	214	*
	215	* Returns 1 if ARI forwarding is enabled, or 0 if not enabled;
	216	*/
6a49d812	217	static inline int pci_ari_enabled(struct pci_bus *bus)
58c3a727	218	{
6a49d812	219	return bus->self && bus->self->ari_enabled;
58c3a727 YZ	220	}
58c3a727 YZ	221
2069ecfb	222	void pci_reassigndev_resource_alignment(struct pci_dev *dev);
f39d5b72	223	void pci_disable_bridge_window(struct pci_dev *dev);
32a9a682	224
d1b054da YZ	225	/* Single Root I/O Virtualization */
	226	struct pci_sriov {
	227	int pos; /* capability position */
	228	int nres; /* number of resources */
	229	u32 cap; /* SR-IOV Capabilities */
	230	u16 ctrl; /* SR-IOV Control */
6b136724 BH	231	u16 total_VFs; /* total VFs associated with the PF */
	232	u16 initial_VFs; /* initial VFs associated with the PF */
	233	u16 num_VFs; /* number of VFs available */
d1b054da YZ	234	u16 offset; /* first VF Routing ID offset */
	235	u16 stride; /* following VF stride */
	236	u32 pgsz; /* page size for BAR alignment */
	237	u8 link; /* Function Dependency Link */
6b136724	238	u16 driver_max_VFs; /* max num VFs driver supports */
d1b054da YZ	239	struct pci_dev dev; / lowest numbered PF */
	240	struct pci_dev self; / this PF */
	241	struct mutex lock; /* lock for VF bus */
74bb1bcc YZ	242	struct work_struct mtask; /* VF Migration task */
74bb1bcc YZ	243	u8 __iomem mstate; / VF Migration State Array */
d1b054da YZ	244	};
d1b054da YZ	245
1900ca13	246	#ifdef CONFIG_PCI_ATS
f39d5b72	247	void pci_restore_ats_state(struct pci_dev *dev);
1900ca13 HX	248	#else
	249	static inline void pci_restore_ats_state(struct pci_dev *dev)
	250	{
	251	}
	252	#endif /* CONFIG_PCI_ATS */
	253
d1b054da	254	#ifdef CONFIG_PCI_IOV
f39d5b72 BH	255	int pci_iov_init(struct pci_dev *dev);
	256	void pci_iov_release(struct pci_dev *dev);
	257	int pci_iov_resource_bar(struct pci_dev *dev, int resno,
	258	enum pci_bar_type *type);
	259	resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno);
	260	void pci_restore_iov_state(struct pci_dev *dev);
	261	int pci_iov_bus_range(struct pci_bus *bus);
302b4215	262
d1b054da YZ	263	#else
	264	static inline int pci_iov_init(struct pci_dev *dev)
	265	{
	266	return -ENODEV;
	267	}
	268	static inline void pci_iov_release(struct pci_dev *dev)
	269
	270	{
	271	}
	272	static inline int pci_iov_resource_bar(struct pci_dev *dev, int resno,
	273	enum pci_bar_type *type)
	274	{
	275	return 0;
	276	}
8c5cdb6a YZ	277	static inline void pci_restore_iov_state(struct pci_dev *dev)
	278	{
	279	}
a28724b0 YZ	280	static inline int pci_iov_bus_range(struct pci_bus *bus)
	281	{
	282	return 0;
	283	}
302b4215	284
d1b054da YZ	285	#endif /* CONFIG_PCI_IOV */
d1b054da YZ	286
f39d5b72	287	unsigned long pci_cardbus_resource_alignment(struct resource *);
0a2daa1c	288
0e52247a	289	static inline resource_size_t pci_resource_alignment(struct pci_dev *dev,
f39d5b72	290	struct resource *res)
6faf17f6 CW	291	{
	292	#ifdef CONFIG_PCI_IOV
	293	int resno = res - dev->resource;
	294
	295	if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END)
	296	return pci_sriov_resource_alignment(dev, resno);
	297	#endif
0a2daa1c RP	298	if (dev->class >> 8 == PCI_CLASS_BRIDGE_CARDBUS)
0a2daa1c RP	299	return pci_cardbus_resource_alignment(res);
6faf17f6 CW	300	return resource_alignment(res);
	301	}
	302
f39d5b72	303	void pci_enable_acs(struct pci_dev *dev);
ae21ee65	304
b9c3b266 DC	305	struct pci_dev_reset_methods {
	306	u16 vendor;
	307	u16 device;
	308	int (reset)(struct pci_dev dev, int probe);
	309	};
	310
93177a74	311	#ifdef CONFIG_PCI_QUIRKS
f39d5b72	312	int pci_dev_specific_reset(struct pci_dev *dev, int probe);
93177a74 RW	313	#else
	314	static inline int pci_dev_specific_reset(struct pci_dev *dev, int probe)
	315	{
	316	return -ENOTTY;
	317	}
	318	#endif
b9c3b266	319
557848c3	320	#endif /* DRIVERS_PCI_H */