[linux.git] / drivers / pci / pci.h

#ifndef DRIVERS_PCI_H
#define DRIVERS_PCI_H

#include <linux/workqueue.h>

#define PCI_CFG_SPACE_SIZE	256
#define PCI_CFG_SPACE_EXP_SIZE	4096

/* Functions internal to the PCI core code */

extern int pci_uevent(struct device *dev, struct kobj_uevent_env *env);
extern int pci_create_sysfs_dev_files(struct pci_dev *pdev);
extern void pci_remove_sysfs_dev_files(struct pci_dev *pdev);
extern void pci_cleanup_rom(struct pci_dev *dev);
#ifdef HAVE_PCI_MMAP
extern int pci_mmap_fits(struct pci_dev *pdev, int resno,
			 struct vm_area_struct *vma);
#endif
int pci_probe_reset_function(struct pci_dev *dev);

/**
 * struct pci_platform_pm_ops - Firmware PM callbacks
 *
 * @is_manageable: returns 'true' if given device is power manageable by the
 *                 platform firmware
 *
 * @set_state: invokes the platform firmware to set the device's power state
 *
 * @choose_state: returns PCI power state of given device preferred by the
 *                platform; to be used during system-wide transitions from a
 *                sleeping state to the working state and vice versa
 *
 * @can_wakeup: returns 'true' if given device is capable of waking up the
 *              system from a sleeping state
 *
 * @sleep_wake: enables/disables the system wake up capability of given device
 *
 * If given platform is generally capable of power managing PCI devices, all of
 * these callbacks are mandatory.
 */
struct pci_platform_pm_ops {
	bool (*is_manageable)(struct pci_dev *dev);
	int (*set_state)(struct pci_dev *dev, pci_power_t state);
	pci_power_t (*choose_state)(struct pci_dev *dev);
	bool (*can_wakeup)(struct pci_dev *dev);
	int (*sleep_wake)(struct pci_dev *dev, bool enable);
};

extern int pci_set_platform_pm(struct pci_platform_pm_ops *ops);
extern void pci_update_current_state(struct pci_dev *dev, pci_power_t state);
extern void pci_disable_enabled_device(struct pci_dev *dev);
extern void pci_pm_init(struct pci_dev *dev);
extern void platform_pci_wakeup_init(struct pci_dev *dev);
extern void pci_allocate_cap_save_buffers(struct pci_dev *dev);

static inline bool pci_is_bridge(struct pci_dev *pci_dev)
{
	return !!(pci_dev->subordinate);
}

extern int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
extern int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
extern int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
extern int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
extern int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
extern int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);

struct pci_vpd_ops {
	ssize_t (*read)(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
	ssize_t (*write)(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
	void (*release)(struct pci_dev *dev);
};

struct pci_vpd {
	unsigned int len;
	const struct pci_vpd_ops *ops;
	struct bin_attribute *attr; /* descriptor for sysfs VPD entry */
};

extern int pci_vpd_pci22_init(struct pci_dev *dev);
static inline void pci_vpd_release(struct pci_dev *dev)
{
	if (dev->vpd)
		dev->vpd->ops->release(dev);
}

/* PCI /proc functions */
#ifdef CONFIG_PROC_FS
extern int pci_proc_attach_device(struct pci_dev *dev);
extern int pci_proc_detach_device(struct pci_dev *dev);
extern int pci_proc_detach_bus(struct pci_bus *bus);
#else
static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; }
static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; }
static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; }
#endif

/* Functions for PCI Hotplug drivers to use */
extern unsigned int pci_do_scan_bus(struct pci_bus *bus);

#ifdef HAVE_PCI_LEGACY
extern void pci_create_legacy_files(struct pci_bus *bus);
extern void pci_remove_legacy_files(struct pci_bus *bus);
#else
static inline void pci_create_legacy_files(struct pci_bus *bus) { return; }
static inline void pci_remove_legacy_files(struct pci_bus *bus) { return; }
#endif

/* Lock for read/write access to pci device and bus lists */
extern struct rw_semaphore pci_bus_sem;

extern unsigned int pci_pm_d3_delay;

#ifdef CONFIG_PCI_MSI
void pci_no_msi(void);
extern void pci_msi_init_pci_dev(struct pci_dev *dev);
#else
static inline void pci_no_msi(void) { }
static inline void pci_msi_init_pci_dev(struct pci_dev *dev) { }
#endif

#ifdef CONFIG_PCIEAER
void pci_no_aer(void);
#else
static inline void pci_no_aer(void) { }
#endif

static inline int pci_no_d1d2(struct pci_dev *dev)
{
	unsigned int parent_dstates = 0;

	if (dev->bus->self)
		parent_dstates = dev->bus->self->no_d1d2;
	return (dev->no_d1d2 || parent_dstates);

}
extern struct device_attribute pci_dev_attrs[];
extern struct device_attribute dev_attr_cpuaffinity;
extern struct device_attribute dev_attr_cpulistaffinity;
#ifdef CONFIG_HOTPLUG
extern struct bus_attribute pci_bus_attrs[];
#else
#define pci_bus_attrs	NULL
#endif


/**
 * pci_match_one_device - Tell if a PCI device structure has a matching
 *                        PCI device id structure
 * @id: single PCI device id structure to match
 * @dev: the PCI device structure to match against
 *
 * Returns the matching pci_device_id structure or %NULL if there is no match.
 */
static inline const struct pci_device_id *
pci_match_one_device(const struct pci_device_id *id, const struct pci_dev *dev)
{
	if ((id->vendor == PCI_ANY_ID || id->vendor == dev->vendor) &&
	    (id->device == PCI_ANY_ID || id->device == dev->device) &&
	    (id->subvendor == PCI_ANY_ID || id->subvendor == dev->subsystem_vendor) &&
	    (id->subdevice == PCI_ANY_ID || id->subdevice == dev->subsystem_device) &&
	    !((id->class ^ dev->class) & id->class_mask))
		return id;
	return NULL;
}

struct pci_dev *pci_find_upstream_pcie_bridge(struct pci_dev *pdev);

/* PCI slot sysfs helper code */
#define to_pci_slot(s) container_of(s, struct pci_slot, kobj)

extern struct kset *pci_slots_kset;

struct pci_slot_attribute {
	struct attribute attr;
	ssize_t (*show)(struct pci_slot *, char *);
	ssize_t (*store)(struct pci_slot *, const char *, size_t);
};
#define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr)

enum pci_bar_type {
	pci_bar_unknown,	/* Standard PCI BAR probe */
	pci_bar_io,		/* An io port BAR */
	pci_bar_mem32,		/* A 32-bit memory BAR */
	pci_bar_mem64,		/* A 64-bit memory BAR */
};

extern int pci_setup_device(struct pci_dev *dev);
extern int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
				struct resource *res, unsigned int reg);
extern int pci_resource_bar(struct pci_dev *dev, int resno,
			    enum pci_bar_type *type);
extern int pci_bus_add_child(struct pci_bus *bus);
extern void pci_enable_ari(struct pci_dev *dev);
/**
 * pci_ari_enabled - query ARI forwarding status
 * @bus: the PCI bus
 *
 * Returns 1 if ARI forwarding is enabled, or 0 if not enabled;
 */
static inline int pci_ari_enabled(struct pci_bus *bus)
{
	return bus->self && bus->self->ari_enabled;
}

#ifdef CONFIG_PCI_QUIRKS
extern int pci_is_reassigndev(struct pci_dev *dev);
resource_size_t pci_specified_resource_alignment(struct pci_dev *dev);
extern void pci_disable_bridge_window(struct pci_dev *dev);
#endif

/* Single Root I/O Virtualization */
struct pci_sriov {
	int pos;		/* capability position */
	int nres;		/* number of resources */
	u32 cap;		/* SR-IOV Capabilities */
	u16 ctrl;		/* SR-IOV Control */
	u16 total;		/* total VFs associated with the PF */
	u16 initial;		/* initial VFs associated with the PF */
	u16 nr_virtfn;		/* number of VFs available */
	u16 offset;		/* first VF Routing ID offset */
	u16 stride;		/* following VF stride */
	u32 pgsz;		/* page size for BAR alignment */
	u8 link;		/* Function Dependency Link */
	struct pci_dev *dev;	/* lowest numbered PF */
	struct pci_dev *self;	/* this PF */
	struct mutex lock;	/* lock for VF bus */
	struct work_struct mtask; /* VF Migration task */
	u8 __iomem *mstate;	/* VF Migration State Array */
};

/* Address Translation Service */
struct pci_ats {
	int pos;	/* capability position */
	int stu;	/* Smallest Translation Unit */
	int qdep;	/* Invalidate Queue Depth */
	int ref_cnt;	/* Physical Function reference count */
	int is_enabled:1;	/* Enable bit is set */
};

#ifdef CONFIG_PCI_IOV
extern int pci_iov_init(struct pci_dev *dev);
extern void pci_iov_release(struct pci_dev *dev);
extern int pci_iov_resource_bar(struct pci_dev *dev, int resno,
				enum pci_bar_type *type);
extern int pci_sriov_resource_alignment(struct pci_dev *dev, int resno);
extern void pci_restore_iov_state(struct pci_dev *dev);
extern int pci_iov_bus_range(struct pci_bus *bus);

extern int pci_enable_ats(struct pci_dev *dev, int ps);
extern void pci_disable_ats(struct pci_dev *dev);
extern int pci_ats_queue_depth(struct pci_dev *dev);
/**
 * pci_ats_enabled - query the ATS status
 * @dev: the PCI device
 *
 * Returns 1 if ATS capability is enabled, or 0 if not.
 */
static inline int pci_ats_enabled(struct pci_dev *dev)
{
	return dev->ats && dev->ats->is_enabled;
}
#else
static inline int pci_iov_init(struct pci_dev *dev)
{
	return -ENODEV;
}
static inline void pci_iov_release(struct pci_dev *dev)

{
}
static inline int pci_iov_resource_bar(struct pci_dev *dev, int resno,
				       enum pci_bar_type *type)
{
	return 0;
}
static inline void pci_restore_iov_state(struct pci_dev *dev)
{
}
static inline int pci_iov_bus_range(struct pci_bus *bus)
{
	return 0;
}

static inline int pci_enable_ats(struct pci_dev *dev, int ps)
{
	return -ENODEV;
}
static inline void pci_disable_ats(struct pci_dev *dev)
{
}
static inline int pci_ats_queue_depth(struct pci_dev *dev)
{
	return -ENODEV;
}
static inline int pci_ats_enabled(struct pci_dev *dev)
{
	return 0;
}
#endif /* CONFIG_PCI_IOV */

static inline int pci_resource_alignment(struct pci_dev *dev,
					 struct resource *res)
{
#ifdef CONFIG_PCI_IOV
	int resno = res - dev->resource;

	if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END)
		return pci_sriov_resource_alignment(dev, resno);
#endif
	return resource_alignment(res);
}

#endif /* DRIVERS_PCI_H */
Commit	Line	Data
557848c3 ZY	1	#ifndef DRIVERS_PCI_H
	2	#define DRIVERS_PCI_H
	3
74bb1bcc YZ	4	#include <linux/workqueue.h>
74bb1bcc YZ	5
557848c3 ZY	6	#define PCI_CFG_SPACE_SIZE 256
	7	#define PCI_CFG_SPACE_EXP_SIZE 4096
	8
1da177e4 LT	9	/* Functions internal to the PCI core code */
1da177e4 LT	10
7eff2e7a	11	extern int pci_uevent(struct device dev, struct kobj_uevent_env env);
1da177e4 LT	12	extern int pci_create_sysfs_dev_files(struct pci_dev *pdev);
	13	extern void pci_remove_sysfs_dev_files(struct pci_dev *pdev);
	14	extern void pci_cleanup_rom(struct pci_dev *dev);
9eff02e2 JB	15	#ifdef HAVE_PCI_MMAP
	16	extern int pci_mmap_fits(struct pci_dev *pdev, int resno,
	17	struct vm_area_struct *vma);
	18	#endif
711d5779	19	int pci_probe_reset_function(struct pci_dev *dev);
ce5ccdef	20
961d9120	21	/**
b33bfdef	22	* struct pci_platform_pm_ops - Firmware PM callbacks
961d9120	23	*
b33bfdef RD	24	* @is_manageable: returns 'true' if given device is power manageable by the
b33bfdef RD	25	* platform firmware
961d9120	26	*
b33bfdef	27	* @set_state: invokes the platform firmware to set the device's power state
961d9120	28	*
b33bfdef RD	29	* @choose_state: returns PCI power state of given device preferred by the
	30	* platform; to be used during system-wide transitions from a
	31	* sleeping state to the working state and vice versa
961d9120	32	*
b33bfdef RD	33	* @can_wakeup: returns 'true' if given device is capable of waking up the
b33bfdef RD	34	* system from a sleeping state
eb9d0fe4	35	*
b33bfdef	36	* @sleep_wake: enables/disables the system wake up capability of given device
eb9d0fe4	37	*
961d9120 RW	38	* If given platform is generally capable of power managing PCI devices, all of
	39	* these callbacks are mandatory.
	40	*/
	41	struct pci_platform_pm_ops {
	42	bool (is_manageable)(struct pci_dev dev);
	43	int (set_state)(struct pci_dev dev, pci_power_t state);
	44	pci_power_t (choose_state)(struct pci_dev dev);
eb9d0fe4 RW	45	bool (can_wakeup)(struct pci_dev dev);
eb9d0fe4 RW	46	int (sleep_wake)(struct pci_dev dev, bool enable);
961d9120 RW	47	};
	48
	49	extern int pci_set_platform_pm(struct pci_platform_pm_ops *ops);
73410429	50	extern void pci_update_current_state(struct pci_dev *dev, pci_power_t state);
fa58d305	51	extern void pci_disable_enabled_device(struct pci_dev *dev);
eb9d0fe4	52	extern void pci_pm_init(struct pci_dev *dev);
eb9c39d0	53	extern void platform_pci_wakeup_init(struct pci_dev *dev);
63f4898a	54	extern void pci_allocate_cap_save_buffers(struct pci_dev *dev);
aa8c6c93 RW	55
	56	static inline bool pci_is_bridge(struct pci_dev *pci_dev)
	57	{
	58	return !!(pci_dev->subordinate);
	59	}
0f64474b	60
e04b0ea2 BK	61	extern int pci_user_read_config_byte(struct pci_dev dev, int where, u8 val);
	62	extern int pci_user_read_config_word(struct pci_dev dev, int where, u16 val);
	63	extern int pci_user_read_config_dword(struct pci_dev dev, int where, u32 val);
	64	extern int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
	65	extern int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
	66	extern int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
	67
94e61088	68	struct pci_vpd_ops {
287d19ce SH	69	ssize_t (read)(struct pci_dev dev, loff_t pos, size_t count, void *buf);
287d19ce SH	70	ssize_t (write)(struct pci_dev dev, loff_t pos, size_t count, const void *buf);
94e61088 BH	71	void (release)(struct pci_dev dev);
	72	};
	73
	74	struct pci_vpd {
99cb233d	75	unsigned int len;
287d19ce	76	const struct pci_vpd_ops *ops;
94e61088 BH	77	struct bin_attribute attr; / descriptor for sysfs VPD entry */
	78	};
	79
	80	extern int pci_vpd_pci22_init(struct pci_dev *dev);
	81	static inline void pci_vpd_release(struct pci_dev *dev)
	82	{
	83	if (dev->vpd)
	84	dev->vpd->ops->release(dev);
	85	}
	86
1da177e4 LT	87	/* PCI /proc functions */
	88	#ifdef CONFIG_PROC_FS
	89	extern int pci_proc_attach_device(struct pci_dev *dev);
	90	extern int pci_proc_detach_device(struct pci_dev *dev);
1da177e4 LT	91	extern int pci_proc_detach_bus(struct pci_bus *bus);
	92	#else
	93	static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; }
	94	static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; }
1da177e4 LT	95	static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; }
	96	#endif
	97
	98	/* Functions for PCI Hotplug drivers to use */
1da177e4	99	extern unsigned int pci_do_scan_bus(struct pci_bus *bus);
1da177e4	100
f19aeb1f BH	101	#ifdef HAVE_PCI_LEGACY
f19aeb1f BH	102	extern void pci_create_legacy_files(struct pci_bus *bus);
1da177e4	103	extern void pci_remove_legacy_files(struct pci_bus *bus);
f19aeb1f BH	104	#else
	105	static inline void pci_create_legacy_files(struct pci_bus *bus) { return; }
	106	static inline void pci_remove_legacy_files(struct pci_bus *bus) { return; }
	107	#endif
1da177e4 LT	108
1da177e4 LT	109	/* Lock for read/write access to pci device and bus lists */
d71374da	110	extern struct rw_semaphore pci_bus_sem;
1da177e4	111
ffadcc2f	112	extern unsigned int pci_pm_d3_delay;
88187dfa	113
4b47b0ee	114	#ifdef CONFIG_PCI_MSI
309e57df	115	void pci_no_msi(void);
4aa9bc95	116	extern void pci_msi_init_pci_dev(struct pci_dev *dev);
4b47b0ee	117	#else
309e57df	118	static inline void pci_no_msi(void) { }
4aa9bc95	119	static inline void pci_msi_init_pci_dev(struct pci_dev *dev) { }
4b47b0ee	120	#endif
8fed4b65	121
7f785763 RD	122	#ifdef CONFIG_PCIEAER
	123	void pci_no_aer(void);
	124	#else
	125	static inline void pci_no_aer(void) { }
	126	#endif
	127
ffadcc2f KCA	128	static inline int pci_no_d1d2(struct pci_dev *dev)
	129	{
	130	unsigned int parent_dstates = 0;
4b47b0ee	131
ffadcc2f KCA	132	if (dev->bus->self)
	133	parent_dstates = dev->bus->self->no_d1d2;
	134	return (dev->no_d1d2 \|\| parent_dstates);
	135
	136	}
1da177e4	137	extern struct device_attribute pci_dev_attrs[];
fd7d1ced	138	extern struct device_attribute dev_attr_cpuaffinity;
93ff68a5	139	extern struct device_attribute dev_attr_cpulistaffinity;
705b1aaa AC	140	#ifdef CONFIG_HOTPLUG
	141	extern struct bus_attribute pci_bus_attrs[];
	142	#else
	143	#define pci_bus_attrs NULL
	144	#endif
	145
1da177e4 LT	146
	147	/**
	148	* pci_match_one_device - Tell if a PCI device structure has a matching
	149	* PCI device id structure
	150	* @id: single PCI device id structure to match
	151	* @dev: the PCI device structure to match against
367b09fe	152	*
1da177e4 LT	153	* Returns the matching pci_device_id structure or %NULL if there is no match.
	154	*/
	155	static inline const struct pci_device_id *
	156	pci_match_one_device(const struct pci_device_id id, const struct pci_dev dev)
	157	{
	158	if ((id->vendor == PCI_ANY_ID \|\| id->vendor == dev->vendor) &&
	159	(id->device == PCI_ANY_ID \|\| id->device == dev->device) &&
	160	(id->subvendor == PCI_ANY_ID \|\| id->subvendor == dev->subsystem_vendor) &&
	161	(id->subdevice == PCI_ANY_ID \|\| id->subdevice == dev->subsystem_device) &&
	162	!((id->class ^ dev->class) & id->class_mask))
	163	return id;
	164	return NULL;
	165	}
	166
994a65e2	167	struct pci_dev pci_find_upstream_pcie_bridge(struct pci_dev pdev);
f46753c5 AC	168
	169	/* PCI slot sysfs helper code */
	170	#define to_pci_slot(s) container_of(s, struct pci_slot, kobj)
	171
	172	extern struct kset *pci_slots_kset;
	173
	174	struct pci_slot_attribute {
	175	struct attribute attr;
	176	ssize_t (show)(struct pci_slot , char *);
	177	ssize_t (store)(struct pci_slot , const char *, size_t);
	178	};
	179	#define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr)
	180
0b400c7e YZ	181	enum pci_bar_type {
	182	pci_bar_unknown, /* Standard PCI BAR probe */
	183	pci_bar_io, /* An io port BAR */
	184	pci_bar_mem32, /* A 32-bit memory BAR */
	185	pci_bar_mem64, /* A 64-bit memory BAR */
	186	};
	187
480b93b7	188	extern int pci_setup_device(struct pci_dev *dev);
0b400c7e YZ	189	extern int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
0b400c7e YZ	190	struct resource *res, unsigned int reg);
613e7ed6 YZ	191	extern int pci_resource_bar(struct pci_dev *dev, int resno,
613e7ed6 YZ	192	enum pci_bar_type *type);
876e501a	193	extern int pci_bus_add_child(struct pci_bus *bus);
58c3a727 YZ	194	extern void pci_enable_ari(struct pci_dev *dev);
	195	/**
	196	* pci_ari_enabled - query ARI forwarding status
6a49d812	197	* @bus: the PCI bus
58c3a727 YZ	198	*
	199	* Returns 1 if ARI forwarding is enabled, or 0 if not enabled;
	200	*/
6a49d812	201	static inline int pci_ari_enabled(struct pci_bus *bus)
58c3a727	202	{
6a49d812	203	return bus->self && bus->self->ari_enabled;
58c3a727 YZ	204	}
58c3a727 YZ	205
32a9a682 YS	206	#ifdef CONFIG_PCI_QUIRKS
	207	extern int pci_is_reassigndev(struct pci_dev *dev);
	208	resource_size_t pci_specified_resource_alignment(struct pci_dev *dev);
	209	extern void pci_disable_bridge_window(struct pci_dev *dev);
	210	#endif
	211
d1b054da YZ	212	/* Single Root I/O Virtualization */
	213	struct pci_sriov {
	214	int pos; /* capability position */
	215	int nres; /* number of resources */
	216	u32 cap; /* SR-IOV Capabilities */
	217	u16 ctrl; /* SR-IOV Control */
	218	u16 total; /* total VFs associated with the PF */
dd7cc44d YZ	219	u16 initial; /* initial VFs associated with the PF */
dd7cc44d YZ	220	u16 nr_virtfn; /* number of VFs available */
d1b054da YZ	221	u16 offset; /* first VF Routing ID offset */
	222	u16 stride; /* following VF stride */
	223	u32 pgsz; /* page size for BAR alignment */
	224	u8 link; /* Function Dependency Link */
	225	struct pci_dev dev; / lowest numbered PF */
	226	struct pci_dev self; / this PF */
	227	struct mutex lock; /* lock for VF bus */
74bb1bcc YZ	228	struct work_struct mtask; /* VF Migration task */
74bb1bcc YZ	229	u8 __iomem mstate; / VF Migration State Array */
d1b054da YZ	230	};
d1b054da YZ	231
302b4215 YZ	232	/* Address Translation Service */
	233	struct pci_ats {
	234	int pos; /* capability position */
	235	int stu; /* Smallest Translation Unit */
	236	int qdep; /* Invalidate Queue Depth */
e277d2fc YZ	237	int ref_cnt; /* Physical Function reference count */
e277d2fc YZ	238	int is_enabled:1; /* Enable bit is set */
302b4215 YZ	239	};
302b4215 YZ	240
d1b054da YZ	241	#ifdef CONFIG_PCI_IOV
	242	extern int pci_iov_init(struct pci_dev *dev);
	243	extern void pci_iov_release(struct pci_dev *dev);
	244	extern int pci_iov_resource_bar(struct pci_dev *dev, int resno,
	245	enum pci_bar_type *type);
6faf17f6	246	extern int pci_sriov_resource_alignment(struct pci_dev *dev, int resno);
8c5cdb6a	247	extern void pci_restore_iov_state(struct pci_dev *dev);
a28724b0	248	extern int pci_iov_bus_range(struct pci_bus *bus);
302b4215 YZ	249
	250	extern int pci_enable_ats(struct pci_dev *dev, int ps);
	251	extern void pci_disable_ats(struct pci_dev *dev);
	252	extern int pci_ats_queue_depth(struct pci_dev *dev);
	253	/**
	254	* pci_ats_enabled - query the ATS status
	255	* @dev: the PCI device
	256	*
	257	* Returns 1 if ATS capability is enabled, or 0 if not.
	258	*/
	259	static inline int pci_ats_enabled(struct pci_dev *dev)
	260	{
e277d2fc	261	return dev->ats && dev->ats->is_enabled;
302b4215	262	}
d1b054da YZ	263	#else
	264	static inline int pci_iov_init(struct pci_dev *dev)
	265	{
	266	return -ENODEV;
	267	}
	268	static inline void pci_iov_release(struct pci_dev *dev)
	269
	270	{
	271	}
	272	static inline int pci_iov_resource_bar(struct pci_dev *dev, int resno,
	273	enum pci_bar_type *type)
	274	{
	275	return 0;
	276	}
8c5cdb6a YZ	277	static inline void pci_restore_iov_state(struct pci_dev *dev)
	278	{
	279	}
a28724b0 YZ	280	static inline int pci_iov_bus_range(struct pci_bus *bus)
	281	{
	282	return 0;
	283	}
302b4215 YZ	284
	285	static inline int pci_enable_ats(struct pci_dev *dev, int ps)
	286	{
	287	return -ENODEV;
	288	}
	289	static inline void pci_disable_ats(struct pci_dev *dev)
	290	{
	291	}
	292	static inline int pci_ats_queue_depth(struct pci_dev *dev)
	293	{
	294	return -ENODEV;
	295	}
	296	static inline int pci_ats_enabled(struct pci_dev *dev)
	297	{
	298	return 0;
	299	}
d1b054da YZ	300	#endif /* CONFIG_PCI_IOV */
d1b054da YZ	301
6faf17f6 CW	302	static inline int pci_resource_alignment(struct pci_dev *dev,
	303	struct resource *res)
	304	{
	305	#ifdef CONFIG_PCI_IOV
	306	int resno = res - dev->resource;
	307
	308	if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END)
	309	return pci_sriov_resource_alignment(dev, resno);
	310	#endif
	311	return resource_alignment(res);
	312	}
	313
557848c3	314	#endif /* DRIVERS_PCI_H */