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Commit | Line | Data |
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c767a54b | 1 | /* |
4cedb334 GOC |
2 | * x86 SMP booting functions |
3 | * | |
87c6fe26 | 4 | * (c) 1995 Alan Cox, Building #3 <[email protected]> |
8f47e163 | 5 | * (c) 1998, 1999, 2000, 2009 Ingo Molnar <[email protected]> |
4cedb334 GOC |
6 | * Copyright 2001 Andi Kleen, SuSE Labs. |
7 | * | |
8 | * Much of the core SMP work is based on previous work by Thomas Radke, to | |
9 | * whom a great many thanks are extended. | |
10 | * | |
11 | * Thanks to Intel for making available several different Pentium, | |
12 | * Pentium Pro and Pentium-II/Xeon MP machines. | |
13 | * Original development of Linux SMP code supported by Caldera. | |
14 | * | |
15 | * This code is released under the GNU General Public License version 2 or | |
16 | * later. | |
17 | * | |
18 | * Fixes | |
19 | * Felix Koop : NR_CPUS used properly | |
20 | * Jose Renau : Handle single CPU case. | |
21 | * Alan Cox : By repeated request 8) - Total BogoMIPS report. | |
22 | * Greg Wright : Fix for kernel stacks panic. | |
23 | * Erich Boleyn : MP v1.4 and additional changes. | |
24 | * Matthias Sattler : Changes for 2.1 kernel map. | |
25 | * Michel Lespinasse : Changes for 2.1 kernel map. | |
26 | * Michael Chastain : Change trampoline.S to gnu as. | |
27 | * Alan Cox : Dumb bug: 'B' step PPro's are fine | |
28 | * Ingo Molnar : Added APIC timers, based on code | |
29 | * from Jose Renau | |
30 | * Ingo Molnar : various cleanups and rewrites | |
31 | * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. | |
32 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs | |
33 | * Andi Kleen : Changed for SMP boot into long mode. | |
34 | * Martin J. Bligh : Added support for multi-quad systems | |
35 | * Dave Jones : Report invalid combinations of Athlon CPUs. | |
36 | * Rusty Russell : Hacked into shape for new "hotplug" boot process. | |
37 | * Andi Kleen : Converted to new state machine. | |
38 | * Ashok Raj : CPU hotplug support | |
39 | * Glauber Costa : i386 and x86_64 integration | |
40 | */ | |
41 | ||
c767a54b JP |
42 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
43 | ||
68a1c3f8 GC |
44 | #include <linux/init.h> |
45 | #include <linux/smp.h> | |
186f4360 | 46 | #include <linux/export.h> |
70708a18 | 47 | #include <linux/sched.h> |
69c18c15 | 48 | #include <linux/percpu.h> |
91718e8d | 49 | #include <linux/bootmem.h> |
cb3c8b90 GOC |
50 | #include <linux/err.h> |
51 | #include <linux/nmi.h> | |
69575d38 | 52 | #include <linux/tboot.h> |
35f720c5 | 53 | #include <linux/stackprotector.h> |
5a0e3ad6 | 54 | #include <linux/gfp.h> |
1a022e3f | 55 | #include <linux/cpuidle.h> |
69c18c15 | 56 | |
8aef135c | 57 | #include <asm/acpi.h> |
cb3c8b90 | 58 | #include <asm/desc.h> |
69c18c15 GC |
59 | #include <asm/nmi.h> |
60 | #include <asm/irq.h> | |
48927bbb | 61 | #include <asm/realmode.h> |
69c18c15 GC |
62 | #include <asm/cpu.h> |
63 | #include <asm/numa.h> | |
cb3c8b90 GOC |
64 | #include <asm/pgtable.h> |
65 | #include <asm/tlbflush.h> | |
66 | #include <asm/mtrr.h> | |
ea530692 | 67 | #include <asm/mwait.h> |
7b6aa335 | 68 | #include <asm/apic.h> |
7167d08e | 69 | #include <asm/io_apic.h> |
78f7f1e5 | 70 | #include <asm/fpu/internal.h> |
569712b2 | 71 | #include <asm/setup.h> |
bdbcdd48 | 72 | #include <asm/uv/uv.h> |
cb3c8b90 | 73 | #include <linux/mc146818rtc.h> |
b81bb373 | 74 | #include <asm/i8259.h> |
48927bbb | 75 | #include <asm/realmode.h> |
646e29a1 | 76 | #include <asm/misc.h> |
48927bbb | 77 | |
a355352b GC |
78 | /* Number of siblings per CPU package */ |
79 | int smp_num_siblings = 1; | |
80 | EXPORT_SYMBOL(smp_num_siblings); | |
81 | ||
82 | /* Last level cache ID of each logical CPU */ | |
0816b0f0 | 83 | DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) = BAD_APICID; |
a355352b | 84 | |
a355352b | 85 | /* representing HT siblings of each logical CPU */ |
0816b0f0 | 86 | DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map); |
a355352b GC |
87 | EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); |
88 | ||
89 | /* representing HT and core siblings of each logical CPU */ | |
0816b0f0 | 90 | DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map); |
a355352b GC |
91 | EXPORT_PER_CPU_SYMBOL(cpu_core_map); |
92 | ||
0816b0f0 | 93 | DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_llc_shared_map); |
b3d7336d | 94 | |
a355352b | 95 | /* Per CPU bogomips and other parameters */ |
2c773dd3 | 96 | DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info); |
a355352b | 97 | EXPORT_PER_CPU_SYMBOL(cpu_info); |
768d9505 | 98 | |
1f12e32f TG |
99 | /* Logical package management. We might want to allocate that dynamically */ |
100 | static int *physical_to_logical_pkg __read_mostly; | |
101 | static unsigned long *physical_package_map __read_mostly;; | |
1f12e32f TG |
102 | static unsigned int max_physical_pkg_id __read_mostly; |
103 | unsigned int __max_logical_packages __read_mostly; | |
104 | EXPORT_SYMBOL(__max_logical_packages); | |
7b0501b1 | 105 | static unsigned int logical_packages __read_mostly; |
1f12e32f | 106 | |
70b8301f AK |
107 | /* Maximum number of SMT threads on any online core */ |
108 | int __max_smt_threads __read_mostly; | |
109 | ||
7d25127c TC |
110 | /* Flag to indicate if a complete sched domain rebuild is required */ |
111 | bool x86_topology_update; | |
112 | ||
113 | int arch_update_cpu_topology(void) | |
114 | { | |
115 | int retval = x86_topology_update; | |
116 | ||
117 | x86_topology_update = false; | |
118 | return retval; | |
119 | } | |
120 | ||
f77aa308 TG |
121 | static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip) |
122 | { | |
123 | unsigned long flags; | |
124 | ||
125 | spin_lock_irqsave(&rtc_lock, flags); | |
126 | CMOS_WRITE(0xa, 0xf); | |
127 | spin_unlock_irqrestore(&rtc_lock, flags); | |
128 | local_flush_tlb(); | |
129 | pr_debug("1.\n"); | |
130 | *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) = | |
131 | start_eip >> 4; | |
132 | pr_debug("2.\n"); | |
133 | *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = | |
134 | start_eip & 0xf; | |
135 | pr_debug("3.\n"); | |
136 | } | |
137 | ||
138 | static inline void smpboot_restore_warm_reset_vector(void) | |
139 | { | |
140 | unsigned long flags; | |
141 | ||
142 | /* | |
143 | * Install writable page 0 entry to set BIOS data area. | |
144 | */ | |
145 | local_flush_tlb(); | |
146 | ||
147 | /* | |
148 | * Paranoid: Set warm reset code and vector here back | |
149 | * to default values. | |
150 | */ | |
151 | spin_lock_irqsave(&rtc_lock, flags); | |
152 | CMOS_WRITE(0, 0xf); | |
153 | spin_unlock_irqrestore(&rtc_lock, flags); | |
154 | ||
155 | *((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0; | |
156 | } | |
157 | ||
cb3c8b90 | 158 | /* |
30106c17 FY |
159 | * Report back to the Boot Processor during boot time or to the caller processor |
160 | * during CPU online. | |
cb3c8b90 | 161 | */ |
148f9bb8 | 162 | static void smp_callin(void) |
cb3c8b90 GOC |
163 | { |
164 | int cpuid, phys_id; | |
cb3c8b90 GOC |
165 | |
166 | /* | |
167 | * If waken up by an INIT in an 82489DX configuration | |
656bba30 LB |
168 | * cpu_callout_mask guarantees we don't get here before |
169 | * an INIT_deassert IPI reaches our local APIC, so it is | |
170 | * now safe to touch our local APIC. | |
cb3c8b90 | 171 | */ |
e1c467e6 | 172 | cpuid = smp_processor_id(); |
cb3c8b90 GOC |
173 | |
174 | /* | |
175 | * (This works even if the APIC is not enabled.) | |
176 | */ | |
4c9961d5 | 177 | phys_id = read_apic_id(); |
cb3c8b90 GOC |
178 | |
179 | /* | |
180 | * the boot CPU has finished the init stage and is spinning | |
181 | * on callin_map until we finish. We are free to set up this | |
182 | * CPU, first the APIC. (this is probably redundant on most | |
183 | * boards) | |
184 | */ | |
05f7e46d | 185 | apic_ap_setup(); |
cb3c8b90 | 186 | |
b565201c JS |
187 | /* |
188 | * Save our processor parameters. Note: this information | |
189 | * is needed for clock calibration. | |
190 | */ | |
191 | smp_store_cpu_info(cpuid); | |
192 | ||
cb3c8b90 GOC |
193 | /* |
194 | * Get our bogomips. | |
b565201c JS |
195 | * Update loops_per_jiffy in cpu_data. Previous call to |
196 | * smp_store_cpu_info() stored a value that is close but not as | |
197 | * accurate as the value just calculated. | |
cb3c8b90 | 198 | */ |
cb3c8b90 | 199 | calibrate_delay(); |
b565201c | 200 | cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy; |
cfc1b9a6 | 201 | pr_debug("Stack at about %p\n", &cpuid); |
cb3c8b90 | 202 | |
5ef428c4 AK |
203 | /* |
204 | * This must be done before setting cpu_online_mask | |
205 | * or calling notify_cpu_starting. | |
206 | */ | |
207 | set_cpu_sibling_map(raw_smp_processor_id()); | |
208 | wmb(); | |
209 | ||
85257024 PZ |
210 | notify_cpu_starting(cpuid); |
211 | ||
cb3c8b90 GOC |
212 | /* |
213 | * Allow the master to continue. | |
214 | */ | |
c2d1cec1 | 215 | cpumask_set_cpu(cpuid, cpu_callin_mask); |
cb3c8b90 GOC |
216 | } |
217 | ||
e1c467e6 FY |
218 | static int cpu0_logical_apicid; |
219 | static int enable_start_cpu0; | |
bbc2ff6a GOC |
220 | /* |
221 | * Activate a secondary processor. | |
222 | */ | |
148f9bb8 | 223 | static void notrace start_secondary(void *unused) |
bbc2ff6a GOC |
224 | { |
225 | /* | |
226 | * Don't put *anything* before cpu_init(), SMP booting is too | |
227 | * fragile that we want to limit the things done here to the | |
228 | * most necessary things. | |
229 | */ | |
b40827fa | 230 | cpu_init(); |
df156f90 | 231 | x86_cpuinit.early_percpu_clock_init(); |
b40827fa BP |
232 | preempt_disable(); |
233 | smp_callin(); | |
fd89a137 | 234 | |
e1c467e6 FY |
235 | enable_start_cpu0 = 0; |
236 | ||
fd89a137 | 237 | #ifdef CONFIG_X86_32 |
b40827fa | 238 | /* switch away from the initial page table */ |
fd89a137 JR |
239 | load_cr3(swapper_pg_dir); |
240 | __flush_tlb_all(); | |
241 | #endif | |
242 | ||
bbc2ff6a GOC |
243 | /* otherwise gcc will move up smp_processor_id before the cpu_init */ |
244 | barrier(); | |
245 | /* | |
246 | * Check TSC synchronization with the BP: | |
247 | */ | |
248 | check_tsc_sync_target(); | |
249 | ||
bbc2ff6a | 250 | /* |
5a3f75e3 TG |
251 | * Lock vector_lock and initialize the vectors on this cpu |
252 | * before setting the cpu online. We must set it online with | |
253 | * vector_lock held to prevent a concurrent setup/teardown | |
254 | * from seeing a half valid vector space. | |
bbc2ff6a | 255 | */ |
d388e5fd | 256 | lock_vector_lock(); |
5a3f75e3 | 257 | setup_vector_irq(smp_processor_id()); |
c2d1cec1 | 258 | set_cpu_online(smp_processor_id(), true); |
d388e5fd | 259 | unlock_vector_lock(); |
2a442c9c | 260 | cpu_set_state_online(smp_processor_id()); |
78c06176 | 261 | x86_platform.nmi_init(); |
bbc2ff6a | 262 | |
0cefa5b9 MS |
263 | /* enable local interrupts */ |
264 | local_irq_enable(); | |
265 | ||
35f720c5 JP |
266 | /* to prevent fake stack check failure in clock setup */ |
267 | boot_init_stack_canary(); | |
0cefa5b9 | 268 | |
736decac | 269 | x86_cpuinit.setup_percpu_clockev(); |
bbc2ff6a GOC |
270 | |
271 | wmb(); | |
fc6d73d6 | 272 | cpu_startup_entry(CPUHP_AP_ONLINE_IDLE); |
bbc2ff6a GOC |
273 | } |
274 | ||
9d85eb91 TG |
275 | /** |
276 | * topology_update_package_map - Update the physical to logical package map | |
277 | * @pkg: The physical package id as retrieved via CPUID | |
278 | * @cpu: The cpu for which this is updated | |
279 | */ | |
280 | int topology_update_package_map(unsigned int pkg, unsigned int cpu) | |
1f12e32f | 281 | { |
9d85eb91 | 282 | unsigned int new; |
1f12e32f TG |
283 | |
284 | /* Called from early boot ? */ | |
285 | if (!physical_package_map) | |
286 | return 0; | |
287 | ||
288 | if (pkg >= max_physical_pkg_id) | |
289 | return -EINVAL; | |
290 | ||
291 | /* Set the logical package id */ | |
292 | if (test_and_set_bit(pkg, physical_package_map)) | |
293 | goto found; | |
294 | ||
9d85eb91 TG |
295 | if (logical_packages >= __max_logical_packages) { |
296 | pr_warn("Package %u of CPU %u exceeds BIOS package data %u.\n", | |
297 | logical_packages, cpu, __max_logical_packages); | |
1f12e32f TG |
298 | return -ENOSPC; |
299 | } | |
7b0501b1 JO |
300 | |
301 | new = logical_packages++; | |
9d85eb91 TG |
302 | if (new != pkg) { |
303 | pr_info("CPU %u Converting physical %u to logical package %u\n", | |
304 | cpu, pkg, new); | |
305 | } | |
1f12e32f TG |
306 | physical_to_logical_pkg[pkg] = new; |
307 | ||
308 | found: | |
309 | cpu_data(cpu).logical_proc_id = physical_to_logical_pkg[pkg]; | |
310 | return 0; | |
311 | } | |
312 | ||
313 | /** | |
314 | * topology_phys_to_logical_pkg - Map a physical package id to a logical | |
315 | * | |
316 | * Returns logical package id or -1 if not found | |
317 | */ | |
318 | int topology_phys_to_logical_pkg(unsigned int phys_pkg) | |
319 | { | |
320 | if (phys_pkg >= max_physical_pkg_id) | |
321 | return -1; | |
322 | return physical_to_logical_pkg[phys_pkg]; | |
323 | } | |
324 | EXPORT_SYMBOL(topology_phys_to_logical_pkg); | |
325 | ||
9d85eb91 | 326 | static void __init smp_init_package_map(struct cpuinfo_x86 *c, unsigned int cpu) |
1f12e32f | 327 | { |
9d85eb91 | 328 | unsigned int ncpus; |
1f12e32f TG |
329 | size_t size; |
330 | ||
331 | /* | |
332 | * Today neither Intel nor AMD support heterogenous systems. That | |
333 | * might change in the future.... | |
63d1e995 PZ |
334 | * |
335 | * While ideally we'd want '* smp_num_siblings' in the below @ncpus | |
336 | * computation, this won't actually work since some Intel BIOSes | |
337 | * report inconsistent HT data when they disable HT. | |
338 | * | |
339 | * In particular, they reduce the APIC-IDs to only include the cores, | |
340 | * but leave the CPUID topology to say there are (2) siblings. | |
341 | * This means we don't know how many threads there will be until | |
342 | * after the APIC enumeration. | |
343 | * | |
344 | * By not including this we'll sometimes over-estimate the number of | |
345 | * logical packages by the amount of !present siblings, but this is | |
346 | * still better than MAX_LOCAL_APIC. | |
3e8db224 TG |
347 | * |
348 | * We use total_cpus not nr_cpu_ids because nr_cpu_ids can be limited | |
349 | * on the command line leading to a similar issue as the HT disable | |
350 | * problem because the hyperthreads are usually enumerated after the | |
351 | * primary cores. | |
1f12e32f | 352 | */ |
63d1e995 | 353 | ncpus = boot_cpu_data.x86_max_cores; |
56402d63 TG |
354 | if (!ncpus) { |
355 | pr_warn("x86_max_cores == zero !?!?"); | |
356 | ncpus = 1; | |
357 | } | |
358 | ||
3e8db224 | 359 | __max_logical_packages = DIV_ROUND_UP(total_cpus, ncpus); |
7b0501b1 | 360 | logical_packages = 0; |
1f12e32f TG |
361 | |
362 | /* | |
363 | * Possibly larger than what we need as the number of apic ids per | |
364 | * package can be smaller than the actual used apic ids. | |
365 | */ | |
366 | max_physical_pkg_id = DIV_ROUND_UP(MAX_LOCAL_APIC, ncpus); | |
367 | size = max_physical_pkg_id * sizeof(unsigned int); | |
368 | physical_to_logical_pkg = kmalloc(size, GFP_KERNEL); | |
369 | memset(physical_to_logical_pkg, 0xff, size); | |
370 | size = BITS_TO_LONGS(max_physical_pkg_id) * sizeof(unsigned long); | |
371 | physical_package_map = kzalloc(size, GFP_KERNEL); | |
1f12e32f | 372 | |
7b0501b1 | 373 | pr_info("Max logical packages: %u\n", __max_logical_packages); |
9d85eb91 TG |
374 | |
375 | topology_update_package_map(c->phys_proc_id, cpu); | |
1f12e32f TG |
376 | } |
377 | ||
30106c17 FY |
378 | void __init smp_store_boot_cpu_info(void) |
379 | { | |
380 | int id = 0; /* CPU 0 */ | |
381 | struct cpuinfo_x86 *c = &cpu_data(id); | |
382 | ||
383 | *c = boot_cpu_data; | |
384 | c->cpu_index = id; | |
9d85eb91 | 385 | smp_init_package_map(c, id); |
30106c17 FY |
386 | } |
387 | ||
1d89a7f0 GOC |
388 | /* |
389 | * The bootstrap kernel entry code has set these up. Save them for | |
390 | * a given CPU | |
391 | */ | |
148f9bb8 | 392 | void smp_store_cpu_info(int id) |
1d89a7f0 GOC |
393 | { |
394 | struct cpuinfo_x86 *c = &cpu_data(id); | |
395 | ||
b3d7336d | 396 | *c = boot_cpu_data; |
1d89a7f0 | 397 | c->cpu_index = id; |
30106c17 FY |
398 | /* |
399 | * During boot time, CPU0 has this setup already. Save the info when | |
400 | * bringing up AP or offlined CPU0. | |
401 | */ | |
402 | identify_secondary_cpu(c); | |
1d89a7f0 GOC |
403 | } |
404 | ||
cebf15eb DH |
405 | static bool |
406 | topology_same_node(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) | |
407 | { | |
408 | int cpu1 = c->cpu_index, cpu2 = o->cpu_index; | |
409 | ||
410 | return (cpu_to_node(cpu1) == cpu_to_node(cpu2)); | |
411 | } | |
412 | ||
148f9bb8 | 413 | static bool |
316ad248 | 414 | topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name) |
d4fbe4f0 | 415 | { |
316ad248 PZ |
416 | int cpu1 = c->cpu_index, cpu2 = o->cpu_index; |
417 | ||
cebf15eb | 418 | return !WARN_ONCE(!topology_same_node(c, o), |
316ad248 PZ |
419 | "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! " |
420 | "[node: %d != %d]. Ignoring dependency.\n", | |
421 | cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2)); | |
422 | } | |
423 | ||
7d79a7bd | 424 | #define link_mask(mfunc, c1, c2) \ |
316ad248 | 425 | do { \ |
7d79a7bd BG |
426 | cpumask_set_cpu((c1), mfunc(c2)); \ |
427 | cpumask_set_cpu((c2), mfunc(c1)); \ | |
316ad248 PZ |
428 | } while (0) |
429 | ||
148f9bb8 | 430 | static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) |
316ad248 | 431 | { |
362f924b | 432 | if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { |
316ad248 PZ |
433 | int cpu1 = c->cpu_index, cpu2 = o->cpu_index; |
434 | ||
435 | if (c->phys_proc_id == o->phys_proc_id && | |
436 | per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2) && | |
8196dab4 | 437 | c->cpu_core_id == o->cpu_core_id) |
316ad248 PZ |
438 | return topology_sane(c, o, "smt"); |
439 | ||
440 | } else if (c->phys_proc_id == o->phys_proc_id && | |
441 | c->cpu_core_id == o->cpu_core_id) { | |
442 | return topology_sane(c, o, "smt"); | |
443 | } | |
444 | ||
445 | return false; | |
446 | } | |
447 | ||
148f9bb8 | 448 | static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) |
316ad248 PZ |
449 | { |
450 | int cpu1 = c->cpu_index, cpu2 = o->cpu_index; | |
451 | ||
452 | if (per_cpu(cpu_llc_id, cpu1) != BAD_APICID && | |
453 | per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2)) | |
454 | return topology_sane(c, o, "llc"); | |
455 | ||
456 | return false; | |
d4fbe4f0 AH |
457 | } |
458 | ||
cebf15eb DH |
459 | /* |
460 | * Unlike the other levels, we do not enforce keeping a | |
461 | * multicore group inside a NUMA node. If this happens, we will | |
462 | * discard the MC level of the topology later. | |
463 | */ | |
464 | static bool match_die(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) | |
316ad248 | 465 | { |
cebf15eb DH |
466 | if (c->phys_proc_id == o->phys_proc_id) |
467 | return true; | |
316ad248 PZ |
468 | return false; |
469 | } | |
1d89a7f0 | 470 | |
d3d37d85 TC |
471 | #if defined(CONFIG_SCHED_SMT) || defined(CONFIG_SCHED_MC) |
472 | static inline int x86_sched_itmt_flags(void) | |
473 | { | |
474 | return sysctl_sched_itmt_enabled ? SD_ASYM_PACKING : 0; | |
475 | } | |
476 | ||
477 | #ifdef CONFIG_SCHED_MC | |
478 | static int x86_core_flags(void) | |
479 | { | |
480 | return cpu_core_flags() | x86_sched_itmt_flags(); | |
481 | } | |
482 | #endif | |
483 | #ifdef CONFIG_SCHED_SMT | |
484 | static int x86_smt_flags(void) | |
485 | { | |
486 | return cpu_smt_flags() | x86_sched_itmt_flags(); | |
487 | } | |
488 | #endif | |
489 | #endif | |
490 | ||
8f37961c | 491 | static struct sched_domain_topology_level x86_numa_in_package_topology[] = { |
cebf15eb | 492 | #ifdef CONFIG_SCHED_SMT |
d3d37d85 | 493 | { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) }, |
cebf15eb DH |
494 | #endif |
495 | #ifdef CONFIG_SCHED_MC | |
d3d37d85 | 496 | { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) }, |
cebf15eb DH |
497 | #endif |
498 | { NULL, }, | |
499 | }; | |
8f37961c TC |
500 | |
501 | static struct sched_domain_topology_level x86_topology[] = { | |
502 | #ifdef CONFIG_SCHED_SMT | |
d3d37d85 | 503 | { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) }, |
8f37961c TC |
504 | #endif |
505 | #ifdef CONFIG_SCHED_MC | |
d3d37d85 | 506 | { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) }, |
8f37961c TC |
507 | #endif |
508 | { cpu_cpu_mask, SD_INIT_NAME(DIE) }, | |
509 | { NULL, }, | |
510 | }; | |
511 | ||
cebf15eb | 512 | /* |
8f37961c TC |
513 | * Set if a package/die has multiple NUMA nodes inside. |
514 | * AMD Magny-Cours and Intel Cluster-on-Die have this. | |
cebf15eb | 515 | */ |
8f37961c | 516 | static bool x86_has_numa_in_package; |
cebf15eb | 517 | |
148f9bb8 | 518 | void set_cpu_sibling_map(int cpu) |
768d9505 | 519 | { |
316ad248 | 520 | bool has_smt = smp_num_siblings > 1; |
b0bc225d | 521 | bool has_mp = has_smt || boot_cpu_data.x86_max_cores > 1; |
768d9505 | 522 | struct cpuinfo_x86 *c = &cpu_data(cpu); |
316ad248 | 523 | struct cpuinfo_x86 *o; |
70b8301f | 524 | int i, threads; |
768d9505 | 525 | |
c2d1cec1 | 526 | cpumask_set_cpu(cpu, cpu_sibling_setup_mask); |
768d9505 | 527 | |
b0bc225d | 528 | if (!has_mp) { |
7d79a7bd | 529 | cpumask_set_cpu(cpu, topology_sibling_cpumask(cpu)); |
316ad248 | 530 | cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu)); |
7d79a7bd | 531 | cpumask_set_cpu(cpu, topology_core_cpumask(cpu)); |
768d9505 GC |
532 | c->booted_cores = 1; |
533 | return; | |
534 | } | |
535 | ||
c2d1cec1 | 536 | for_each_cpu(i, cpu_sibling_setup_mask) { |
316ad248 PZ |
537 | o = &cpu_data(i); |
538 | ||
539 | if ((i == cpu) || (has_smt && match_smt(c, o))) | |
7d79a7bd | 540 | link_mask(topology_sibling_cpumask, cpu, i); |
316ad248 | 541 | |
b0bc225d | 542 | if ((i == cpu) || (has_mp && match_llc(c, o))) |
7d79a7bd | 543 | link_mask(cpu_llc_shared_mask, cpu, i); |
316ad248 | 544 | |
ceb1cbac KB |
545 | } |
546 | ||
547 | /* | |
548 | * This needs a separate iteration over the cpus because we rely on all | |
7d79a7bd | 549 | * topology_sibling_cpumask links to be set-up. |
ceb1cbac KB |
550 | */ |
551 | for_each_cpu(i, cpu_sibling_setup_mask) { | |
552 | o = &cpu_data(i); | |
553 | ||
cebf15eb | 554 | if ((i == cpu) || (has_mp && match_die(c, o))) { |
7d79a7bd | 555 | link_mask(topology_core_cpumask, cpu, i); |
316ad248 | 556 | |
768d9505 GC |
557 | /* |
558 | * Does this new cpu bringup a new core? | |
559 | */ | |
7d79a7bd BG |
560 | if (cpumask_weight( |
561 | topology_sibling_cpumask(cpu)) == 1) { | |
768d9505 GC |
562 | /* |
563 | * for each core in package, increment | |
564 | * the booted_cores for this new cpu | |
565 | */ | |
7d79a7bd BG |
566 | if (cpumask_first( |
567 | topology_sibling_cpumask(i)) == i) | |
768d9505 GC |
568 | c->booted_cores++; |
569 | /* | |
570 | * increment the core count for all | |
571 | * the other cpus in this package | |
572 | */ | |
573 | if (i != cpu) | |
574 | cpu_data(i).booted_cores++; | |
575 | } else if (i != cpu && !c->booted_cores) | |
576 | c->booted_cores = cpu_data(i).booted_cores; | |
577 | } | |
728e5653 | 578 | if (match_die(c, o) && !topology_same_node(c, o)) |
8f37961c | 579 | x86_has_numa_in_package = true; |
768d9505 | 580 | } |
70b8301f AK |
581 | |
582 | threads = cpumask_weight(topology_sibling_cpumask(cpu)); | |
583 | if (threads > __max_smt_threads) | |
584 | __max_smt_threads = threads; | |
768d9505 GC |
585 | } |
586 | ||
70708a18 | 587 | /* maps the cpu to the sched domain representing multi-core */ |
030bb203 | 588 | const struct cpumask *cpu_coregroup_mask(int cpu) |
70708a18 | 589 | { |
9f646389 | 590 | return cpu_llc_shared_mask(cpu); |
030bb203 RR |
591 | } |
592 | ||
a4928cff | 593 | static void impress_friends(void) |
904541e2 GOC |
594 | { |
595 | int cpu; | |
596 | unsigned long bogosum = 0; | |
597 | /* | |
598 | * Allow the user to impress friends. | |
599 | */ | |
c767a54b | 600 | pr_debug("Before bogomips\n"); |
904541e2 | 601 | for_each_possible_cpu(cpu) |
c2d1cec1 | 602 | if (cpumask_test_cpu(cpu, cpu_callout_mask)) |
904541e2 | 603 | bogosum += cpu_data(cpu).loops_per_jiffy; |
c767a54b | 604 | pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n", |
f68e00a3 | 605 | num_online_cpus(), |
904541e2 GOC |
606 | bogosum/(500000/HZ), |
607 | (bogosum/(5000/HZ))%100); | |
608 | ||
c767a54b | 609 | pr_debug("Before bogocount - setting activated=1\n"); |
904541e2 GOC |
610 | } |
611 | ||
569712b2 | 612 | void __inquire_remote_apic(int apicid) |
cb3c8b90 GOC |
613 | { |
614 | unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 }; | |
a6c23905 | 615 | const char * const names[] = { "ID", "VERSION", "SPIV" }; |
cb3c8b90 GOC |
616 | int timeout; |
617 | u32 status; | |
618 | ||
c767a54b | 619 | pr_info("Inquiring remote APIC 0x%x...\n", apicid); |
cb3c8b90 GOC |
620 | |
621 | for (i = 0; i < ARRAY_SIZE(regs); i++) { | |
c767a54b | 622 | pr_info("... APIC 0x%x %s: ", apicid, names[i]); |
cb3c8b90 GOC |
623 | |
624 | /* | |
625 | * Wait for idle. | |
626 | */ | |
627 | status = safe_apic_wait_icr_idle(); | |
628 | if (status) | |
c767a54b | 629 | pr_cont("a previous APIC delivery may have failed\n"); |
cb3c8b90 | 630 | |
1b374e4d | 631 | apic_icr_write(APIC_DM_REMRD | regs[i], apicid); |
cb3c8b90 GOC |
632 | |
633 | timeout = 0; | |
634 | do { | |
635 | udelay(100); | |
636 | status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK; | |
637 | } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000); | |
638 | ||
639 | switch (status) { | |
640 | case APIC_ICR_RR_VALID: | |
641 | status = apic_read(APIC_RRR); | |
c767a54b | 642 | pr_cont("%08x\n", status); |
cb3c8b90 GOC |
643 | break; |
644 | default: | |
c767a54b | 645 | pr_cont("failed\n"); |
cb3c8b90 GOC |
646 | } |
647 | } | |
648 | } | |
649 | ||
d68921f9 LB |
650 | /* |
651 | * The Multiprocessor Specification 1.4 (1997) example code suggests | |
652 | * that there should be a 10ms delay between the BSP asserting INIT | |
653 | * and de-asserting INIT, when starting a remote processor. | |
654 | * But that slows boot and resume on modern processors, which include | |
655 | * many cores and don't require that delay. | |
656 | * | |
657 | * Cmdline "init_cpu_udelay=" is available to over-ride this delay. | |
1a744cb3 | 658 | * Modern processor families are quirked to remove the delay entirely. |
d68921f9 LB |
659 | */ |
660 | #define UDELAY_10MS_DEFAULT 10000 | |
661 | ||
656279a1 | 662 | static unsigned int init_udelay = UINT_MAX; |
d68921f9 LB |
663 | |
664 | static int __init cpu_init_udelay(char *str) | |
665 | { | |
666 | get_option(&str, &init_udelay); | |
667 | ||
668 | return 0; | |
669 | } | |
670 | early_param("cpu_init_udelay", cpu_init_udelay); | |
671 | ||
1a744cb3 LB |
672 | static void __init smp_quirk_init_udelay(void) |
673 | { | |
674 | /* if cmdline changed it from default, leave it alone */ | |
656279a1 | 675 | if (init_udelay != UINT_MAX) |
1a744cb3 LB |
676 | return; |
677 | ||
678 | /* if modern processor, use no delay */ | |
679 | if (((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 6)) || | |
656279a1 | 680 | ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && (boot_cpu_data.x86 >= 0xF))) { |
1a744cb3 | 681 | init_udelay = 0; |
656279a1 LB |
682 | return; |
683 | } | |
f1ccd249 LB |
684 | /* else, use legacy delay */ |
685 | init_udelay = UDELAY_10MS_DEFAULT; | |
1a744cb3 LB |
686 | } |
687 | ||
cb3c8b90 GOC |
688 | /* |
689 | * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal | |
690 | * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this | |
691 | * won't ... remember to clear down the APIC, etc later. | |
692 | */ | |
148f9bb8 | 693 | int |
e1c467e6 | 694 | wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip) |
cb3c8b90 GOC |
695 | { |
696 | unsigned long send_status, accept_status = 0; | |
697 | int maxlvt; | |
698 | ||
699 | /* Target chip */ | |
cb3c8b90 GOC |
700 | /* Boot on the stack */ |
701 | /* Kick the second */ | |
e1c467e6 | 702 | apic_icr_write(APIC_DM_NMI | apic->dest_logical, apicid); |
cb3c8b90 | 703 | |
cfc1b9a6 | 704 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
705 | send_status = safe_apic_wait_icr_idle(); |
706 | ||
707 | /* | |
708 | * Give the other CPU some time to accept the IPI. | |
709 | */ | |
710 | udelay(200); | |
cff9ab2b | 711 | if (APIC_INTEGRATED(boot_cpu_apic_version)) { |
59ef48a5 CG |
712 | maxlvt = lapic_get_maxlvt(); |
713 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
714 | apic_write(APIC_ESR, 0); | |
715 | accept_status = (apic_read(APIC_ESR) & 0xEF); | |
716 | } | |
c767a54b | 717 | pr_debug("NMI sent\n"); |
cb3c8b90 GOC |
718 | |
719 | if (send_status) | |
c767a54b | 720 | pr_err("APIC never delivered???\n"); |
cb3c8b90 | 721 | if (accept_status) |
c767a54b | 722 | pr_err("APIC delivery error (%lx)\n", accept_status); |
cb3c8b90 GOC |
723 | |
724 | return (send_status | accept_status); | |
725 | } | |
cb3c8b90 | 726 | |
148f9bb8 | 727 | static int |
569712b2 | 728 | wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip) |
cb3c8b90 | 729 | { |
f5d6a52f | 730 | unsigned long send_status = 0, accept_status = 0; |
cb3c8b90 GOC |
731 | int maxlvt, num_starts, j; |
732 | ||
593f4a78 MR |
733 | maxlvt = lapic_get_maxlvt(); |
734 | ||
cb3c8b90 GOC |
735 | /* |
736 | * Be paranoid about clearing APIC errors. | |
737 | */ | |
cff9ab2b | 738 | if (APIC_INTEGRATED(boot_cpu_apic_version)) { |
593f4a78 MR |
739 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
740 | apic_write(APIC_ESR, 0); | |
cb3c8b90 GOC |
741 | apic_read(APIC_ESR); |
742 | } | |
743 | ||
c767a54b | 744 | pr_debug("Asserting INIT\n"); |
cb3c8b90 GOC |
745 | |
746 | /* | |
747 | * Turn INIT on target chip | |
748 | */ | |
cb3c8b90 GOC |
749 | /* |
750 | * Send IPI | |
751 | */ | |
1b374e4d SS |
752 | apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT, |
753 | phys_apicid); | |
cb3c8b90 | 754 | |
cfc1b9a6 | 755 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
756 | send_status = safe_apic_wait_icr_idle(); |
757 | ||
7cb68598 | 758 | udelay(init_udelay); |
cb3c8b90 | 759 | |
c767a54b | 760 | pr_debug("Deasserting INIT\n"); |
cb3c8b90 GOC |
761 | |
762 | /* Target chip */ | |
cb3c8b90 | 763 | /* Send IPI */ |
1b374e4d | 764 | apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid); |
cb3c8b90 | 765 | |
cfc1b9a6 | 766 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
767 | send_status = safe_apic_wait_icr_idle(); |
768 | ||
769 | mb(); | |
cb3c8b90 GOC |
770 | |
771 | /* | |
772 | * Should we send STARTUP IPIs ? | |
773 | * | |
774 | * Determine this based on the APIC version. | |
775 | * If we don't have an integrated APIC, don't send the STARTUP IPIs. | |
776 | */ | |
cff9ab2b | 777 | if (APIC_INTEGRATED(boot_cpu_apic_version)) |
cb3c8b90 GOC |
778 | num_starts = 2; |
779 | else | |
780 | num_starts = 0; | |
781 | ||
cb3c8b90 GOC |
782 | /* |
783 | * Run STARTUP IPI loop. | |
784 | */ | |
c767a54b | 785 | pr_debug("#startup loops: %d\n", num_starts); |
cb3c8b90 | 786 | |
cb3c8b90 | 787 | for (j = 1; j <= num_starts; j++) { |
c767a54b | 788 | pr_debug("Sending STARTUP #%d\n", j); |
593f4a78 MR |
789 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
790 | apic_write(APIC_ESR, 0); | |
cb3c8b90 | 791 | apic_read(APIC_ESR); |
c767a54b | 792 | pr_debug("After apic_write\n"); |
cb3c8b90 GOC |
793 | |
794 | /* | |
795 | * STARTUP IPI | |
796 | */ | |
797 | ||
798 | /* Target chip */ | |
cb3c8b90 GOC |
799 | /* Boot on the stack */ |
800 | /* Kick the second */ | |
1b374e4d SS |
801 | apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12), |
802 | phys_apicid); | |
cb3c8b90 GOC |
803 | |
804 | /* | |
805 | * Give the other CPU some time to accept the IPI. | |
806 | */ | |
fcafddec LB |
807 | if (init_udelay == 0) |
808 | udelay(10); | |
809 | else | |
a9bcaa02 | 810 | udelay(300); |
cb3c8b90 | 811 | |
c767a54b | 812 | pr_debug("Startup point 1\n"); |
cb3c8b90 | 813 | |
cfc1b9a6 | 814 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
815 | send_status = safe_apic_wait_icr_idle(); |
816 | ||
817 | /* | |
818 | * Give the other CPU some time to accept the IPI. | |
819 | */ | |
fcafddec LB |
820 | if (init_udelay == 0) |
821 | udelay(10); | |
822 | else | |
a9bcaa02 | 823 | udelay(200); |
cb3c8b90 | 824 | |
593f4a78 | 825 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
cb3c8b90 | 826 | apic_write(APIC_ESR, 0); |
cb3c8b90 GOC |
827 | accept_status = (apic_read(APIC_ESR) & 0xEF); |
828 | if (send_status || accept_status) | |
829 | break; | |
830 | } | |
c767a54b | 831 | pr_debug("After Startup\n"); |
cb3c8b90 GOC |
832 | |
833 | if (send_status) | |
c767a54b | 834 | pr_err("APIC never delivered???\n"); |
cb3c8b90 | 835 | if (accept_status) |
c767a54b | 836 | pr_err("APIC delivery error (%lx)\n", accept_status); |
cb3c8b90 GOC |
837 | |
838 | return (send_status | accept_status); | |
839 | } | |
cb3c8b90 | 840 | |
2eaad1fd | 841 | /* reduce the number of lines printed when booting a large cpu count system */ |
148f9bb8 | 842 | static void announce_cpu(int cpu, int apicid) |
2eaad1fd MT |
843 | { |
844 | static int current_node = -1; | |
4adc8b71 | 845 | int node = early_cpu_to_node(cpu); |
a17bce4d | 846 | static int width, node_width; |
646e29a1 BP |
847 | |
848 | if (!width) | |
849 | width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */ | |
2eaad1fd | 850 | |
a17bce4d BP |
851 | if (!node_width) |
852 | node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */ | |
853 | ||
854 | if (cpu == 1) | |
855 | printk(KERN_INFO "x86: Booting SMP configuration:\n"); | |
856 | ||
2eaad1fd MT |
857 | if (system_state == SYSTEM_BOOTING) { |
858 | if (node != current_node) { | |
859 | if (current_node > (-1)) | |
a17bce4d | 860 | pr_cont("\n"); |
2eaad1fd | 861 | current_node = node; |
a17bce4d BP |
862 | |
863 | printk(KERN_INFO ".... node %*s#%d, CPUs: ", | |
864 | node_width - num_digits(node), " ", node); | |
2eaad1fd | 865 | } |
646e29a1 BP |
866 | |
867 | /* Add padding for the BSP */ | |
868 | if (cpu == 1) | |
869 | pr_cont("%*s", width + 1, " "); | |
870 | ||
871 | pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu); | |
872 | ||
2eaad1fd MT |
873 | } else |
874 | pr_info("Booting Node %d Processor %d APIC 0x%x\n", | |
875 | node, cpu, apicid); | |
876 | } | |
877 | ||
e1c467e6 FY |
878 | static int wakeup_cpu0_nmi(unsigned int cmd, struct pt_regs *regs) |
879 | { | |
880 | int cpu; | |
881 | ||
882 | cpu = smp_processor_id(); | |
883 | if (cpu == 0 && !cpu_online(cpu) && enable_start_cpu0) | |
884 | return NMI_HANDLED; | |
885 | ||
886 | return NMI_DONE; | |
887 | } | |
888 | ||
889 | /* | |
890 | * Wake up AP by INIT, INIT, STARTUP sequence. | |
891 | * | |
892 | * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS | |
893 | * boot-strap code which is not a desired behavior for waking up BSP. To | |
894 | * void the boot-strap code, wake up CPU0 by NMI instead. | |
895 | * | |
896 | * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined | |
897 | * (i.e. physically hot removed and then hot added), NMI won't wake it up. | |
898 | * We'll change this code in the future to wake up hard offlined CPU0 if | |
899 | * real platform and request are available. | |
900 | */ | |
148f9bb8 | 901 | static int |
e1c467e6 FY |
902 | wakeup_cpu_via_init_nmi(int cpu, unsigned long start_ip, int apicid, |
903 | int *cpu0_nmi_registered) | |
904 | { | |
905 | int id; | |
906 | int boot_error; | |
907 | ||
ea7bdc65 JK |
908 | preempt_disable(); |
909 | ||
e1c467e6 FY |
910 | /* |
911 | * Wake up AP by INIT, INIT, STARTUP sequence. | |
912 | */ | |
ea7bdc65 JK |
913 | if (cpu) { |
914 | boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip); | |
915 | goto out; | |
916 | } | |
e1c467e6 FY |
917 | |
918 | /* | |
919 | * Wake up BSP by nmi. | |
920 | * | |
921 | * Register a NMI handler to help wake up CPU0. | |
922 | */ | |
923 | boot_error = register_nmi_handler(NMI_LOCAL, | |
924 | wakeup_cpu0_nmi, 0, "wake_cpu0"); | |
925 | ||
926 | if (!boot_error) { | |
927 | enable_start_cpu0 = 1; | |
928 | *cpu0_nmi_registered = 1; | |
929 | if (apic->dest_logical == APIC_DEST_LOGICAL) | |
930 | id = cpu0_logical_apicid; | |
931 | else | |
932 | id = apicid; | |
933 | boot_error = wakeup_secondary_cpu_via_nmi(id, start_ip); | |
934 | } | |
ea7bdc65 JK |
935 | |
936 | out: | |
937 | preempt_enable(); | |
e1c467e6 FY |
938 | |
939 | return boot_error; | |
940 | } | |
941 | ||
3f85483b BO |
942 | void common_cpu_up(unsigned int cpu, struct task_struct *idle) |
943 | { | |
944 | /* Just in case we booted with a single CPU. */ | |
945 | alternatives_enable_smp(); | |
946 | ||
947 | per_cpu(current_task, cpu) = idle; | |
948 | ||
949 | #ifdef CONFIG_X86_32 | |
950 | /* Stack for startup_32 can be just as for start_secondary onwards */ | |
951 | irq_ctx_init(cpu); | |
952 | per_cpu(cpu_current_top_of_stack, cpu) = | |
953 | (unsigned long)task_stack_page(idle) + THREAD_SIZE; | |
954 | #else | |
3f85483b BO |
955 | initial_gs = per_cpu_offset(cpu); |
956 | #endif | |
3f85483b BO |
957 | } |
958 | ||
cb3c8b90 GOC |
959 | /* |
960 | * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad | |
961 | * (ie clustered apic addressing mode), this is a LOGICAL apic ID. | |
1f5bcabf IM |
962 | * Returns zero if CPU booted OK, else error code from |
963 | * ->wakeup_secondary_cpu. | |
cb3c8b90 | 964 | */ |
148f9bb8 | 965 | static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle) |
cb3c8b90 | 966 | { |
48927bbb | 967 | volatile u32 *trampoline_status = |
b429dbf6 | 968 | (volatile u32 *) __va(real_mode_header->trampoline_status); |
48927bbb | 969 | /* start_ip had better be page-aligned! */ |
f37240f1 | 970 | unsigned long start_ip = real_mode_header->trampoline_start; |
48927bbb | 971 | |
cb3c8b90 | 972 | unsigned long boot_error = 0; |
e1c467e6 | 973 | int cpu0_nmi_registered = 0; |
ce4b1b16 | 974 | unsigned long timeout; |
cb3c8b90 | 975 | |
b9b1a9c3 | 976 | idle->thread.sp = (unsigned long)task_pt_regs(idle); |
a939098a | 977 | early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu); |
3e970473 | 978 | initial_code = (unsigned long)start_secondary; |
b32f96c7 | 979 | initial_stack = idle->thread.sp; |
cb3c8b90 | 980 | |
20d5e4a9 ZG |
981 | /* |
982 | * Enable the espfix hack for this CPU | |
983 | */ | |
984 | #ifdef CONFIG_X86_ESPFIX64 | |
985 | init_espfix_ap(cpu); | |
986 | #endif | |
987 | ||
2eaad1fd MT |
988 | /* So we see what's up */ |
989 | announce_cpu(cpu, apicid); | |
cb3c8b90 GOC |
990 | |
991 | /* | |
992 | * This grunge runs the startup process for | |
993 | * the targeted processor. | |
994 | */ | |
995 | ||
34d05591 | 996 | if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { |
cb3c8b90 | 997 | |
cfc1b9a6 | 998 | pr_debug("Setting warm reset code and vector.\n"); |
cb3c8b90 | 999 | |
34d05591 JS |
1000 | smpboot_setup_warm_reset_vector(start_ip); |
1001 | /* | |
1002 | * Be paranoid about clearing APIC errors. | |
db96b0a0 | 1003 | */ |
cff9ab2b | 1004 | if (APIC_INTEGRATED(boot_cpu_apic_version)) { |
db96b0a0 CG |
1005 | apic_write(APIC_ESR, 0); |
1006 | apic_read(APIC_ESR); | |
1007 | } | |
34d05591 | 1008 | } |
cb3c8b90 | 1009 | |
ce4b1b16 IM |
1010 | /* |
1011 | * AP might wait on cpu_callout_mask in cpu_init() with | |
1012 | * cpu_initialized_mask set if previous attempt to online | |
1013 | * it timed-out. Clear cpu_initialized_mask so that after | |
1014 | * INIT/SIPI it could start with a clean state. | |
1015 | */ | |
1016 | cpumask_clear_cpu(cpu, cpu_initialized_mask); | |
1017 | smp_mb(); | |
1018 | ||
cb3c8b90 | 1019 | /* |
e1c467e6 FY |
1020 | * Wake up a CPU in difference cases: |
1021 | * - Use the method in the APIC driver if it's defined | |
1022 | * Otherwise, | |
1023 | * - Use an INIT boot APIC message for APs or NMI for BSP. | |
cb3c8b90 | 1024 | */ |
1f5bcabf IM |
1025 | if (apic->wakeup_secondary_cpu) |
1026 | boot_error = apic->wakeup_secondary_cpu(apicid, start_ip); | |
1027 | else | |
e1c467e6 FY |
1028 | boot_error = wakeup_cpu_via_init_nmi(cpu, start_ip, apicid, |
1029 | &cpu0_nmi_registered); | |
cb3c8b90 GOC |
1030 | |
1031 | if (!boot_error) { | |
1032 | /* | |
6e38f1e7 | 1033 | * Wait 10s total for first sign of life from AP |
cb3c8b90 | 1034 | */ |
ce4b1b16 IM |
1035 | boot_error = -1; |
1036 | timeout = jiffies + 10*HZ; | |
1037 | while (time_before(jiffies, timeout)) { | |
1038 | if (cpumask_test_cpu(cpu, cpu_initialized_mask)) { | |
1039 | /* | |
1040 | * Tell AP to proceed with initialization | |
1041 | */ | |
1042 | cpumask_set_cpu(cpu, cpu_callout_mask); | |
1043 | boot_error = 0; | |
1044 | break; | |
1045 | } | |
ce4b1b16 IM |
1046 | schedule(); |
1047 | } | |
1048 | } | |
cb3c8b90 | 1049 | |
ce4b1b16 | 1050 | if (!boot_error) { |
cb3c8b90 | 1051 | /* |
ce4b1b16 | 1052 | * Wait till AP completes initial initialization |
cb3c8b90 | 1053 | */ |
ce4b1b16 | 1054 | while (!cpumask_test_cpu(cpu, cpu_callin_mask)) { |
68f202e4 SS |
1055 | /* |
1056 | * Allow other tasks to run while we wait for the | |
1057 | * AP to come online. This also gives a chance | |
1058 | * for the MTRR work(triggered by the AP coming online) | |
1059 | * to be completed in the stop machine context. | |
1060 | */ | |
1061 | schedule(); | |
cb3c8b90 | 1062 | } |
cb3c8b90 GOC |
1063 | } |
1064 | ||
1065 | /* mark "stuck" area as not stuck */ | |
48927bbb | 1066 | *trampoline_status = 0; |
cb3c8b90 | 1067 | |
02421f98 YL |
1068 | if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { |
1069 | /* | |
1070 | * Cleanup possible dangling ends... | |
1071 | */ | |
1072 | smpboot_restore_warm_reset_vector(); | |
1073 | } | |
e1c467e6 FY |
1074 | /* |
1075 | * Clean up the nmi handler. Do this after the callin and callout sync | |
1076 | * to avoid impact of possible long unregister time. | |
1077 | */ | |
1078 | if (cpu0_nmi_registered) | |
1079 | unregister_nmi_handler(NMI_LOCAL, "wake_cpu0"); | |
1080 | ||
cb3c8b90 GOC |
1081 | return boot_error; |
1082 | } | |
1083 | ||
148f9bb8 | 1084 | int native_cpu_up(unsigned int cpu, struct task_struct *tidle) |
cb3c8b90 | 1085 | { |
a21769a4 | 1086 | int apicid = apic->cpu_present_to_apicid(cpu); |
cb3c8b90 GOC |
1087 | unsigned long flags; |
1088 | int err; | |
1089 | ||
1090 | WARN_ON(irqs_disabled()); | |
1091 | ||
cfc1b9a6 | 1092 | pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu); |
cb3c8b90 | 1093 | |
30106c17 | 1094 | if (apicid == BAD_APICID || |
c284b42a | 1095 | !physid_isset(apicid, phys_cpu_present_map) || |
fa63030e | 1096 | !apic->apic_id_valid(apicid)) { |
c767a54b | 1097 | pr_err("%s: bad cpu %d\n", __func__, cpu); |
cb3c8b90 GOC |
1098 | return -EINVAL; |
1099 | } | |
1100 | ||
1101 | /* | |
1102 | * Already booted CPU? | |
1103 | */ | |
c2d1cec1 | 1104 | if (cpumask_test_cpu(cpu, cpu_callin_mask)) { |
cfc1b9a6 | 1105 | pr_debug("do_boot_cpu %d Already started\n", cpu); |
cb3c8b90 GOC |
1106 | return -ENOSYS; |
1107 | } | |
1108 | ||
1109 | /* | |
1110 | * Save current MTRR state in case it was changed since early boot | |
1111 | * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync: | |
1112 | */ | |
1113 | mtrr_save_state(); | |
1114 | ||
2a442c9c PM |
1115 | /* x86 CPUs take themselves offline, so delayed offline is OK. */ |
1116 | err = cpu_check_up_prepare(cpu); | |
1117 | if (err && err != -EBUSY) | |
1118 | return err; | |
cb3c8b90 | 1119 | |
644c1541 | 1120 | /* the FPU context is blank, nobody can own it */ |
317b622c | 1121 | per_cpu(fpu_fpregs_owner_ctx, cpu) = NULL; |
644c1541 | 1122 | |
3f85483b BO |
1123 | common_cpu_up(cpu, tidle); |
1124 | ||
7eb43a6d | 1125 | err = do_boot_cpu(apicid, cpu, tidle); |
61165d7a | 1126 | if (err) { |
feef1e8e | 1127 | pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu); |
61165d7a | 1128 | return -EIO; |
cb3c8b90 GOC |
1129 | } |
1130 | ||
1131 | /* | |
1132 | * Check TSC synchronization with the AP (keep irqs disabled | |
1133 | * while doing so): | |
1134 | */ | |
1135 | local_irq_save(flags); | |
1136 | check_tsc_sync_source(cpu); | |
1137 | local_irq_restore(flags); | |
1138 | ||
7c04e64a | 1139 | while (!cpu_online(cpu)) { |
cb3c8b90 GOC |
1140 | cpu_relax(); |
1141 | touch_nmi_watchdog(); | |
1142 | } | |
1143 | ||
1144 | return 0; | |
1145 | } | |
1146 | ||
7167d08e HK |
1147 | /** |
1148 | * arch_disable_smp_support() - disables SMP support for x86 at runtime | |
1149 | */ | |
1150 | void arch_disable_smp_support(void) | |
1151 | { | |
1152 | disable_ioapic_support(); | |
1153 | } | |
1154 | ||
8aef135c GOC |
1155 | /* |
1156 | * Fall back to non SMP mode after errors. | |
1157 | * | |
1158 | * RED-PEN audit/test this more. I bet there is more state messed up here. | |
1159 | */ | |
1160 | static __init void disable_smp(void) | |
1161 | { | |
613c25ef TG |
1162 | pr_info("SMP disabled\n"); |
1163 | ||
ef4c59a4 TG |
1164 | disable_ioapic_support(); |
1165 | ||
4f062896 RR |
1166 | init_cpu_present(cpumask_of(0)); |
1167 | init_cpu_possible(cpumask_of(0)); | |
0f385d1d | 1168 | |
8aef135c | 1169 | if (smp_found_config) |
b6df1b8b | 1170 | physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); |
8aef135c | 1171 | else |
b6df1b8b | 1172 | physid_set_mask_of_physid(0, &phys_cpu_present_map); |
7d79a7bd BG |
1173 | cpumask_set_cpu(0, topology_sibling_cpumask(0)); |
1174 | cpumask_set_cpu(0, topology_core_cpumask(0)); | |
8aef135c GOC |
1175 | } |
1176 | ||
613c25ef TG |
1177 | enum { |
1178 | SMP_OK, | |
1179 | SMP_NO_CONFIG, | |
1180 | SMP_NO_APIC, | |
1181 | SMP_FORCE_UP, | |
1182 | }; | |
1183 | ||
8aef135c GOC |
1184 | /* |
1185 | * Various sanity checks. | |
1186 | */ | |
1187 | static int __init smp_sanity_check(unsigned max_cpus) | |
1188 | { | |
ac23d4ee | 1189 | preempt_disable(); |
a58f03b0 | 1190 | |
1ff2f20d | 1191 | #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32) |
a58f03b0 YL |
1192 | if (def_to_bigsmp && nr_cpu_ids > 8) { |
1193 | unsigned int cpu; | |
1194 | unsigned nr; | |
1195 | ||
c767a54b JP |
1196 | pr_warn("More than 8 CPUs detected - skipping them\n" |
1197 | "Use CONFIG_X86_BIGSMP\n"); | |
a58f03b0 YL |
1198 | |
1199 | nr = 0; | |
1200 | for_each_present_cpu(cpu) { | |
1201 | if (nr >= 8) | |
c2d1cec1 | 1202 | set_cpu_present(cpu, false); |
a58f03b0 YL |
1203 | nr++; |
1204 | } | |
1205 | ||
1206 | nr = 0; | |
1207 | for_each_possible_cpu(cpu) { | |
1208 | if (nr >= 8) | |
c2d1cec1 | 1209 | set_cpu_possible(cpu, false); |
a58f03b0 YL |
1210 | nr++; |
1211 | } | |
1212 | ||
1213 | nr_cpu_ids = 8; | |
1214 | } | |
1215 | #endif | |
1216 | ||
8aef135c | 1217 | if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) { |
c767a54b | 1218 | pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n", |
55c395b4 MT |
1219 | hard_smp_processor_id()); |
1220 | ||
8aef135c GOC |
1221 | physid_set(hard_smp_processor_id(), phys_cpu_present_map); |
1222 | } | |
1223 | ||
1224 | /* | |
1225 | * If we couldn't find an SMP configuration at boot time, | |
1226 | * get out of here now! | |
1227 | */ | |
1228 | if (!smp_found_config && !acpi_lapic) { | |
ac23d4ee | 1229 | preempt_enable(); |
c767a54b | 1230 | pr_notice("SMP motherboard not detected\n"); |
613c25ef | 1231 | return SMP_NO_CONFIG; |
8aef135c GOC |
1232 | } |
1233 | ||
1234 | /* | |
1235 | * Should not be necessary because the MP table should list the boot | |
1236 | * CPU too, but we do it for the sake of robustness anyway. | |
1237 | */ | |
a27a6210 | 1238 | if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) { |
c767a54b JP |
1239 | pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n", |
1240 | boot_cpu_physical_apicid); | |
8aef135c GOC |
1241 | physid_set(hard_smp_processor_id(), phys_cpu_present_map); |
1242 | } | |
ac23d4ee | 1243 | preempt_enable(); |
8aef135c GOC |
1244 | |
1245 | /* | |
1246 | * If we couldn't find a local APIC, then get out of here now! | |
1247 | */ | |
cff9ab2b | 1248 | if (APIC_INTEGRATED(boot_cpu_apic_version) && |
93984fbd | 1249 | !boot_cpu_has(X86_FEATURE_APIC)) { |
103428e5 CG |
1250 | if (!disable_apic) { |
1251 | pr_err("BIOS bug, local APIC #%d not detected!...\n", | |
1252 | boot_cpu_physical_apicid); | |
c767a54b | 1253 | pr_err("... forcing use of dummy APIC emulation (tell your hw vendor)\n"); |
103428e5 | 1254 | } |
613c25ef | 1255 | return SMP_NO_APIC; |
8aef135c GOC |
1256 | } |
1257 | ||
8aef135c GOC |
1258 | /* |
1259 | * If SMP should be disabled, then really disable it! | |
1260 | */ | |
1261 | if (!max_cpus) { | |
c767a54b | 1262 | pr_info("SMP mode deactivated\n"); |
613c25ef | 1263 | return SMP_FORCE_UP; |
8aef135c GOC |
1264 | } |
1265 | ||
613c25ef | 1266 | return SMP_OK; |
8aef135c GOC |
1267 | } |
1268 | ||
1269 | static void __init smp_cpu_index_default(void) | |
1270 | { | |
1271 | int i; | |
1272 | struct cpuinfo_x86 *c; | |
1273 | ||
7c04e64a | 1274 | for_each_possible_cpu(i) { |
8aef135c GOC |
1275 | c = &cpu_data(i); |
1276 | /* mark all to hotplug */ | |
9628937d | 1277 | c->cpu_index = nr_cpu_ids; |
8aef135c GOC |
1278 | } |
1279 | } | |
1280 | ||
1281 | /* | |
1282 | * Prepare for SMP bootup. The MP table or ACPI has been read | |
1283 | * earlier. Just do some sanity checking here and enable APIC mode. | |
1284 | */ | |
1285 | void __init native_smp_prepare_cpus(unsigned int max_cpus) | |
1286 | { | |
7ad728f9 RR |
1287 | unsigned int i; |
1288 | ||
8aef135c | 1289 | smp_cpu_index_default(); |
792363d2 | 1290 | |
8aef135c GOC |
1291 | /* |
1292 | * Setup boot CPU information | |
1293 | */ | |
30106c17 | 1294 | smp_store_boot_cpu_info(); /* Final full version of the data */ |
792363d2 YL |
1295 | cpumask_copy(cpu_callin_mask, cpumask_of(0)); |
1296 | mb(); | |
bd22a2f1 | 1297 | |
7ad728f9 | 1298 | for_each_possible_cpu(i) { |
79f55997 LZ |
1299 | zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL); |
1300 | zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL); | |
b3d7336d | 1301 | zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL); |
7ad728f9 | 1302 | } |
8f37961c TC |
1303 | |
1304 | /* | |
1305 | * Set 'default' x86 topology, this matches default_topology() in that | |
1306 | * it has NUMA nodes as a topology level. See also | |
1307 | * native_smp_cpus_done(). | |
1308 | * | |
1309 | * Must be done before set_cpus_sibling_map() is ran. | |
1310 | */ | |
1311 | set_sched_topology(x86_topology); | |
1312 | ||
8aef135c GOC |
1313 | set_cpu_sibling_map(0); |
1314 | ||
613c25ef TG |
1315 | switch (smp_sanity_check(max_cpus)) { |
1316 | case SMP_NO_CONFIG: | |
8aef135c | 1317 | disable_smp(); |
613c25ef TG |
1318 | if (APIC_init_uniprocessor()) |
1319 | pr_notice("Local APIC not detected. Using dummy APIC emulation.\n"); | |
1320 | return; | |
1321 | case SMP_NO_APIC: | |
1322 | disable_smp(); | |
1323 | return; | |
1324 | case SMP_FORCE_UP: | |
1325 | disable_smp(); | |
374aab33 | 1326 | apic_bsp_setup(false); |
250a1ac6 | 1327 | return; |
613c25ef TG |
1328 | case SMP_OK: |
1329 | break; | |
8aef135c GOC |
1330 | } |
1331 | ||
4c9961d5 | 1332 | if (read_apic_id() != boot_cpu_physical_apicid) { |
8aef135c | 1333 | panic("Boot APIC ID in local APIC unexpected (%d vs %d)", |
4c9961d5 | 1334 | read_apic_id(), boot_cpu_physical_apicid); |
8aef135c GOC |
1335 | /* Or can we switch back to PIC here? */ |
1336 | } | |
1337 | ||
384d9fe3 | 1338 | default_setup_apic_routing(); |
374aab33 | 1339 | cpu0_logical_apicid = apic_bsp_setup(false); |
ef4c59a4 | 1340 | |
d54ff31d | 1341 | pr_info("CPU0: "); |
8aef135c | 1342 | print_cpu_info(&cpu_data(0)); |
c4bd1fda MS |
1343 | |
1344 | if (is_uv_system()) | |
1345 | uv_system_init(); | |
d0af9eed SS |
1346 | |
1347 | set_mtrr_aps_delayed_init(); | |
1a744cb3 LB |
1348 | |
1349 | smp_quirk_init_udelay(); | |
8aef135c | 1350 | } |
d0af9eed SS |
1351 | |
1352 | void arch_enable_nonboot_cpus_begin(void) | |
1353 | { | |
1354 | set_mtrr_aps_delayed_init(); | |
1355 | } | |
1356 | ||
1357 | void arch_enable_nonboot_cpus_end(void) | |
1358 | { | |
1359 | mtrr_aps_init(); | |
1360 | } | |
1361 | ||
a8db8453 GOC |
1362 | /* |
1363 | * Early setup to make printk work. | |
1364 | */ | |
1365 | void __init native_smp_prepare_boot_cpu(void) | |
1366 | { | |
1367 | int me = smp_processor_id(); | |
552be871 | 1368 | switch_to_new_gdt(me); |
c2d1cec1 MT |
1369 | /* already set me in cpu_online_mask in boot_cpu_init() */ |
1370 | cpumask_set_cpu(me, cpu_callout_mask); | |
2a442c9c | 1371 | cpu_set_state_online(me); |
a8db8453 GOC |
1372 | } |
1373 | ||
83f7eb9c GOC |
1374 | void __init native_smp_cpus_done(unsigned int max_cpus) |
1375 | { | |
c767a54b | 1376 | pr_debug("Boot done\n"); |
83f7eb9c | 1377 | |
8f37961c TC |
1378 | if (x86_has_numa_in_package) |
1379 | set_sched_topology(x86_numa_in_package_topology); | |
1380 | ||
99e8b9ca | 1381 | nmi_selftest(); |
83f7eb9c | 1382 | impress_friends(); |
83f7eb9c | 1383 | setup_ioapic_dest(); |
d0af9eed | 1384 | mtrr_aps_init(); |
83f7eb9c GOC |
1385 | } |
1386 | ||
3b11ce7f MT |
1387 | static int __initdata setup_possible_cpus = -1; |
1388 | static int __init _setup_possible_cpus(char *str) | |
1389 | { | |
1390 | get_option(&str, &setup_possible_cpus); | |
1391 | return 0; | |
1392 | } | |
1393 | early_param("possible_cpus", _setup_possible_cpus); | |
1394 | ||
1395 | ||
68a1c3f8 | 1396 | /* |
4f062896 | 1397 | * cpu_possible_mask should be static, it cannot change as cpu's |
68a1c3f8 GC |
1398 | * are onlined, or offlined. The reason is per-cpu data-structures |
1399 | * are allocated by some modules at init time, and dont expect to | |
1400 | * do this dynamically on cpu arrival/departure. | |
4f062896 | 1401 | * cpu_present_mask on the other hand can change dynamically. |
68a1c3f8 GC |
1402 | * In case when cpu_hotplug is not compiled, then we resort to current |
1403 | * behaviour, which is cpu_possible == cpu_present. | |
1404 | * - Ashok Raj | |
1405 | * | |
1406 | * Three ways to find out the number of additional hotplug CPUs: | |
1407 | * - If the BIOS specified disabled CPUs in ACPI/mptables use that. | |
3b11ce7f | 1408 | * - The user can overwrite it with possible_cpus=NUM |
68a1c3f8 GC |
1409 | * - Otherwise don't reserve additional CPUs. |
1410 | * We do this because additional CPUs waste a lot of memory. | |
1411 | * -AK | |
1412 | */ | |
1413 | __init void prefill_possible_map(void) | |
1414 | { | |
cb48bb59 | 1415 | int i, possible; |
68a1c3f8 | 1416 | |
2a51fe08 PB |
1417 | /* No boot processor was found in mptable or ACPI MADT */ |
1418 | if (!num_processors) { | |
ff856051 VS |
1419 | if (boot_cpu_has(X86_FEATURE_APIC)) { |
1420 | int apicid = boot_cpu_physical_apicid; | |
1421 | int cpu = hard_smp_processor_id(); | |
2a51fe08 | 1422 | |
ff856051 | 1423 | pr_warn("Boot CPU (id %d) not listed by BIOS\n", cpu); |
2a51fe08 | 1424 | |
ff856051 VS |
1425 | /* Make sure boot cpu is enumerated */ |
1426 | if (apic->cpu_present_to_apicid(0) == BAD_APICID && | |
1427 | apic->apic_id_valid(apicid)) | |
1428 | generic_processor_info(apicid, boot_cpu_apic_version); | |
1429 | } | |
2a51fe08 PB |
1430 | |
1431 | if (!num_processors) | |
1432 | num_processors = 1; | |
1433 | } | |
329513a3 | 1434 | |
5f2eb550 JB |
1435 | i = setup_max_cpus ?: 1; |
1436 | if (setup_possible_cpus == -1) { | |
1437 | possible = num_processors; | |
1438 | #ifdef CONFIG_HOTPLUG_CPU | |
1439 | if (setup_max_cpus) | |
1440 | possible += disabled_cpus; | |
1441 | #else | |
1442 | if (possible > i) | |
1443 | possible = i; | |
1444 | #endif | |
1445 | } else | |
3b11ce7f MT |
1446 | possible = setup_possible_cpus; |
1447 | ||
730cf272 MT |
1448 | total_cpus = max_t(int, possible, num_processors + disabled_cpus); |
1449 | ||
2b633e3f YL |
1450 | /* nr_cpu_ids could be reduced via nr_cpus= */ |
1451 | if (possible > nr_cpu_ids) { | |
c767a54b | 1452 | pr_warn("%d Processors exceeds NR_CPUS limit of %d\n", |
2b633e3f YL |
1453 | possible, nr_cpu_ids); |
1454 | possible = nr_cpu_ids; | |
3b11ce7f | 1455 | } |
68a1c3f8 | 1456 | |
5f2eb550 JB |
1457 | #ifdef CONFIG_HOTPLUG_CPU |
1458 | if (!setup_max_cpus) | |
1459 | #endif | |
1460 | if (possible > i) { | |
c767a54b | 1461 | pr_warn("%d Processors exceeds max_cpus limit of %u\n", |
5f2eb550 JB |
1462 | possible, setup_max_cpus); |
1463 | possible = i; | |
1464 | } | |
1465 | ||
c767a54b | 1466 | pr_info("Allowing %d CPUs, %d hotplug CPUs\n", |
68a1c3f8 GC |
1467 | possible, max_t(int, possible - num_processors, 0)); |
1468 | ||
1469 | for (i = 0; i < possible; i++) | |
c2d1cec1 | 1470 | set_cpu_possible(i, true); |
5f2eb550 JB |
1471 | for (; i < NR_CPUS; i++) |
1472 | set_cpu_possible(i, false); | |
3461b0af MT |
1473 | |
1474 | nr_cpu_ids = possible; | |
68a1c3f8 | 1475 | } |
69c18c15 | 1476 | |
14adf855 CE |
1477 | #ifdef CONFIG_HOTPLUG_CPU |
1478 | ||
70b8301f AK |
1479 | /* Recompute SMT state for all CPUs on offline */ |
1480 | static void recompute_smt_state(void) | |
1481 | { | |
1482 | int max_threads, cpu; | |
1483 | ||
1484 | max_threads = 0; | |
1485 | for_each_online_cpu (cpu) { | |
1486 | int threads = cpumask_weight(topology_sibling_cpumask(cpu)); | |
1487 | ||
1488 | if (threads > max_threads) | |
1489 | max_threads = threads; | |
1490 | } | |
1491 | __max_smt_threads = max_threads; | |
1492 | } | |
1493 | ||
14adf855 CE |
1494 | static void remove_siblinginfo(int cpu) |
1495 | { | |
1496 | int sibling; | |
1497 | struct cpuinfo_x86 *c = &cpu_data(cpu); | |
1498 | ||
7d79a7bd BG |
1499 | for_each_cpu(sibling, topology_core_cpumask(cpu)) { |
1500 | cpumask_clear_cpu(cpu, topology_core_cpumask(sibling)); | |
14adf855 CE |
1501 | /*/ |
1502 | * last thread sibling in this cpu core going down | |
1503 | */ | |
7d79a7bd | 1504 | if (cpumask_weight(topology_sibling_cpumask(cpu)) == 1) |
14adf855 CE |
1505 | cpu_data(sibling).booted_cores--; |
1506 | } | |
1507 | ||
7d79a7bd BG |
1508 | for_each_cpu(sibling, topology_sibling_cpumask(cpu)) |
1509 | cpumask_clear_cpu(cpu, topology_sibling_cpumask(sibling)); | |
03bd4e1f WL |
1510 | for_each_cpu(sibling, cpu_llc_shared_mask(cpu)) |
1511 | cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling)); | |
1512 | cpumask_clear(cpu_llc_shared_mask(cpu)); | |
7d79a7bd BG |
1513 | cpumask_clear(topology_sibling_cpumask(cpu)); |
1514 | cpumask_clear(topology_core_cpumask(cpu)); | |
14adf855 CE |
1515 | c->phys_proc_id = 0; |
1516 | c->cpu_core_id = 0; | |
c2d1cec1 | 1517 | cpumask_clear_cpu(cpu, cpu_sibling_setup_mask); |
70b8301f | 1518 | recompute_smt_state(); |
14adf855 CE |
1519 | } |
1520 | ||
4daa832d | 1521 | static void remove_cpu_from_maps(int cpu) |
69c18c15 | 1522 | { |
c2d1cec1 MT |
1523 | set_cpu_online(cpu, false); |
1524 | cpumask_clear_cpu(cpu, cpu_callout_mask); | |
1525 | cpumask_clear_cpu(cpu, cpu_callin_mask); | |
69c18c15 | 1526 | /* was set by cpu_init() */ |
c2d1cec1 | 1527 | cpumask_clear_cpu(cpu, cpu_initialized_mask); |
23ca4bba | 1528 | numa_remove_cpu(cpu); |
69c18c15 GC |
1529 | } |
1530 | ||
8227dce7 | 1531 | void cpu_disable_common(void) |
69c18c15 GC |
1532 | { |
1533 | int cpu = smp_processor_id(); | |
69c18c15 | 1534 | |
69c18c15 GC |
1535 | remove_siblinginfo(cpu); |
1536 | ||
1537 | /* It's now safe to remove this processor from the online map */ | |
d388e5fd | 1538 | lock_vector_lock(); |
69c18c15 | 1539 | remove_cpu_from_maps(cpu); |
d388e5fd | 1540 | unlock_vector_lock(); |
d7b381bb | 1541 | fixup_irqs(); |
8227dce7 AN |
1542 | } |
1543 | ||
1544 | int native_cpu_disable(void) | |
1545 | { | |
da6139e4 PB |
1546 | int ret; |
1547 | ||
1548 | ret = check_irq_vectors_for_cpu_disable(); | |
1549 | if (ret) | |
1550 | return ret; | |
1551 | ||
8227dce7 | 1552 | clear_local_APIC(); |
8227dce7 | 1553 | cpu_disable_common(); |
2ed53c0d | 1554 | |
69c18c15 GC |
1555 | return 0; |
1556 | } | |
1557 | ||
2a442c9c | 1558 | int common_cpu_die(unsigned int cpu) |
54279552 | 1559 | { |
2a442c9c | 1560 | int ret = 0; |
54279552 | 1561 | |
69c18c15 | 1562 | /* We don't do anything here: idle task is faking death itself. */ |
54279552 | 1563 | |
2ed53c0d | 1564 | /* They ack this in play_dead() by setting CPU_DEAD */ |
2a442c9c | 1565 | if (cpu_wait_death(cpu, 5)) { |
2ed53c0d LT |
1566 | if (system_state == SYSTEM_RUNNING) |
1567 | pr_info("CPU %u is now offline\n", cpu); | |
1568 | } else { | |
1569 | pr_err("CPU %u didn't die...\n", cpu); | |
2a442c9c | 1570 | ret = -1; |
69c18c15 | 1571 | } |
2a442c9c PM |
1572 | |
1573 | return ret; | |
1574 | } | |
1575 | ||
1576 | void native_cpu_die(unsigned int cpu) | |
1577 | { | |
1578 | common_cpu_die(cpu); | |
69c18c15 | 1579 | } |
a21f5d88 AN |
1580 | |
1581 | void play_dead_common(void) | |
1582 | { | |
1583 | idle_task_exit(); | |
1584 | reset_lazy_tlbstate(); | |
a21f5d88 | 1585 | |
a21f5d88 | 1586 | /* Ack it */ |
2a442c9c | 1587 | (void)cpu_report_death(); |
a21f5d88 AN |
1588 | |
1589 | /* | |
1590 | * With physical CPU hotplug, we should halt the cpu | |
1591 | */ | |
1592 | local_irq_disable(); | |
1593 | } | |
1594 | ||
e1c467e6 FY |
1595 | static bool wakeup_cpu0(void) |
1596 | { | |
1597 | if (smp_processor_id() == 0 && enable_start_cpu0) | |
1598 | return true; | |
1599 | ||
1600 | return false; | |
1601 | } | |
1602 | ||
ea530692 PA |
1603 | /* |
1604 | * We need to flush the caches before going to sleep, lest we have | |
1605 | * dirty data in our caches when we come back up. | |
1606 | */ | |
1607 | static inline void mwait_play_dead(void) | |
1608 | { | |
1609 | unsigned int eax, ebx, ecx, edx; | |
1610 | unsigned int highest_cstate = 0; | |
1611 | unsigned int highest_subcstate = 0; | |
ce5f6824 | 1612 | void *mwait_ptr; |
576cfb40 | 1613 | int i; |
ea530692 | 1614 | |
69fb3676 | 1615 | if (!this_cpu_has(X86_FEATURE_MWAIT)) |
ea530692 | 1616 | return; |
840d2830 | 1617 | if (!this_cpu_has(X86_FEATURE_CLFLUSH)) |
ce5f6824 | 1618 | return; |
7b543a53 | 1619 | if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF) |
ea530692 PA |
1620 | return; |
1621 | ||
1622 | eax = CPUID_MWAIT_LEAF; | |
1623 | ecx = 0; | |
1624 | native_cpuid(&eax, &ebx, &ecx, &edx); | |
1625 | ||
1626 | /* | |
1627 | * eax will be 0 if EDX enumeration is not valid. | |
1628 | * Initialized below to cstate, sub_cstate value when EDX is valid. | |
1629 | */ | |
1630 | if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) { | |
1631 | eax = 0; | |
1632 | } else { | |
1633 | edx >>= MWAIT_SUBSTATE_SIZE; | |
1634 | for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) { | |
1635 | if (edx & MWAIT_SUBSTATE_MASK) { | |
1636 | highest_cstate = i; | |
1637 | highest_subcstate = edx & MWAIT_SUBSTATE_MASK; | |
1638 | } | |
1639 | } | |
1640 | eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) | | |
1641 | (highest_subcstate - 1); | |
1642 | } | |
1643 | ||
ce5f6824 PA |
1644 | /* |
1645 | * This should be a memory location in a cache line which is | |
1646 | * unlikely to be touched by other processors. The actual | |
1647 | * content is immaterial as it is not actually modified in any way. | |
1648 | */ | |
1649 | mwait_ptr = ¤t_thread_info()->flags; | |
1650 | ||
a68e5c94 PA |
1651 | wbinvd(); |
1652 | ||
ea530692 | 1653 | while (1) { |
ce5f6824 PA |
1654 | /* |
1655 | * The CLFLUSH is a workaround for erratum AAI65 for | |
1656 | * the Xeon 7400 series. It's not clear it is actually | |
1657 | * needed, but it should be harmless in either case. | |
1658 | * The WBINVD is insufficient due to the spurious-wakeup | |
1659 | * case where we return around the loop. | |
1660 | */ | |
7d590cca | 1661 | mb(); |
ce5f6824 | 1662 | clflush(mwait_ptr); |
7d590cca | 1663 | mb(); |
ce5f6824 | 1664 | __monitor(mwait_ptr, 0, 0); |
ea530692 PA |
1665 | mb(); |
1666 | __mwait(eax, 0); | |
e1c467e6 FY |
1667 | /* |
1668 | * If NMI wants to wake up CPU0, start CPU0. | |
1669 | */ | |
1670 | if (wakeup_cpu0()) | |
1671 | start_cpu0(); | |
ea530692 PA |
1672 | } |
1673 | } | |
1674 | ||
406f992e | 1675 | void hlt_play_dead(void) |
ea530692 | 1676 | { |
7b543a53 | 1677 | if (__this_cpu_read(cpu_info.x86) >= 4) |
a68e5c94 PA |
1678 | wbinvd(); |
1679 | ||
ea530692 | 1680 | while (1) { |
ea530692 | 1681 | native_halt(); |
e1c467e6 FY |
1682 | /* |
1683 | * If NMI wants to wake up CPU0, start CPU0. | |
1684 | */ | |
1685 | if (wakeup_cpu0()) | |
1686 | start_cpu0(); | |
ea530692 PA |
1687 | } |
1688 | } | |
1689 | ||
a21f5d88 AN |
1690 | void native_play_dead(void) |
1691 | { | |
1692 | play_dead_common(); | |
86886e55 | 1693 | tboot_shutdown(TB_SHUTDOWN_WFS); |
ea530692 PA |
1694 | |
1695 | mwait_play_dead(); /* Only returns on failure */ | |
1a022e3f BO |
1696 | if (cpuidle_play_dead()) |
1697 | hlt_play_dead(); | |
a21f5d88 AN |
1698 | } |
1699 | ||
69c18c15 | 1700 | #else /* ... !CONFIG_HOTPLUG_CPU */ |
93be71b6 | 1701 | int native_cpu_disable(void) |
69c18c15 GC |
1702 | { |
1703 | return -ENOSYS; | |
1704 | } | |
1705 | ||
93be71b6 | 1706 | void native_cpu_die(unsigned int cpu) |
69c18c15 GC |
1707 | { |
1708 | /* We said "no" in __cpu_disable */ | |
1709 | BUG(); | |
1710 | } | |
a21f5d88 AN |
1711 | |
1712 | void native_play_dead(void) | |
1713 | { | |
1714 | BUG(); | |
1715 | } | |
1716 | ||
68a1c3f8 | 1717 | #endif |