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KVM: VMX: disable apicv by default
[linux.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <[email protected]>
13 * Yaniv Kamay <[email protected]>
4d5c5d0f
BAY		 14 * Amit Shah <[email protected]>
15 * Ben-Ami Yassour <[email protected]>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
313a3dc7 30
18068523 31#include <linux/clocksource.h>
4d5c5d0f 32#include <linux/interrupt.h>
313a3dc7
CO		 33#include <linux/kvm.h>
34#include <linux/fs.h>
35#include <linux/vmalloc.h>
5fb76f9b 36#include <linux/module.h>
0de10343 37#include <linux/mman.h>
2bacc55c 38#include <linux/highmem.h>
19de40a8 39#include <linux/iommu.h>
62c476c7 40#include <linux/intel-iommu.h>
c8076604 41#include <linux/cpufreq.h>
18863bdd 42#include <linux/user-return-notifier.h>
a983fb23 43#include <linux/srcu.h>
5a0e3ad6 44#include <linux/slab.h>
ff9d07a0 45#include <linux/perf_event.h>
7bee342a 46#include <linux/uaccess.h>
af585b92 47#include <linux/hash.h>
a1b60c1c 48#include <linux/pci.h>
16e8d74d
MT		 49#include <linux/timekeeper_internal.h>
50#include <linux/pvclock_gtod.h>
aec51dc4 51#include <trace/events/kvm.h>
2ed152af 52
229456fc
MT		 53#define CREATE_TRACE_POINTS
54#include "trace.h"
043405e1 55
24f1e32c 56#include <asm/debugreg.h>
d825ed0a 57#include <asm/msr.h>
a5f61300 58#include <asm/desc.h>
0bed3b56 59#include <asm/mtrr.h>
890ca9ae 60#include <asm/mce.h>
7cf30855 61#include <asm/i387.h>
1361b83a 62#include <asm/fpu-internal.h> /* Ugh! */
98918833 63#include <asm/xcr.h>
1d5f066e 64#include <asm/pvclock.h>
217fc9cf 65#include <asm/div64.h>
043405e1 66
313a3dc7 67#define MAX_IO_MSRS 256
890ca9ae 68#define KVM_MAX_MCE_BANKS 32
5854dbca 69#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 70
0f65dd70
AK		 71#define emul_to_vcpu(ctxt) \
72 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
73
50a37eb4
JR		 74/* EFER defaults:
75 * - enable syscall per default because its emulated by KVM
76 * - enable LME and LMA per default on 64 bit KVM
77 */
78#ifdef CONFIG_X86_64
1260edbe
LJ		 79static
80u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 81#else
1260edbe 82static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 83#endif
313a3dc7 84
ba1389b7
AK		 85#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
86#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 87
cb142eb7 88static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 89static void process_nmi(struct kvm_vcpu *vcpu);
674eea0f 90
97896d04 91struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 92EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 93
476bc001
RR		 94static bool ignore_msrs = 0;
95module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 96
92a1f12d
JR		 97bool kvm_has_tsc_control;
98EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
99u32 kvm_max_guest_tsc_khz;
100EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
101
cc578287
ZA		 102/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
103static u32 tsc_tolerance_ppm = 250;
104module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
105
18863bdd
AK		 106#define KVM_NR_SHARED_MSRS 16
107
108struct kvm_shared_msrs_global {
109 int nr;
2bf78fa7 110 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 111};
112
113struct kvm_shared_msrs {
114 struct user_return_notifier urn;
115 bool registered;
2bf78fa7
SY		 116 struct kvm_shared_msr_values {
117 u64 host;
118 u64 curr;
119 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 120};
121
122static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
123static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs);
124
417bc304 125struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 126 { "pf_fixed", VCPU_STAT(pf_fixed) },
127 { "pf_guest", VCPU_STAT(pf_guest) },
128 { "tlb_flush", VCPU_STAT(tlb_flush) },
129 { "invlpg", VCPU_STAT(invlpg) },
130 { "exits", VCPU_STAT(exits) },
131 { "io_exits", VCPU_STAT(io_exits) },
132 { "mmio_exits", VCPU_STAT(mmio_exits) },
133 { "signal_exits", VCPU_STAT(signal_exits) },
134 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 135 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 136 { "halt_exits", VCPU_STAT(halt_exits) },
137 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 138 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 139 { "request_irq", VCPU_STAT(request_irq_exits) },
140 { "irq_exits", VCPU_STAT(irq_exits) },
141 { "host_state_reload", VCPU_STAT(host_state_reload) },
142 { "efer_reload", VCPU_STAT(efer_reload) },
143 { "fpu_reload", VCPU_STAT(fpu_reload) },
144 { "insn_emulation", VCPU_STAT(insn_emulation) },
145 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 146 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 147 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 148 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
149 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
150 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
151 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
152 { "mmu_flooded", VM_STAT(mmu_flooded) },
153 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 154 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 155 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 156 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 157 { "largepages", VM_STAT(lpages) },
417bc304
HB		 158 { NULL }
159};
160
2acf923e
DC		 161u64 __read_mostly host_xcr0;
162
b6785def 163static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 164
8b6e4547 165static int kvm_vcpu_reset(struct kvm_vcpu *vcpu);
d6aa1000 166
af585b92
GN		 167static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
168{
169 int i;
170 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
171 vcpu->arch.apf.gfns[i] = ~0;
172}
173
18863bdd
AK		 174static void kvm_on_user_return(struct user_return_notifier *urn)
175{
176 unsigned slot;
18863bdd
AK		 177 struct kvm_shared_msrs *locals
178 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 179 struct kvm_shared_msr_values *values;
18863bdd
AK		 180
181 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 182 values = &locals->values[slot];
183 if (values->host != values->curr) {
184 wrmsrl(shared_msrs_global.msrs[slot], values->host);
185 values->curr = values->host;
18863bdd
AK		 186 }
187 }
188 locals->registered = false;
189 user_return_notifier_unregister(urn);
190}
191
2bf78fa7 192static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 193{
2bf78fa7 194 struct kvm_shared_msrs *smsr;
18863bdd
AK		 195 u64 value;
196
2bf78fa7
SY		 197 smsr = &__get_cpu_var(shared_msrs);
198 /* only read, and nobody should modify it at this time,
199 * so don't need lock */
200 if (slot >= shared_msrs_global.nr) {
201 printk(KERN_ERR "kvm: invalid MSR slot!");
202 return;
203 }
204 rdmsrl_safe(msr, &value);
205 smsr->values[slot].host = value;
206 smsr->values[slot].curr = value;
207}
208
209void kvm_define_shared_msr(unsigned slot, u32 msr)
210{
18863bdd
AK		 211 if (slot >= shared_msrs_global.nr)
212 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 213 shared_msrs_global.msrs[slot] = msr;
214 /* we need ensured the shared_msr_global have been updated */
215 smp_wmb();
18863bdd
AK		 216}
217EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
218
219static void kvm_shared_msr_cpu_online(void)
220{
221 unsigned i;
18863bdd
AK		 222
223 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 224 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 225}
226
d5696725 227void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd
AK		 228{
229 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
230
2bf78fa7 231 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 232 return;
2bf78fa7
SY		 233 smsr->values[slot].curr = value;
234 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 235 if (!smsr->registered) {
236 smsr->urn.on_user_return = kvm_on_user_return;
237 user_return_notifier_register(&smsr->urn);
238 smsr->registered = true;
239 }
240}
241EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
242
3548bab5
AK		 243static void drop_user_return_notifiers(void *ignore)
244{
245 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
246
247 if (smsr->registered)
248 kvm_on_user_return(&smsr->urn);
249}
250
6866b83e
CO		 251u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
252{
8a5a87d9 253 return vcpu->arch.apic_base;
6866b83e
CO		 254}
255EXPORT_SYMBOL_GPL(kvm_get_apic_base);
256
257void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
258{
259 /* TODO: reserve bits check */
8a5a87d9 260 kvm_lapic_set_base(vcpu, data);
6866b83e
CO		 261}
262EXPORT_SYMBOL_GPL(kvm_set_apic_base);
263
3fd28fce
ED		 264#define EXCPT_BENIGN 0
265#define EXCPT_CONTRIBUTORY 1
266#define EXCPT_PF 2
267
268static int exception_class(int vector)
269{
270 switch (vector) {
271 case PF_VECTOR:
272 return EXCPT_PF;
273 case DE_VECTOR:
274 case TS_VECTOR:
275 case NP_VECTOR:
276 case SS_VECTOR:
277 case GP_VECTOR:
278 return EXCPT_CONTRIBUTORY;
279 default:
280 break;
281 }
282 return EXCPT_BENIGN;
283}
284
285static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 286 unsigned nr, bool has_error, u32 error_code,
287 bool reinject)
3fd28fce
ED		 288{
289 u32 prev_nr;
290 int class1, class2;
291
3842d135
AK		 292 kvm_make_request(KVM_REQ_EVENT, vcpu);
293
3fd28fce
ED		 294 if (!vcpu->arch.exception.pending) {
295 queue:
296 vcpu->arch.exception.pending = true;
297 vcpu->arch.exception.has_error_code = has_error;
298 vcpu->arch.exception.nr = nr;
299 vcpu->arch.exception.error_code = error_code;
3f0fd292 300 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 301 return;
302 }
303
304 /* to check exception */
305 prev_nr = vcpu->arch.exception.nr;
306 if (prev_nr == DF_VECTOR) {
307 /* triple fault -> shutdown */
a8eeb04a 308 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 309 return;
310 }
311 class1 = exception_class(prev_nr);
312 class2 = exception_class(nr);
313 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
314 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
315 /* generate double fault per SDM Table 5-5 */
316 vcpu->arch.exception.pending = true;
317 vcpu->arch.exception.has_error_code = true;
318 vcpu->arch.exception.nr = DF_VECTOR;
319 vcpu->arch.exception.error_code = 0;
320 } else
321 /* replace previous exception with a new one in a hope
322 that instruction re-execution will regenerate lost
323 exception */
324 goto queue;
325}
326
298101da
AK		 327void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
328{
ce7ddec4 329 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 330}
331EXPORT_SYMBOL_GPL(kvm_queue_exception);
332
ce7ddec4
JR		 333void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
334{
335 kvm_multiple_exception(vcpu, nr, false, 0, true);
336}
337EXPORT_SYMBOL_GPL(kvm_requeue_exception);
338
db8fcefa 339void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 340{
db8fcefa
AP		 341 if (err)
342 kvm_inject_gp(vcpu, 0);
343 else
344 kvm_x86_ops->skip_emulated_instruction(vcpu);
345}
346EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 347
6389ee94 348void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 349{
350 ++vcpu->stat.pf_guest;
6389ee94
AK		 351 vcpu->arch.cr2 = fault->address;
352 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 353}
27d6c865 354EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 355
6389ee94 356void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 357{
6389ee94
AK		 358 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
359 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 360 else
6389ee94 361 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
d4f8cf66
JR		 362}
363
3419ffc8
SY		 364void kvm_inject_nmi(struct kvm_vcpu *vcpu)
365{
7460fb4a
AK		 366 atomic_inc(&vcpu->arch.nmi_queued);
367 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 368}
369EXPORT_SYMBOL_GPL(kvm_inject_nmi);
370
298101da
AK		 371void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
372{
ce7ddec4 373 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 374}
375EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
376
ce7ddec4
JR		 377void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
378{
379 kvm_multiple_exception(vcpu, nr, true, error_code, true);
380}
381EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
382
0a79b009
AK		 383/*
384 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
385 * a #GP and return false.
386 */
387bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 388{
0a79b009
AK		 389 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
390 return true;
391 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
392 return false;
298101da 393}
0a79b009 394EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 395
ec92fe44
JR		 396/*
397 * This function will be used to read from the physical memory of the currently
398 * running guest. The difference to kvm_read_guest_page is that this function
399 * can read from guest physical or from the guest's guest physical memory.
400 */
401int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
402 gfn_t ngfn, void *data, int offset, int len,
403 u32 access)
404{
405 gfn_t real_gfn;
406 gpa_t ngpa;
407
408 ngpa = gfn_to_gpa(ngfn);
409 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
410 if (real_gfn == UNMAPPED_GVA)
411 return -EFAULT;
412
413 real_gfn = gpa_to_gfn(real_gfn);
414
415 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
416}
417EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
418
3d06b8bf
JR		 419int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
420 void *data, int offset, int len, u32 access)
421{
422 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
423 data, offset, len, access);
424}
425
a03490ed
CO		 426/*
427 * Load the pae pdptrs. Return true is they are all valid.
428 */
ff03a073 429int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 430{
431 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
432 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
433 int i;
434 int ret;
ff03a073 435 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 436
ff03a073
JR		 437 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
438 offset * sizeof(u64), sizeof(pdpte),
439 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 440 if (ret < 0) {
441 ret = 0;
442 goto out;
443 }
444 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 445 if (is_present_gpte(pdpte[i]) &&
20c466b5 446 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 447 ret = 0;
448 goto out;
449 }
450 }
451 ret = 1;
452
ff03a073 453 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 454 __set_bit(VCPU_EXREG_PDPTR,
455 (unsigned long *)&vcpu->arch.regs_avail);
456 __set_bit(VCPU_EXREG_PDPTR,
457 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 458out:
a03490ed
CO		 459
460 return ret;
461}
cc4b6871 462EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 463
d835dfec
AK		 464static bool pdptrs_changed(struct kvm_vcpu *vcpu)
465{
ff03a073 466 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 467 bool changed = true;
3d06b8bf
JR		 468 int offset;
469 gfn_t gfn;
d835dfec
AK		 470 int r;
471
472 if (is_long_mode(vcpu) || !is_pae(vcpu))
473 return false;
474
6de4f3ad
AK		 475 if (!test_bit(VCPU_EXREG_PDPTR,
476 (unsigned long *)&vcpu->arch.regs_avail))
477 return true;
478
9f8fe504
AK		 479 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
480 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 481 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
482 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 483 if (r < 0)
484 goto out;
ff03a073 485 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 486out:
d835dfec
AK		 487
488 return changed;
489}
490
49a9b07e 491int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 492{
aad82703
SY		 493 unsigned long old_cr0 = kvm_read_cr0(vcpu);
494 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
495 X86_CR0_CD | X86_CR0_NW;
496
f9a48e6a
AK		 497 cr0 |= X86_CR0_ET;
498
ab344828 499#ifdef CONFIG_X86_64
0f12244f
GN		 500 if (cr0 & 0xffffffff00000000UL)
501 return 1;
ab344828
GN		 502#endif
503
504 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 505
0f12244f
GN		 506 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
507 return 1;
a03490ed 508
0f12244f
GN		 509 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
510 return 1;
a03490ed
CO		 511
512 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
513#ifdef CONFIG_X86_64
f6801dff 514 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 515 int cs_db, cs_l;
516
0f12244f
GN		 517 if (!is_pae(vcpu))
518 return 1;
a03490ed 519 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 520 if (cs_l)
521 return 1;
a03490ed
CO		 522 } else
523#endif
ff03a073 524 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 525 kvm_read_cr3(vcpu)))
0f12244f 526 return 1;
a03490ed
CO		 527 }
528
ad756a16
MJ		 529 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
530 return 1;
531
a03490ed 532 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 533
d170c419 534 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 535 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 536 kvm_async_pf_hash_reset(vcpu);
537 }
e5f3f027 538
aad82703
SY		 539 if ((cr0 ^ old_cr0) & update_bits)
540 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 541 return 0;
542}
2d3ad1f4 543EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 544
2d3ad1f4 545void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 546{
49a9b07e 547 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 548}
2d3ad1f4 549EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 550
2acf923e
DC		 551int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
552{
553 u64 xcr0;
554
555 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
556 if (index != XCR_XFEATURE_ENABLED_MASK)
557 return 1;
558 xcr0 = xcr;
559 if (kvm_x86_ops->get_cpl(vcpu) != 0)
560 return 1;
561 if (!(xcr0 & XSTATE_FP))
562 return 1;
563 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
564 return 1;
565 if (xcr0 & ~host_xcr0)
566 return 1;
567 vcpu->arch.xcr0 = xcr0;
568 vcpu->guest_xcr0_loaded = 0;
569 return 0;
570}
571
572int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
573{
574 if (__kvm_set_xcr(vcpu, index, xcr)) {
575 kvm_inject_gp(vcpu, 0);
576 return 1;
577 }
578 return 0;
579}
580EXPORT_SYMBOL_GPL(kvm_set_xcr);
581
a83b29c6 582int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 583{
fc78f519 584 unsigned long old_cr4 = kvm_read_cr4(vcpu);
c68b734f
YW		 585 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
586 X86_CR4_PAE | X86_CR4_SMEP;
0f12244f
GN		 587 if (cr4 & CR4_RESERVED_BITS)
588 return 1;
a03490ed 589
2acf923e
DC		 590 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
591 return 1;
592
c68b734f
YW		 593 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
594 return 1;
595
74dc2b4f
YW		 596 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_RDWRGSFS))
597 return 1;
598
a03490ed 599 if (is_long_mode(vcpu)) {
0f12244f
GN		 600 if (!(cr4 & X86_CR4_PAE))
601 return 1;
a2edf57f
AK		 602 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
603 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 604 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
605 kvm_read_cr3(vcpu)))
0f12244f
GN		 606 return 1;
607
ad756a16
MJ		 608 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
609 if (!guest_cpuid_has_pcid(vcpu))
610 return 1;
611
612 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
613 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
614 return 1;
615 }
616
5e1746d6 617 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 618 return 1;
a03490ed 619
ad756a16
MJ		 620 if (((cr4 ^ old_cr4) & pdptr_bits) ||
621 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 622 kvm_mmu_reset_context(vcpu);
0f12244f 623
2acf923e 624 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
00b27a3e 625 kvm_update_cpuid(vcpu);
2acf923e 626
0f12244f
GN		 627 return 0;
628}
2d3ad1f4 629EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 630
2390218b 631int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 632{
9f8fe504 633 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 634 kvm_mmu_sync_roots(vcpu);
d835dfec 635 kvm_mmu_flush_tlb(vcpu);
0f12244f 636 return 0;
d835dfec
AK		 637 }
638
a03490ed 639 if (is_long_mode(vcpu)) {
471842ec 640 if (kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) {
ad756a16
MJ		 641 if (cr3 & CR3_PCID_ENABLED_RESERVED_BITS)
642 return 1;
643 } else
644 if (cr3 & CR3_L_MODE_RESERVED_BITS)
645 return 1;
a03490ed
CO		 646 } else {
647 if (is_pae(vcpu)) {
0f12244f
GN		 648 if (cr3 & CR3_PAE_RESERVED_BITS)
649 return 1;
ff03a073
JR		 650 if (is_paging(vcpu) &&
651 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
0f12244f 652 return 1;
a03490ed
CO		 653 }
654 /*
655 * We don't check reserved bits in nonpae mode, because
656 * this isn't enforced, and VMware depends on this.
657 */
658 }
659
a03490ed
CO		 660 /*
661 * Does the new cr3 value map to physical memory? (Note, we
662 * catch an invalid cr3 even in real-mode, because it would
663 * cause trouble later on when we turn on paging anyway.)
664 *
665 * A real CPU would silently accept an invalid cr3 and would
666 * attempt to use it - with largely undefined (and often hard
667 * to debug) behavior on the guest side.
668 */
669 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
0f12244f
GN		 670 return 1;
671 vcpu->arch.cr3 = cr3;
aff48baa 672 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
0f12244f
GN		 673 vcpu->arch.mmu.new_cr3(vcpu);
674 return 0;
675}
2d3ad1f4 676EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 677
eea1cff9 678int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 679{
0f12244f
GN		 680 if (cr8 & CR8_RESERVED_BITS)
681 return 1;
a03490ed
CO		 682 if (irqchip_in_kernel(vcpu->kvm))
683 kvm_lapic_set_tpr(vcpu, cr8);
684 else
ad312c7c 685 vcpu->arch.cr8 = cr8;
0f12244f
GN		 686 return 0;
687}
2d3ad1f4 688EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 689
2d3ad1f4 690unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 691{
692 if (irqchip_in_kernel(vcpu->kvm))
693 return kvm_lapic_get_cr8(vcpu);
694 else
ad312c7c 695 return vcpu->arch.cr8;
a03490ed 696}
2d3ad1f4 697EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 698
c8639010
JK		 699static void kvm_update_dr7(struct kvm_vcpu *vcpu)
700{
701 unsigned long dr7;
702
703 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
704 dr7 = vcpu->arch.guest_debug_dr7;
705 else
706 dr7 = vcpu->arch.dr7;
707 kvm_x86_ops->set_dr7(vcpu, dr7);
708 vcpu->arch.switch_db_regs = (dr7 & DR7_BP_EN_MASK);
709}
710
338dbc97 711static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 712{
713 switch (dr) {
714 case 0 ... 3:
715 vcpu->arch.db[dr] = val;
716 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
717 vcpu->arch.eff_db[dr] = val;
718 break;
719 case 4:
338dbc97
GN		 720 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
721 return 1; /* #UD */
020df079
GN		 722 /* fall through */
723 case 6:
338dbc97
GN		 724 if (val & 0xffffffff00000000ULL)
725 return -1; /* #GP */
020df079
GN		 726 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
727 break;
728 case 5:
338dbc97
GN		 729 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
730 return 1; /* #UD */
020df079
GN		 731 /* fall through */
732 default: /* 7 */
338dbc97
GN		 733 if (val & 0xffffffff00000000ULL)
734 return -1; /* #GP */
020df079 735 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 736 kvm_update_dr7(vcpu);
020df079
GN		 737 break;
738 }
739
740 return 0;
741}
338dbc97
GN		 742
743int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
744{
745 int res;
746
747 res = __kvm_set_dr(vcpu, dr, val);
748 if (res > 0)
749 kvm_queue_exception(vcpu, UD_VECTOR);
750 else if (res < 0)
751 kvm_inject_gp(vcpu, 0);
752
753 return res;
754}
020df079
GN		 755EXPORT_SYMBOL_GPL(kvm_set_dr);
756
338dbc97 757static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 758{
759 switch (dr) {
760 case 0 ... 3:
761 *val = vcpu->arch.db[dr];
762 break;
763 case 4:
338dbc97 764 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 765 return 1;
020df079
GN		 766 /* fall through */
767 case 6:
768 *val = vcpu->arch.dr6;
769 break;
770 case 5:
338dbc97 771 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 772 return 1;
020df079
GN		 773 /* fall through */
774 default: /* 7 */
775 *val = vcpu->arch.dr7;
776 break;
777 }
778
779 return 0;
780}
338dbc97
GN		 781
782int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
783{
784 if (_kvm_get_dr(vcpu, dr, val)) {
785 kvm_queue_exception(vcpu, UD_VECTOR);
786 return 1;
787 }
788 return 0;
789}
020df079
GN		 790EXPORT_SYMBOL_GPL(kvm_get_dr);
791
022cd0e8
AK		 792bool kvm_rdpmc(struct kvm_vcpu *vcpu)
793{
794 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
795 u64 data;
796 int err;
797
798 err = kvm_pmu_read_pmc(vcpu, ecx, &data);
799 if (err)
800 return err;
801 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
802 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
803 return err;
804}
805EXPORT_SYMBOL_GPL(kvm_rdpmc);
806
043405e1
CO		 807/*
808 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
809 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
810 *
811 * This list is modified at module load time to reflect the
e3267cbb
GC		 812 * capabilities of the host cpu. This capabilities test skips MSRs that are
813 * kvm-specific. Those are put in the beginning of the list.
043405e1 814 */
e3267cbb 815
439793d4 816#define KVM_SAVE_MSRS_BEGIN 10
043405e1 817static u32 msrs_to_save[] = {
e3267cbb 818 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 819 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 820 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
c9aaa895 821 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
ae7a2a3f 822 MSR_KVM_PV_EOI_EN,
043405e1 823 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 824 MSR_STAR,
043405e1
CO		 825#ifdef CONFIG_X86_64
826 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
827#endif
e90aa41e 828 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 829};
830
831static unsigned num_msrs_to_save;
832
f1d24831 833static const u32 emulated_msrs[] = {
ba904635 834 MSR_IA32_TSC_ADJUST,
a3e06bbe 835 MSR_IA32_TSCDEADLINE,
043405e1 836 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 837 MSR_IA32_MCG_STATUS,
838 MSR_IA32_MCG_CTL,
043405e1
CO		 839};
840
b69e8cae 841static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 842{
aad82703
SY		 843 u64 old_efer = vcpu->arch.efer;
844
b69e8cae
RJ		 845 if (efer & efer_reserved_bits)
846 return 1;
15c4a640
CO		 847
848 if (is_paging(vcpu)
b69e8cae
RJ		 849 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
850 return 1;
15c4a640 851
1b2fd70c
AG		 852 if (efer & EFER_FFXSR) {
853 struct kvm_cpuid_entry2 *feat;
854
855 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 856 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
857 return 1;
1b2fd70c
AG		 858 }
859
d8017474
AG		 860 if (efer & EFER_SVME) {
861 struct kvm_cpuid_entry2 *feat;
862
863 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 864 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
865 return 1;
d8017474
AG		 866 }
867
15c4a640 868 efer &= ~EFER_LMA;
f6801dff 869 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 870
a3d204e2
SY		 871 kvm_x86_ops->set_efer(vcpu, efer);
872
aad82703
SY		 873 /* Update reserved bits */
874 if ((efer ^ old_efer) & EFER_NX)
875 kvm_mmu_reset_context(vcpu);
876
b69e8cae 877 return 0;
15c4a640
CO		 878}
879
f2b4b7dd
JR		 880void kvm_enable_efer_bits(u64 mask)
881{
882 efer_reserved_bits &= ~mask;
883}
884EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
885
886
15c4a640
CO		 887/*
888 * Writes msr value into into the appropriate "register".
889 * Returns 0 on success, non-0 otherwise.
890 * Assumes vcpu_load() was already called.
891 */
8fe8ab46 892int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 893{
8fe8ab46 894 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640
CO		 895}
896
313a3dc7
CO		 897/*
898 * Adapt set_msr() to msr_io()'s calling convention
899 */
900static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
901{
8fe8ab46
WA		 902 struct msr_data msr;
903
904 msr.data = *data;
905 msr.index = index;
906 msr.host_initiated = true;
907 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 908}
909
16e8d74d
MT		 910#ifdef CONFIG_X86_64
911struct pvclock_gtod_data {
912 seqcount_t seq;
913
914 struct { /* extract of a clocksource struct */
915 int vclock_mode;
916 cycle_t cycle_last;
917 cycle_t mask;
918 u32 mult;
919 u32 shift;
920 } clock;
921
922 /* open coded 'struct timespec' */
923 u64 monotonic_time_snsec;
924 time_t monotonic_time_sec;
925};
926
927static struct pvclock_gtod_data pvclock_gtod_data;
928
929static void update_pvclock_gtod(struct timekeeper *tk)
930{
931 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
932
933 write_seqcount_begin(&vdata->seq);
934
935 /* copy pvclock gtod data */
936 vdata->clock.vclock_mode = tk->clock->archdata.vclock_mode;
937 vdata->clock.cycle_last = tk->clock->cycle_last;
938 vdata->clock.mask = tk->clock->mask;
939 vdata->clock.mult = tk->mult;
940 vdata->clock.shift = tk->shift;
941
942 vdata->monotonic_time_sec = tk->xtime_sec
943 + tk->wall_to_monotonic.tv_sec;
944 vdata->monotonic_time_snsec = tk->xtime_nsec
945 + (tk->wall_to_monotonic.tv_nsec
946 << tk->shift);
947 while (vdata->monotonic_time_snsec >=
948 (((u64)NSEC_PER_SEC) << tk->shift)) {
949 vdata->monotonic_time_snsec -=
950 ((u64)NSEC_PER_SEC) << tk->shift;
951 vdata->monotonic_time_sec++;
952 }
953
954 write_seqcount_end(&vdata->seq);
955}
956#endif
957
958
18068523
GOC		 959static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
960{
9ed3c444
AK		 961 int version;
962 int r;
50d0a0f9 963 struct pvclock_wall_clock wc;
923de3cf 964 struct timespec boot;
18068523
GOC		 965
966 if (!wall_clock)
967 return;
968
9ed3c444
AK		 969 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
970 if (r)
971 return;
972
973 if (version & 1)
974 ++version; /* first time write, random junk */
975
976 ++version;
18068523 977
18068523
GOC		 978 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
979
50d0a0f9
GH		 980 /*
981 * The guest calculates current wall clock time by adding
34c238a1 982 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 983 * wall clock specified here. guest system time equals host
984 * system time for us, thus we must fill in host boot time here.
985 */
923de3cf 986 getboottime(&boot);
50d0a0f9 987
4b648665
BR		 988 if (kvm->arch.kvmclock_offset) {
989 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
990 boot = timespec_sub(boot, ts);
991 }
50d0a0f9
GH		 992 wc.sec = boot.tv_sec;
993 wc.nsec = boot.tv_nsec;
994 wc.version = version;
18068523
GOC		 995
996 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
997
998 version++;
999 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1000}
1001
50d0a0f9
GH		 1002static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1003{
1004 uint32_t quotient, remainder;
1005
1006 /* Don't try to replace with do_div(), this one calculates
1007 * "(dividend << 32) / divisor" */
1008 __asm__ ( "divl %4"
1009 : "=a" (quotient), "=d" (remainder)
1010 : "0" (0), "1" (dividend), "r" (divisor) );
1011 return quotient;
1012}
1013
5f4e3f88
ZA		 1014static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1015 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1016{
5f4e3f88 1017 uint64_t scaled64;
50d0a0f9
GH		 1018 int32_t shift = 0;
1019 uint64_t tps64;
1020 uint32_t tps32;
1021
5f4e3f88
ZA		 1022 tps64 = base_khz * 1000LL;
1023 scaled64 = scaled_khz * 1000LL;
50933623 1024 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1025 tps64 >>= 1;
1026 shift--;
1027 }
1028
1029 tps32 = (uint32_t)tps64;
50933623
JK		 1030 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1031 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1032 scaled64 >>= 1;
1033 else
1034 tps32 <<= 1;
50d0a0f9
GH		 1035 shift++;
1036 }
1037
5f4e3f88
ZA		 1038 *pshift = shift;
1039 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1040
5f4e3f88
ZA		 1041 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1042 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 1043}
1044
759379dd
ZA		 1045static inline u64 get_kernel_ns(void)
1046{
1047 struct timespec ts;
1048
1049 WARN_ON(preemptible());
1050 ktime_get_ts(&ts);
1051 monotonic_to_bootbased(&ts);
1052 return timespec_to_ns(&ts);
50d0a0f9
GH		 1053}
1054
d828199e 1055#ifdef CONFIG_X86_64
16e8d74d 1056static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1057#endif
16e8d74d 1058
c8076604 1059static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
c285545f 1060unsigned long max_tsc_khz;
c8076604 1061
cc578287 1062static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
8cfdc000 1063{
cc578287
ZA		 1064 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1065 vcpu->arch.virtual_tsc_shift);
8cfdc000
ZA		 1066}
1067
cc578287 1068static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1069{
cc578287
ZA		 1070 u64 v = (u64)khz * (1000000 + ppm);
1071 do_div(v, 1000000);
1072 return v;
1e993611
JR		 1073}
1074
cc578287 1075static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
759379dd 1076{
cc578287
ZA		 1077 u32 thresh_lo, thresh_hi;
1078 int use_scaling = 0;
217fc9cf 1079
c285545f
ZA		 1080 /* Compute a scale to convert nanoseconds in TSC cycles */
1081 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
cc578287
ZA		 1082 &vcpu->arch.virtual_tsc_shift,
1083 &vcpu->arch.virtual_tsc_mult);
1084 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1085
1086 /*
1087 * Compute the variation in TSC rate which is acceptable
1088 * within the range of tolerance and decide if the
1089 * rate being applied is within that bounds of the hardware
1090 * rate. If so, no scaling or compensation need be done.
1091 */
1092 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1093 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1094 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1095 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1096 use_scaling = 1;
1097 }
1098 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
c285545f
ZA		 1099}
1100
1101static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1102{
e26101b1 1103 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1104 vcpu->arch.virtual_tsc_mult,
1105 vcpu->arch.virtual_tsc_shift);
e26101b1 1106 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1107 return tsc;
1108}
1109
b48aa97e
MT		 1110void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1111{
1112#ifdef CONFIG_X86_64
1113 bool vcpus_matched;
1114 bool do_request = false;
1115 struct kvm_arch *ka = &vcpu->kvm->arch;
1116 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1117
1118 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1119 atomic_read(&vcpu->kvm->online_vcpus));
1120
1121 if (vcpus_matched && gtod->clock.vclock_mode == VCLOCK_TSC)
1122 if (!ka->use_master_clock)
1123 do_request = 1;
1124
1125 if (!vcpus_matched && ka->use_master_clock)
1126 do_request = 1;
1127
1128 if (do_request)
1129 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1130
1131 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1132 atomic_read(&vcpu->kvm->online_vcpus),
1133 ka->use_master_clock, gtod->clock.vclock_mode);
1134#endif
1135}
1136
ba904635
WA		 1137static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1138{
1139 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1140 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1141}
1142
8fe8ab46 1143void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1144{
1145 struct kvm *kvm = vcpu->kvm;
f38e098f 1146 u64 offset, ns, elapsed;
99e3e30a 1147 unsigned long flags;
02626b6a 1148 s64 usdiff;
b48aa97e 1149 bool matched;
8fe8ab46 1150 u64 data = msr->data;
99e3e30a 1151
038f8c11 1152 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
857e4099 1153 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1154 ns = get_kernel_ns();
f38e098f 1155 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6
ZA		 1156
1157 /* n.b - signed multiplication and division required */
02626b6a 1158 usdiff = data - kvm->arch.last_tsc_write;
5d3cb0f6 1159#ifdef CONFIG_X86_64
02626b6a 1160 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
5d3cb0f6
ZA		 1161#else
1162 /* do_div() only does unsigned */
1163 asm("idivl %2; xor %%edx, %%edx"
02626b6a
MT		 1164 : "=A"(usdiff)
1165 : "A"(usdiff * 1000), "rm"(vcpu->arch.virtual_tsc_khz));
5d3cb0f6 1166#endif
02626b6a
MT		 1167 do_div(elapsed, 1000);
1168 usdiff -= elapsed;
1169 if (usdiff < 0)
1170 usdiff = -usdiff;
f38e098f
ZA		 1171
1172 /*
5d3cb0f6
ZA		 1173 * Special case: TSC write with a small delta (1 second) of virtual
1174 * cycle time against real time is interpreted as an attempt to
1175 * synchronize the CPU.
1176 *
1177 * For a reliable TSC, we can match TSC offsets, and for an unstable
1178 * TSC, we add elapsed time in this computation. We could let the
1179 * compensation code attempt to catch up if we fall behind, but
1180 * it's better to try to match offsets from the beginning.
1181 */
02626b6a 1182 if (usdiff < USEC_PER_SEC &&
5d3cb0f6 1183 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1184 if (!check_tsc_unstable()) {
e26101b1 1185 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1186 pr_debug("kvm: matched tsc offset for %llu\n", data);
1187 } else {
857e4099 1188 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6
ZA		 1189 data += delta;
1190 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1191 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1192 }
b48aa97e 1193 matched = true;
e26101b1
ZA		 1194 } else {
1195 /*
1196 * We split periods of matched TSC writes into generations.
1197 * For each generation, we track the original measured
1198 * nanosecond time, offset, and write, so if TSCs are in
1199 * sync, we can match exact offset, and if not, we can match
4a969980 1200 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1201 *
1202 * These values are tracked in kvm->arch.cur_xxx variables.
1203 */
1204 kvm->arch.cur_tsc_generation++;
1205 kvm->arch.cur_tsc_nsec = ns;
1206 kvm->arch.cur_tsc_write = data;
1207 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1208 matched = false;
e26101b1
ZA		 1209 pr_debug("kvm: new tsc generation %u, clock %llu\n",
1210 kvm->arch.cur_tsc_generation, data);
f38e098f 1211 }
e26101b1
ZA		 1212
1213 /*
1214 * We also track th most recent recorded KHZ, write and time to
1215 * allow the matching interval to be extended at each write.
1216 */
f38e098f
ZA		 1217 kvm->arch.last_tsc_nsec = ns;
1218 kvm->arch.last_tsc_write = data;
5d3cb0f6 1219 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a
ZA		 1220
1221 /* Reset of TSC must disable overshoot protection below */
1222 vcpu->arch.hv_clock.tsc_timestamp = 0;
b183aa58 1223 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1224
1225 /* Keep track of which generation this VCPU has synchronized to */
1226 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1227 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1228 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1229
ba904635
WA		 1230 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1231 update_ia32_tsc_adjust_msr(vcpu, offset);
e26101b1
ZA		 1232 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1233 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1234
1235 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
1236 if (matched)
1237 kvm->arch.nr_vcpus_matched_tsc++;
1238 else
1239 kvm->arch.nr_vcpus_matched_tsc = 0;
1240
1241 kvm_track_tsc_matching(vcpu);
1242 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1243}
e26101b1 1244
99e3e30a
ZA		 1245EXPORT_SYMBOL_GPL(kvm_write_tsc);
1246
d828199e
MT		 1247#ifdef CONFIG_X86_64
1248
1249static cycle_t read_tsc(void)
1250{
1251 cycle_t ret;
1252 u64 last;
1253
1254 /*
1255 * Empirically, a fence (of type that depends on the CPU)
1256 * before rdtsc is enough to ensure that rdtsc is ordered
1257 * with respect to loads. The various CPU manuals are unclear
1258 * as to whether rdtsc can be reordered with later loads,
1259 * but no one has ever seen it happen.
1260 */
1261 rdtsc_barrier();
1262 ret = (cycle_t)vget_cycles();
1263
1264 last = pvclock_gtod_data.clock.cycle_last;
1265
1266 if (likely(ret >= last))
1267 return ret;
1268
1269 /*
1270 * GCC likes to generate cmov here, but this branch is extremely
1271 * predictable (it's just a funciton of time and the likely is
1272 * very likely) and there's a data dependence, so force GCC
1273 * to generate a branch instead. I don't barrier() because
1274 * we don't actually need a barrier, and if this function
1275 * ever gets inlined it will generate worse code.
1276 */
1277 asm volatile ("");
1278 return last;
1279}
1280
1281static inline u64 vgettsc(cycle_t *cycle_now)
1282{
1283 long v;
1284 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1285
1286 *cycle_now = read_tsc();
1287
1288 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1289 return v * gtod->clock.mult;
1290}
1291
1292static int do_monotonic(struct timespec *ts, cycle_t *cycle_now)
1293{
1294 unsigned long seq;
1295 u64 ns;
1296 int mode;
1297 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1298
1299 ts->tv_nsec = 0;
1300 do {
1301 seq = read_seqcount_begin(&gtod->seq);
1302 mode = gtod->clock.vclock_mode;
1303 ts->tv_sec = gtod->monotonic_time_sec;
1304 ns = gtod->monotonic_time_snsec;
1305 ns += vgettsc(cycle_now);
1306 ns >>= gtod->clock.shift;
1307 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1308 timespec_add_ns(ts, ns);
1309
1310 return mode;
1311}
1312
1313/* returns true if host is using tsc clocksource */
1314static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1315{
1316 struct timespec ts;
1317
1318 /* checked again under seqlock below */
1319 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1320 return false;
1321
1322 if (do_monotonic(&ts, cycle_now) != VCLOCK_TSC)
1323 return false;
1324
1325 monotonic_to_bootbased(&ts);
1326 *kernel_ns = timespec_to_ns(&ts);
1327
1328 return true;
1329}
1330#endif
1331
1332/*
1333 *
b48aa97e
MT		 1334 * Assuming a stable TSC across physical CPUS, and a stable TSC
1335 * across virtual CPUs, the following condition is possible.
1336 * Each numbered line represents an event visible to both
d828199e
MT		 1337 * CPUs at the next numbered event.
1338 *
1339 * "timespecX" represents host monotonic time. "tscX" represents
1340 * RDTSC value.
1341 *
1342 * VCPU0 on CPU0 | VCPU1 on CPU1
1343 *
1344 * 1. read timespec0,tsc0
1345 * 2. | timespec1 = timespec0 + N
1346 * | tsc1 = tsc0 + M
1347 * 3. transition to guest | transition to guest
1348 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1349 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1350 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1351 *
1352 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1353 *
1354 * - ret0 < ret1
1355 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1356 * ...
1357 * - 0 < N - M => M < N
1358 *
1359 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1360 * always the case (the difference between two distinct xtime instances
1361 * might be smaller then the difference between corresponding TSC reads,
1362 * when updating guest vcpus pvclock areas).
1363 *
1364 * To avoid that problem, do not allow visibility of distinct
1365 * system_timestamp/tsc_timestamp values simultaneously: use a master
1366 * copy of host monotonic time values. Update that master copy
1367 * in lockstep.
1368 *
b48aa97e 1369 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1370 *
1371 */
1372
1373static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1374{
1375#ifdef CONFIG_X86_64
1376 struct kvm_arch *ka = &kvm->arch;
1377 int vclock_mode;
b48aa97e
MT		 1378 bool host_tsc_clocksource, vcpus_matched;
1379
1380 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1381 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1382
1383 /*
1384 * If the host uses TSC clock, then passthrough TSC as stable
1385 * to the guest.
1386 */
b48aa97e 1387 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1388 &ka->master_kernel_ns,
1389 &ka->master_cycle_now);
1390
b48aa97e
MT		 1391 ka->use_master_clock = host_tsc_clocksource & vcpus_matched;
1392
d828199e
MT		 1393 if (ka->use_master_clock)
1394 atomic_set(&kvm_guest_has_master_clock, 1);
1395
1396 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1397 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1398 vcpus_matched);
d828199e
MT		 1399#endif
1400}
1401
34c238a1 1402static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1403{
d828199e 1404 unsigned long flags, this_tsc_khz;
18068523 1405 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1406 struct kvm_arch *ka = &v->kvm->arch;
18068523 1407 void *shared_kaddr;
1d5f066e 1408 s64 kernel_ns, max_kernel_ns;
d828199e 1409 u64 tsc_timestamp, host_tsc;
78c0337a 1410 struct pvclock_vcpu_time_info *guest_hv_clock;
51d59c6b 1411 u8 pvclock_flags;
d828199e
MT		 1412 bool use_master_clock;
1413
1414 kernel_ns = 0;
1415 host_tsc = 0;
18068523 1416
18068523
GOC		 1417 /* Keep irq disabled to prevent changes to the clock */
1418 local_irq_save(flags);
cc578287 1419 this_tsc_khz = __get_cpu_var(cpu_tsc_khz);
8cfdc000 1420 if (unlikely(this_tsc_khz == 0)) {
c285545f 1421 local_irq_restore(flags);
34c238a1 1422 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
8cfdc000
ZA		 1423 return 1;
1424 }
18068523 1425
d828199e
MT		 1426 /*
1427 * If the host uses TSC clock, then passthrough TSC as stable
1428 * to the guest.
1429 */
1430 spin_lock(&ka->pvclock_gtod_sync_lock);
1431 use_master_clock = ka->use_master_clock;
1432 if (use_master_clock) {
1433 host_tsc = ka->master_cycle_now;
1434 kernel_ns = ka->master_kernel_ns;
1435 }
1436 spin_unlock(&ka->pvclock_gtod_sync_lock);
1437 if (!use_master_clock) {
1438 host_tsc = native_read_tsc();
1439 kernel_ns = get_kernel_ns();
1440 }
1441
1442 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc);
1443
c285545f
ZA		 1444 /*
1445 * We may have to catch up the TSC to match elapsed wall clock
1446 * time for two reasons, even if kvmclock is used.
1447 * 1) CPU could have been running below the maximum TSC rate
1448 * 2) Broken TSC compensation resets the base at each VCPU
1449 * entry to avoid unknown leaps of TSC even when running
1450 * again on the same CPU. This may cause apparent elapsed
1451 * time to disappear, and the guest to stand still or run
1452 * very slowly.
1453 */
1454 if (vcpu->tsc_catchup) {
1455 u64 tsc = compute_guest_tsc(v, kernel_ns);
1456 if (tsc > tsc_timestamp) {
f1e2b260 1457 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1458 tsc_timestamp = tsc;
1459 }
50d0a0f9
GH		 1460 }
1461
18068523
GOC		 1462 local_irq_restore(flags);
1463
c285545f
ZA		 1464 if (!vcpu->time_page)
1465 return 0;
18068523 1466
1d5f066e
ZA		 1467 /*
1468 * Time as measured by the TSC may go backwards when resetting the base
1469 * tsc_timestamp. The reason for this is that the TSC resolution is
1470 * higher than the resolution of the other clock scales. Thus, many
1471 * possible measurments of the TSC correspond to one measurement of any
1472 * other clock, and so a spread of values is possible. This is not a
1473 * problem for the computation of the nanosecond clock; with TSC rates
1474 * around 1GHZ, there can only be a few cycles which correspond to one
1475 * nanosecond value, and any path through this code will inevitably
1476 * take longer than that. However, with the kernel_ns value itself,
1477 * the precision may be much lower, down to HZ granularity. If the
1478 * first sampling of TSC against kernel_ns ends in the low part of the
1479 * range, and the second in the high end of the range, we can get:
1480 *
1481 * (TSC - offset_low) * S + kns_old > (TSC - offset_high) * S + kns_new
1482 *
1483 * As the sampling errors potentially range in the thousands of cycles,
1484 * it is possible such a time value has already been observed by the
1485 * guest. To protect against this, we must compute the system time as
1486 * observed by the guest and ensure the new system time is greater.
1487 */
1488 max_kernel_ns = 0;
b183aa58 1489 if (vcpu->hv_clock.tsc_timestamp) {
1d5f066e
ZA		 1490 max_kernel_ns = vcpu->last_guest_tsc -
1491 vcpu->hv_clock.tsc_timestamp;
1492 max_kernel_ns = pvclock_scale_delta(max_kernel_ns,
1493 vcpu->hv_clock.tsc_to_system_mul,
1494 vcpu->hv_clock.tsc_shift);
1495 max_kernel_ns += vcpu->last_kernel_ns;
1496 }
afbcf7ab 1497
e48672fa 1498 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
5f4e3f88
ZA		 1499 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1500 &vcpu->hv_clock.tsc_shift,
1501 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1502 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1503 }
1504
d828199e
MT		 1505 /* with a master <monotonic time, tsc value> tuple,
1506 * pvclock clock reads always increase at the (scaled) rate
1507 * of guest TSC - no need to deal with sampling errors.
1508 */
1509 if (!use_master_clock) {
1510 if (max_kernel_ns > kernel_ns)
1511 kernel_ns = max_kernel_ns;
1512 }
8cfdc000 1513 /* With all the info we got, fill in the values */
1d5f066e 1514 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1515 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1d5f066e 1516 vcpu->last_kernel_ns = kernel_ns;
28e4639a 1517 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1518
18068523
GOC		 1519 /*
1520 * The interface expects us to write an even number signaling that the
1521 * update is finished. Since the guest won't see the intermediate
50d0a0f9 1522 * state, we just increase by 2 at the end.
18068523 1523 */
50d0a0f9 1524 vcpu->hv_clock.version += 2;
18068523 1525
8fd75e12 1526 shared_kaddr = kmap_atomic(vcpu->time_page);
18068523 1527
78c0337a
MT		 1528 guest_hv_clock = shared_kaddr + vcpu->time_offset;
1529
1530 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1531 pvclock_flags = (guest_hv_clock->flags & PVCLOCK_GUEST_STOPPED);
1532
1533 if (vcpu->pvclock_set_guest_stopped_request) {
1534 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1535 vcpu->pvclock_set_guest_stopped_request = false;
1536 }
1537
d828199e
MT		 1538 /* If the host uses TSC clocksource, then it is stable */
1539 if (use_master_clock)
1540 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1541
78c0337a
MT		 1542 vcpu->hv_clock.flags = pvclock_flags;
1543
18068523 1544 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 1545 sizeof(vcpu->hv_clock));
18068523 1546
8fd75e12 1547 kunmap_atomic(shared_kaddr);
18068523
GOC		 1548
1549 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
8cfdc000 1550 return 0;
c8076604
GH		 1551}
1552
9ba075a6
AK		 1553static bool msr_mtrr_valid(unsigned msr)
1554{
1555 switch (msr) {
1556 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1557 case MSR_MTRRfix64K_00000:
1558 case MSR_MTRRfix16K_80000:
1559 case MSR_MTRRfix16K_A0000:
1560 case MSR_MTRRfix4K_C0000:
1561 case MSR_MTRRfix4K_C8000:
1562 case MSR_MTRRfix4K_D0000:
1563 case MSR_MTRRfix4K_D8000:
1564 case MSR_MTRRfix4K_E0000:
1565 case MSR_MTRRfix4K_E8000:
1566 case MSR_MTRRfix4K_F0000:
1567 case MSR_MTRRfix4K_F8000:
1568 case MSR_MTRRdefType:
1569 case MSR_IA32_CR_PAT:
1570 return true;
1571 case 0x2f8:
1572 return true;
1573 }
1574 return false;
1575}
1576
d6289b93
MT		 1577static bool valid_pat_type(unsigned t)
1578{
1579 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1580}
1581
1582static bool valid_mtrr_type(unsigned t)
1583{
1584 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1585}
1586
1587static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1588{
1589 int i;
1590
1591 if (!msr_mtrr_valid(msr))
1592 return false;
1593
1594 if (msr == MSR_IA32_CR_PAT) {
1595 for (i = 0; i < 8; i++)
1596 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1597 return false;
1598 return true;
1599 } else if (msr == MSR_MTRRdefType) {
1600 if (data & ~0xcff)
1601 return false;
1602 return valid_mtrr_type(data & 0xff);
1603 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1604 for (i = 0; i < 8 ; i++)
1605 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1606 return false;
1607 return true;
1608 }
1609
1610 /* variable MTRRs */
1611 return valid_mtrr_type(data & 0xff);
1612}
1613
9ba075a6
AK		 1614static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1615{
0bed3b56
SY		 1616 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1617
d6289b93 1618 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 1619 return 1;
1620
0bed3b56
SY		 1621 if (msr == MSR_MTRRdefType) {
1622 vcpu->arch.mtrr_state.def_type = data;
1623 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1624 } else if (msr == MSR_MTRRfix64K_00000)
1625 p[0] = data;
1626 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1627 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1628 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1629 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1630 else if (msr == MSR_IA32_CR_PAT)
1631 vcpu->arch.pat = data;
1632 else { /* Variable MTRRs */
1633 int idx, is_mtrr_mask;
1634 u64 *pt;
1635
1636 idx = (msr - 0x200) / 2;
1637 is_mtrr_mask = msr - 0x200 - 2 * idx;
1638 if (!is_mtrr_mask)
1639 pt =
1640 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1641 else
1642 pt =
1643 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1644 *pt = data;
1645 }
1646
1647 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 1648 return 0;
1649}
15c4a640 1650
890ca9ae 1651static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1652{
890ca9ae
YH		 1653 u64 mcg_cap = vcpu->arch.mcg_cap;
1654 unsigned bank_num = mcg_cap & 0xff;
1655
15c4a640 1656 switch (msr) {
15c4a640 1657 case MSR_IA32_MCG_STATUS:
890ca9ae 1658 vcpu->arch.mcg_status = data;
15c4a640 1659 break;
c7ac679c 1660 case MSR_IA32_MCG_CTL:
890ca9ae
YH		 1661 if (!(mcg_cap & MCG_CTL_P))
1662 return 1;
1663 if (data != 0 && data != ~(u64)0)
1664 return -1;
1665 vcpu->arch.mcg_ctl = data;
1666 break;
1667 default:
1668 if (msr >= MSR_IA32_MC0_CTL &&
1669 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1670 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1671 /* only 0 or all 1s can be written to IA32_MCi_CTL
1672 * some Linux kernels though clear bit 10 in bank 4 to
1673 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1674 * this to avoid an uncatched #GP in the guest
1675 */
890ca9ae 1676 if ((offset & 0x3) == 0 &&
114be429 1677 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
YH		 1678 return -1;
1679 vcpu->arch.mce_banks[offset] = data;
1680 break;
1681 }
1682 return 1;
1683 }
1684 return 0;
1685}
1686
ffde22ac
ES		 1687static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1688{
1689 struct kvm *kvm = vcpu->kvm;
1690 int lm = is_long_mode(vcpu);
1691 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1692 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1693 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1694 : kvm->arch.xen_hvm_config.blob_size_32;
1695 u32 page_num = data & ~PAGE_MASK;
1696 u64 page_addr = data & PAGE_MASK;
1697 u8 *page;
1698 int r;
1699
1700 r = -E2BIG;
1701 if (page_num >= blob_size)
1702 goto out;
1703 r = -ENOMEM;
ff5c2c03
SL		 1704 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1705 if (IS_ERR(page)) {
1706 r = PTR_ERR(page);
ffde22ac 1707 goto out;
ff5c2c03 1708 }
ffde22ac
ES		 1709 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1710 goto out_free;
1711 r = 0;
1712out_free:
1713 kfree(page);
1714out:
1715 return r;
1716}
1717
55cd8e5a
GN		 1718static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1719{
1720 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1721}
1722
1723static bool kvm_hv_msr_partition_wide(u32 msr)
1724{
1725 bool r = false;
1726 switch (msr) {
1727 case HV_X64_MSR_GUEST_OS_ID:
1728 case HV_X64_MSR_HYPERCALL:
1729 r = true;
1730 break;
1731 }
1732
1733 return r;
1734}
1735
1736static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1737{
1738 struct kvm *kvm = vcpu->kvm;
1739
1740 switch (msr) {
1741 case HV_X64_MSR_GUEST_OS_ID:
1742 kvm->arch.hv_guest_os_id = data;
1743 /* setting guest os id to zero disables hypercall page */
1744 if (!kvm->arch.hv_guest_os_id)
1745 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1746 break;
1747 case HV_X64_MSR_HYPERCALL: {
1748 u64 gfn;
1749 unsigned long addr;
1750 u8 instructions[4];
1751
1752 /* if guest os id is not set hypercall should remain disabled */
1753 if (!kvm->arch.hv_guest_os_id)
1754 break;
1755 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1756 kvm->arch.hv_hypercall = data;
1757 break;
1758 }
1759 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1760 addr = gfn_to_hva(kvm, gfn);
1761 if (kvm_is_error_hva(addr))
1762 return 1;
1763 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1764 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
8b0cedff 1765 if (__copy_to_user((void __user *)addr, instructions, 4))
55cd8e5a
GN		 1766 return 1;
1767 kvm->arch.hv_hypercall = data;
1768 break;
1769 }
1770 default:
a737f256
CD		 1771 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1772 "data 0x%llx\n", msr, data);
55cd8e5a
GN		 1773 return 1;
1774 }
1775 return 0;
1776}
1777
1778static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1779{
10388a07
GN		 1780 switch (msr) {
1781 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1782 unsigned long addr;
55cd8e5a 1783
10388a07
GN		 1784 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1785 vcpu->arch.hv_vapic = data;
1786 break;
1787 }
1788 addr = gfn_to_hva(vcpu->kvm, data >>
1789 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1790 if (kvm_is_error_hva(addr))
1791 return 1;
8b0cedff 1792 if (__clear_user((void __user *)addr, PAGE_SIZE))
10388a07
GN		 1793 return 1;
1794 vcpu->arch.hv_vapic = data;
1795 break;
1796 }
1797 case HV_X64_MSR_EOI:
1798 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1799 case HV_X64_MSR_ICR:
1800 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1801 case HV_X64_MSR_TPR:
1802 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1803 default:
a737f256
CD		 1804 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1805 "data 0x%llx\n", msr, data);
10388a07
GN		 1806 return 1;
1807 }
1808
1809 return 0;
55cd8e5a
GN		 1810}
1811
344d9588
GN		 1812static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1813{
1814 gpa_t gpa = data & ~0x3f;
1815
4a969980 1816 /* Bits 2:5 are reserved, Should be zero */
6adba527 1817 if (data & 0x3c)
344d9588
GN		 1818 return 1;
1819
1820 vcpu->arch.apf.msr_val = data;
1821
1822 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1823 kvm_clear_async_pf_completion_queue(vcpu);
1824 kvm_async_pf_hash_reset(vcpu);
1825 return 0;
1826 }
1827
1828 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa))
1829 return 1;
1830
6adba527 1831 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 1832 kvm_async_pf_wakeup_all(vcpu);
1833 return 0;
1834}
1835
12f9a48f
GC		 1836static void kvmclock_reset(struct kvm_vcpu *vcpu)
1837{
1838 if (vcpu->arch.time_page) {
1839 kvm_release_page_dirty(vcpu->arch.time_page);
1840 vcpu->arch.time_page = NULL;
1841 }
1842}
1843
c9aaa895
GC		 1844static void accumulate_steal_time(struct kvm_vcpu *vcpu)
1845{
1846 u64 delta;
1847
1848 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1849 return;
1850
1851 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
1852 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1853 vcpu->arch.st.accum_steal = delta;
1854}
1855
1856static void record_steal_time(struct kvm_vcpu *vcpu)
1857{
1858 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1859 return;
1860
1861 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1862 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
1863 return;
1864
1865 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
1866 vcpu->arch.st.steal.version += 2;
1867 vcpu->arch.st.accum_steal = 0;
1868
1869 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1870 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
1871}
1872
8fe8ab46 1873int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 1874{
5753785f 1875 bool pr = false;
8fe8ab46
WA		 1876 u32 msr = msr_info->index;
1877 u64 data = msr_info->data;
5753785f 1878
15c4a640 1879 switch (msr) {
15c4a640 1880 case MSR_EFER:
b69e8cae 1881 return set_efer(vcpu, data);
8f1589d9
AP		 1882 case MSR_K7_HWCR:
1883 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 1884 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 1885 data &= ~(u64)0x8; /* ignore TLB cache disable */
8f1589d9 1886 if (data != 0) {
a737f256
CD		 1887 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1888 data);
8f1589d9
AP		 1889 return 1;
1890 }
15c4a640 1891 break;
f7c6d140
AP		 1892 case MSR_FAM10H_MMIO_CONF_BASE:
1893 if (data != 0) {
a737f256
CD		 1894 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1895 "0x%llx\n", data);
f7c6d140
AP		 1896 return 1;
1897 }
15c4a640 1898 break;
c323c0e5 1899 case MSR_AMD64_NB_CFG:
c7ac679c 1900 break;
b5e2fec0
AG		 1901 case MSR_IA32_DEBUGCTLMSR:
1902 if (!data) {
1903 /* We support the non-activated case already */
1904 break;
1905 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1906 /* Values other than LBR and BTF are vendor-specific,
1907 thus reserved and should throw a #GP */
1908 return 1;
1909 }
a737f256
CD		 1910 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1911 __func__, data);
b5e2fec0 1912 break;
15c4a640
CO		 1913 case MSR_IA32_UCODE_REV:
1914 case MSR_IA32_UCODE_WRITE:
61a6bd67 1915 case MSR_VM_HSAVE_PA:
6098ca93 1916 case MSR_AMD64_PATCH_LOADER:
15c4a640 1917 break;
9ba075a6
AK		 1918 case 0x200 ... 0x2ff:
1919 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 1920 case MSR_IA32_APICBASE:
1921 kvm_set_apic_base(vcpu, data);
1922 break;
0105d1a5
GN		 1923 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1924 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 1925 case MSR_IA32_TSCDEADLINE:
1926 kvm_set_lapic_tscdeadline_msr(vcpu, data);
1927 break;
ba904635
WA		 1928 case MSR_IA32_TSC_ADJUST:
1929 if (guest_cpuid_has_tsc_adjust(vcpu)) {
1930 if (!msr_info->host_initiated) {
1931 u64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
1932 kvm_x86_ops->adjust_tsc_offset(vcpu, adj, true);
1933 }
1934 vcpu->arch.ia32_tsc_adjust_msr = data;
1935 }
1936 break;
15c4a640 1937 case MSR_IA32_MISC_ENABLE:
ad312c7c 1938 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 1939 break;
11c6bffa 1940 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1941 case MSR_KVM_WALL_CLOCK:
1942 vcpu->kvm->arch.wall_clock = data;
1943 kvm_write_wall_clock(vcpu->kvm, data);
1944 break;
11c6bffa 1945 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 1946 case MSR_KVM_SYSTEM_TIME: {
12f9a48f 1947 kvmclock_reset(vcpu);
18068523
GOC		 1948
1949 vcpu->arch.time = data;
c285545f 1950 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
18068523
GOC		 1951
1952 /* we verify if the enable bit is set... */
1953 if (!(data & 1))
1954 break;
1955
1956 /* ...but clean it before doing the actual write */
1957 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
1958
18068523
GOC		 1959 vcpu->arch.time_page =
1960 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523 1961
32cad84f 1962 if (is_error_page(vcpu->arch.time_page))
18068523 1963 vcpu->arch.time_page = NULL;
32cad84f 1964
18068523
GOC		 1965 break;
1966 }
344d9588
GN		 1967 case MSR_KVM_ASYNC_PF_EN:
1968 if (kvm_pv_enable_async_pf(vcpu, data))
1969 return 1;
1970 break;
c9aaa895
GC		 1971 case MSR_KVM_STEAL_TIME:
1972
1973 if (unlikely(!sched_info_on()))
1974 return 1;
1975
1976 if (data & KVM_STEAL_RESERVED_MASK)
1977 return 1;
1978
1979 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
1980 data & KVM_STEAL_VALID_BITS))
1981 return 1;
1982
1983 vcpu->arch.st.msr_val = data;
1984
1985 if (!(data & KVM_MSR_ENABLED))
1986 break;
1987
1988 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1989
1990 preempt_disable();
1991 accumulate_steal_time(vcpu);
1992 preempt_enable();
1993
1994 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
1995
1996 break;
ae7a2a3f
MT		 1997 case MSR_KVM_PV_EOI_EN:
1998 if (kvm_lapic_enable_pv_eoi(vcpu, data))
1999 return 1;
2000 break;
c9aaa895 2001
890ca9ae
YH		 2002 case MSR_IA32_MCG_CTL:
2003 case MSR_IA32_MCG_STATUS:
2004 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2005 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 2006
2007 /* Performance counters are not protected by a CPUID bit,
2008 * so we should check all of them in the generic path for the sake of
2009 * cross vendor migration.
2010 * Writing a zero into the event select MSRs disables them,
2011 * which we perfectly emulate ;-). Any other value should be at least
2012 * reported, some guests depend on them.
2013 */
71db6023
AP		 2014 case MSR_K7_EVNTSEL0:
2015 case MSR_K7_EVNTSEL1:
2016 case MSR_K7_EVNTSEL2:
2017 case MSR_K7_EVNTSEL3:
2018 if (data != 0)
a737f256
CD		 2019 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2020 "0x%x data 0x%llx\n", msr, data);
71db6023
AP		 2021 break;
2022 /* at least RHEL 4 unconditionally writes to the perfctr registers,
2023 * so we ignore writes to make it happy.
2024 */
71db6023
AP		 2025 case MSR_K7_PERFCTR0:
2026 case MSR_K7_PERFCTR1:
2027 case MSR_K7_PERFCTR2:
2028 case MSR_K7_PERFCTR3:
a737f256
CD		 2029 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2030 "0x%x data 0x%llx\n", msr, data);
71db6023 2031 break;
5753785f
GN		 2032 case MSR_P6_PERFCTR0:
2033 case MSR_P6_PERFCTR1:
2034 pr = true;
2035 case MSR_P6_EVNTSEL0:
2036 case MSR_P6_EVNTSEL1:
2037 if (kvm_pmu_msr(vcpu, msr))
2038 return kvm_pmu_set_msr(vcpu, msr, data);
2039
2040 if (pr || data != 0)
a737f256
CD		 2041 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2042 "0x%x data 0x%llx\n", msr, data);
5753785f 2043 break;
84e0cefa
JS		 2044 case MSR_K7_CLK_CTL:
2045 /*
2046 * Ignore all writes to this no longer documented MSR.
2047 * Writes are only relevant for old K7 processors,
2048 * all pre-dating SVM, but a recommended workaround from
4a969980 2049 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2050 * affected processor models on the command line, hence
2051 * the need to ignore the workaround.
2052 */
2053 break;
55cd8e5a
GN		 2054 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2055 if (kvm_hv_msr_partition_wide(msr)) {
2056 int r;
2057 mutex_lock(&vcpu->kvm->lock);
2058 r = set_msr_hyperv_pw(vcpu, msr, data);
2059 mutex_unlock(&vcpu->kvm->lock);
2060 return r;
2061 } else
2062 return set_msr_hyperv(vcpu, msr, data);
2063 break;
91c9c3ed 2064 case MSR_IA32_BBL_CR_CTL3:
2065 /* Drop writes to this legacy MSR -- see rdmsr
2066 * counterpart for further detail.
2067 */
a737f256 2068 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
91c9c3ed 2069 break;
2b036c6b
BO		 2070 case MSR_AMD64_OSVW_ID_LENGTH:
2071 if (!guest_cpuid_has_osvw(vcpu))
2072 return 1;
2073 vcpu->arch.osvw.length = data;
2074 break;
2075 case MSR_AMD64_OSVW_STATUS:
2076 if (!guest_cpuid_has_osvw(vcpu))
2077 return 1;
2078 vcpu->arch.osvw.status = data;
2079 break;
15c4a640 2080 default:
ffde22ac
ES		 2081 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2082 return xen_hvm_config(vcpu, data);
f5132b01
GN		 2083 if (kvm_pmu_msr(vcpu, msr))
2084 return kvm_pmu_set_msr(vcpu, msr, data);
ed85c068 2085 if (!ignore_msrs) {
a737f256
CD		 2086 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2087 msr, data);
ed85c068
AP		 2088 return 1;
2089 } else {
a737f256
CD		 2090 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2091 msr, data);
ed85c068
AP		 2092 break;
2093 }
15c4a640
CO		 2094 }
2095 return 0;
2096}
2097EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2098
2099
2100/*
2101 * Reads an msr value (of 'msr_index') into 'pdata'.
2102 * Returns 0 on success, non-0 otherwise.
2103 * Assumes vcpu_load() was already called.
2104 */
2105int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2106{
2107 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
2108}
2109
9ba075a6
AK		 2110static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2111{
0bed3b56
SY		 2112 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
2113
9ba075a6
AK		 2114 if (!msr_mtrr_valid(msr))
2115 return 1;
2116
0bed3b56
SY		 2117 if (msr == MSR_MTRRdefType)
2118 *pdata = vcpu->arch.mtrr_state.def_type +
2119 (vcpu->arch.mtrr_state.enabled << 10);
2120 else if (msr == MSR_MTRRfix64K_00000)
2121 *pdata = p[0];
2122 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
2123 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
2124 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
2125 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
2126 else if (msr == MSR_IA32_CR_PAT)
2127 *pdata = vcpu->arch.pat;
2128 else { /* Variable MTRRs */
2129 int idx, is_mtrr_mask;
2130 u64 *pt;
2131
2132 idx = (msr - 0x200) / 2;
2133 is_mtrr_mask = msr - 0x200 - 2 * idx;
2134 if (!is_mtrr_mask)
2135 pt =
2136 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
2137 else
2138 pt =
2139 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
2140 *pdata = *pt;
2141 }
2142
9ba075a6
AK		 2143 return 0;
2144}
2145
890ca9ae 2146static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2147{
2148 u64 data;
890ca9ae
YH		 2149 u64 mcg_cap = vcpu->arch.mcg_cap;
2150 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2151
2152 switch (msr) {
15c4a640
CO		 2153 case MSR_IA32_P5_MC_ADDR:
2154 case MSR_IA32_P5_MC_TYPE:
890ca9ae
YH		 2155 data = 0;
2156 break;
15c4a640 2157 case MSR_IA32_MCG_CAP:
890ca9ae
YH		 2158 data = vcpu->arch.mcg_cap;
2159 break;
c7ac679c 2160 case MSR_IA32_MCG_CTL:
890ca9ae
YH		 2161 if (!(mcg_cap & MCG_CTL_P))
2162 return 1;
2163 data = vcpu->arch.mcg_ctl;
2164 break;
2165 case MSR_IA32_MCG_STATUS:
2166 data = vcpu->arch.mcg_status;
2167 break;
2168 default:
2169 if (msr >= MSR_IA32_MC0_CTL &&
2170 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
2171 u32 offset = msr - MSR_IA32_MC0_CTL;
2172 data = vcpu->arch.mce_banks[offset];
2173 break;
2174 }
2175 return 1;
2176 }
2177 *pdata = data;
2178 return 0;
2179}
2180
55cd8e5a
GN		 2181static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2182{
2183 u64 data = 0;
2184 struct kvm *kvm = vcpu->kvm;
2185
2186 switch (msr) {
2187 case HV_X64_MSR_GUEST_OS_ID:
2188 data = kvm->arch.hv_guest_os_id;
2189 break;
2190 case HV_X64_MSR_HYPERCALL:
2191 data = kvm->arch.hv_hypercall;
2192 break;
2193 default:
a737f256 2194 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2195 return 1;
2196 }
2197
2198 *pdata = data;
2199 return 0;
2200}
2201
2202static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2203{
2204 u64 data = 0;
2205
2206 switch (msr) {
2207 case HV_X64_MSR_VP_INDEX: {
2208 int r;
2209 struct kvm_vcpu *v;
2210 kvm_for_each_vcpu(r, v, vcpu->kvm)
2211 if (v == vcpu)
2212 data = r;
2213 break;
2214 }
10388a07
GN		 2215 case HV_X64_MSR_EOI:
2216 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
2217 case HV_X64_MSR_ICR:
2218 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
2219 case HV_X64_MSR_TPR:
2220 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
14fa67ee 2221 case HV_X64_MSR_APIC_ASSIST_PAGE:
d1613ad5
MW		 2222 data = vcpu->arch.hv_vapic;
2223 break;
55cd8e5a 2224 default:
a737f256 2225 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2226 return 1;
2227 }
2228 *pdata = data;
2229 return 0;
2230}
2231
890ca9ae
YH		 2232int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2233{
2234 u64 data;
2235
2236 switch (msr) {
890ca9ae 2237 case MSR_IA32_PLATFORM_ID:
15c4a640 2238 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2239 case MSR_IA32_DEBUGCTLMSR:
2240 case MSR_IA32_LASTBRANCHFROMIP:
2241 case MSR_IA32_LASTBRANCHTOIP:
2242 case MSR_IA32_LASTINTFROMIP:
2243 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 2244 case MSR_K8_SYSCFG:
2245 case MSR_K7_HWCR:
61a6bd67 2246 case MSR_VM_HSAVE_PA:
9e699624 2247 case MSR_K7_EVNTSEL0:
1f3ee616 2248 case MSR_K7_PERFCTR0:
1fdbd48c 2249 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2250 case MSR_AMD64_NB_CFG:
f7c6d140 2251 case MSR_FAM10H_MMIO_CONF_BASE:
15c4a640
CO		 2252 data = 0;
2253 break;
5753785f
GN		 2254 case MSR_P6_PERFCTR0:
2255 case MSR_P6_PERFCTR1:
2256 case MSR_P6_EVNTSEL0:
2257 case MSR_P6_EVNTSEL1:
2258 if (kvm_pmu_msr(vcpu, msr))
2259 return kvm_pmu_get_msr(vcpu, msr, pdata);
2260 data = 0;
2261 break;
742bc670
MT		 2262 case MSR_IA32_UCODE_REV:
2263 data = 0x100000000ULL;
2264 break;
9ba075a6
AK		 2265 case MSR_MTRRcap:
2266 data = 0x500 | KVM_NR_VAR_MTRR;
2267 break;
2268 case 0x200 ... 0x2ff:
2269 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 2270 case 0xcd: /* fsb frequency */
2271 data = 3;
2272 break;
7b914098
JS		 2273 /*
2274 * MSR_EBC_FREQUENCY_ID
2275 * Conservative value valid for even the basic CPU models.
2276 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2277 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2278 * and 266MHz for model 3, or 4. Set Core Clock
2279 * Frequency to System Bus Frequency Ratio to 1 (bits
2280 * 31:24) even though these are only valid for CPU
2281 * models > 2, however guests may end up dividing or
2282 * multiplying by zero otherwise.
2283 */
2284 case MSR_EBC_FREQUENCY_ID:
2285 data = 1 << 24;
2286 break;
15c4a640
CO		 2287 case MSR_IA32_APICBASE:
2288 data = kvm_get_apic_base(vcpu);
2289 break;
0105d1a5
GN		 2290 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2291 return kvm_x2apic_msr_read(vcpu, msr, pdata);
2292 break;
a3e06bbe
LJ		 2293 case MSR_IA32_TSCDEADLINE:
2294 data = kvm_get_lapic_tscdeadline_msr(vcpu);
2295 break;
ba904635
WA		 2296 case MSR_IA32_TSC_ADJUST:
2297 data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2298 break;
15c4a640 2299 case MSR_IA32_MISC_ENABLE:
ad312c7c 2300 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2301 break;
847f0ad8
AG		 2302 case MSR_IA32_PERF_STATUS:
2303 /* TSC increment by tick */
2304 data = 1000ULL;
2305 /* CPU multiplier */
2306 data |= (((uint64_t)4ULL) << 40);
2307 break;
15c4a640 2308 case MSR_EFER:
f6801dff 2309 data = vcpu->arch.efer;
15c4a640 2310 break;
18068523 2311 case MSR_KVM_WALL_CLOCK:
11c6bffa 2312 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2313 data = vcpu->kvm->arch.wall_clock;
2314 break;
2315 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2316 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 2317 data = vcpu->arch.time;
2318 break;
344d9588
GN		 2319 case MSR_KVM_ASYNC_PF_EN:
2320 data = vcpu->arch.apf.msr_val;
2321 break;
c9aaa895
GC		 2322 case MSR_KVM_STEAL_TIME:
2323 data = vcpu->arch.st.msr_val;
2324 break;
1d92128f
MT		 2325 case MSR_KVM_PV_EOI_EN:
2326 data = vcpu->arch.pv_eoi.msr_val;
2327 break;
890ca9ae
YH		 2328 case MSR_IA32_P5_MC_ADDR:
2329 case MSR_IA32_P5_MC_TYPE:
2330 case MSR_IA32_MCG_CAP:
2331 case MSR_IA32_MCG_CTL:
2332 case MSR_IA32_MCG_STATUS:
2333 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2334 return get_msr_mce(vcpu, msr, pdata);
84e0cefa
JS		 2335 case MSR_K7_CLK_CTL:
2336 /*
2337 * Provide expected ramp-up count for K7. All other
2338 * are set to zero, indicating minimum divisors for
2339 * every field.
2340 *
2341 * This prevents guest kernels on AMD host with CPU
2342 * type 6, model 8 and higher from exploding due to
2343 * the rdmsr failing.
2344 */
2345 data = 0x20000000;
2346 break;
55cd8e5a
GN		 2347 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2348 if (kvm_hv_msr_partition_wide(msr)) {
2349 int r;
2350 mutex_lock(&vcpu->kvm->lock);
2351 r = get_msr_hyperv_pw(vcpu, msr, pdata);
2352 mutex_unlock(&vcpu->kvm->lock);
2353 return r;
2354 } else
2355 return get_msr_hyperv(vcpu, msr, pdata);
2356 break;
91c9c3ed 2357 case MSR_IA32_BBL_CR_CTL3:
2358 /* This legacy MSR exists but isn't fully documented in current
2359 * silicon. It is however accessed by winxp in very narrow
2360 * scenarios where it sets bit #19, itself documented as
2361 * a "reserved" bit. Best effort attempt to source coherent
2362 * read data here should the balance of the register be
2363 * interpreted by the guest:
2364 *
2365 * L2 cache control register 3: 64GB range, 256KB size,
2366 * enabled, latency 0x1, configured
2367 */
2368 data = 0xbe702111;
2369 break;
2b036c6b
BO		 2370 case MSR_AMD64_OSVW_ID_LENGTH:
2371 if (!guest_cpuid_has_osvw(vcpu))
2372 return 1;
2373 data = vcpu->arch.osvw.length;
2374 break;
2375 case MSR_AMD64_OSVW_STATUS:
2376 if (!guest_cpuid_has_osvw(vcpu))
2377 return 1;
2378 data = vcpu->arch.osvw.status;
2379 break;
15c4a640 2380 default:
f5132b01
GN		 2381 if (kvm_pmu_msr(vcpu, msr))
2382 return kvm_pmu_get_msr(vcpu, msr, pdata);
ed85c068 2383 if (!ignore_msrs) {
a737f256 2384 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
ed85c068
AP		 2385 return 1;
2386 } else {
a737f256 2387 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
ed85c068
AP		 2388 data = 0;
2389 }
2390 break;
15c4a640
CO		 2391 }
2392 *pdata = data;
2393 return 0;
2394}
2395EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2396
313a3dc7
CO		 2397/*
2398 * Read or write a bunch of msrs. All parameters are kernel addresses.
2399 *
2400 * @return number of msrs set successfully.
2401 */
2402static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2403 struct kvm_msr_entry *entries,
2404 int (*do_msr)(struct kvm_vcpu *vcpu,
2405 unsigned index, u64 *data))
2406{
f656ce01 2407 int i, idx;
313a3dc7 2408
f656ce01 2409 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2410 for (i = 0; i < msrs->nmsrs; ++i)
2411 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2412 break;
f656ce01 2413 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2414
313a3dc7
CO		 2415 return i;
2416}
2417
2418/*
2419 * Read or write a bunch of msrs. Parameters are user addresses.
2420 *
2421 * @return number of msrs set successfully.
2422 */
2423static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2424 int (*do_msr)(struct kvm_vcpu *vcpu,
2425 unsigned index, u64 *data),
2426 int writeback)
2427{
2428 struct kvm_msrs msrs;
2429 struct kvm_msr_entry *entries;
2430 int r, n;
2431 unsigned size;
2432
2433 r = -EFAULT;
2434 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2435 goto out;
2436
2437 r = -E2BIG;
2438 if (msrs.nmsrs >= MAX_IO_MSRS)
2439 goto out;
2440
313a3dc7 2441 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2442 entries = memdup_user(user_msrs->entries, size);
2443 if (IS_ERR(entries)) {
2444 r = PTR_ERR(entries);
313a3dc7 2445 goto out;
ff5c2c03 2446 }
313a3dc7
CO		 2447
2448 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2449 if (r < 0)
2450 goto out_free;
2451
2452 r = -EFAULT;
2453 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2454 goto out_free;
2455
2456 r = n;
2457
2458out_free:
7a73c028 2459 kfree(entries);
313a3dc7
CO		 2460out:
2461 return r;
2462}
2463
018d00d2
ZX		 2464int kvm_dev_ioctl_check_extension(long ext)
2465{
2466 int r;
2467
2468 switch (ext) {
2469 case KVM_CAP_IRQCHIP:
2470 case KVM_CAP_HLT:
2471 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2472 case KVM_CAP_SET_TSS_ADDR:
07716717 2473 case KVM_CAP_EXT_CPUID:
c8076604 2474 case KVM_CAP_CLOCKSOURCE:
7837699f 2475 case KVM_CAP_PIT:
a28e4f5a 2476 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2477 case KVM_CAP_MP_STATE:
ed848624 2478 case KVM_CAP_SYNC_MMU:
a355c85c 2479 case KVM_CAP_USER_NMI:
52d939a0 2480 case KVM_CAP_REINJECT_CONTROL:
4925663a 2481 case KVM_CAP_IRQ_INJECT_STATUS:
e56d532f 2482 case KVM_CAP_ASSIGN_DEV_IRQ:
721eecbf 2483 case KVM_CAP_IRQFD:
d34e6b17 2484 case KVM_CAP_IOEVENTFD:
c5ff41ce 2485 case KVM_CAP_PIT2:
e9f42757 2486 case KVM_CAP_PIT_STATE2:
b927a3ce 2487 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2488 case KVM_CAP_XEN_HVM:
afbcf7ab 2489 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2490 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2491 case KVM_CAP_HYPERV:
10388a07 2492 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2493 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 2494 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2495 case KVM_CAP_DEBUGREGS:
d2be1651 2496 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2497 case KVM_CAP_XSAVE:
344d9588 2498 case KVM_CAP_ASYNC_PF:
92a1f12d 2499 case KVM_CAP_GET_TSC_KHZ:
07700a94 2500 case KVM_CAP_PCI_2_3:
1c0b28c2 2501 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2502 case KVM_CAP_READONLY_MEM:
7a84428a 2503 case KVM_CAP_IRQFD_RESAMPLE:
018d00d2
ZX		 2504 r = 1;
2505 break;
542472b5
LV		 2506 case KVM_CAP_COALESCED_MMIO:
2507 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2508 break;
774ead3a
AK		 2509 case KVM_CAP_VAPIC:
2510 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2511 break;
f725230a 2512 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2513 r = KVM_SOFT_MAX_VCPUS;
2514 break;
2515 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2516 r = KVM_MAX_VCPUS;
2517 break;
a988b910 2518 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2519 r = KVM_USER_MEM_SLOTS;
a988b910 2520 break;
a68a6a72
MT		 2521 case KVM_CAP_PV_MMU: /* obsolete */
2522 r = 0;
2f333bcb 2523 break;
62c476c7 2524 case KVM_CAP_IOMMU:
a1b60c1c 2525 r = iommu_present(&pci_bus_type);
62c476c7 2526 break;
890ca9ae
YH		 2527 case KVM_CAP_MCE:
2528 r = KVM_MAX_MCE_BANKS;
2529 break;
2d5b5a66
SY		 2530 case KVM_CAP_XCRS:
2531 r = cpu_has_xsave;
2532 break;
92a1f12d
JR		 2533 case KVM_CAP_TSC_CONTROL:
2534 r = kvm_has_tsc_control;
2535 break;
4d25a066
JK		 2536 case KVM_CAP_TSC_DEADLINE_TIMER:
2537 r = boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER);
2538 break;
018d00d2
ZX		 2539 default:
2540 r = 0;
2541 break;
2542 }
2543 return r;
2544
2545}
2546
043405e1
CO		 2547long kvm_arch_dev_ioctl(struct file *filp,
2548 unsigned int ioctl, unsigned long arg)
2549{
2550 void __user *argp = (void __user *)arg;
2551 long r;
2552
2553 switch (ioctl) {
2554 case KVM_GET_MSR_INDEX_LIST: {
2555 struct kvm_msr_list __user *user_msr_list = argp;
2556 struct kvm_msr_list msr_list;
2557 unsigned n;
2558
2559 r = -EFAULT;
2560 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2561 goto out;
2562 n = msr_list.nmsrs;
2563 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2564 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2565 goto out;
2566 r = -E2BIG;
e125e7b6 2567 if (n < msr_list.nmsrs)
043405e1
CO		 2568 goto out;
2569 r = -EFAULT;
2570 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2571 num_msrs_to_save * sizeof(u32)))
2572 goto out;
e125e7b6 2573 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 2574 &emulated_msrs,
2575 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2576 goto out;
2577 r = 0;
2578 break;
2579 }
674eea0f
AK		 2580 case KVM_GET_SUPPORTED_CPUID: {
2581 struct kvm_cpuid2 __user *cpuid_arg = argp;
2582 struct kvm_cpuid2 cpuid;
2583
2584 r = -EFAULT;
2585 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2586 goto out;
2587 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 2588 cpuid_arg->entries);
674eea0f
AK		 2589 if (r)
2590 goto out;
2591
2592 r = -EFAULT;
2593 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2594 goto out;
2595 r = 0;
2596 break;
2597 }
890ca9ae
YH		 2598 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2599 u64 mce_cap;
2600
2601 mce_cap = KVM_MCE_CAP_SUPPORTED;
2602 r = -EFAULT;
2603 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2604 goto out;
2605 r = 0;
2606 break;
2607 }
043405e1
CO		 2608 default:
2609 r = -EINVAL;
2610 }
2611out:
2612 return r;
2613}
2614
f5f48ee1
SY		 2615static void wbinvd_ipi(void *garbage)
2616{
2617 wbinvd();
2618}
2619
2620static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2621{
2622 return vcpu->kvm->arch.iommu_domain &&
2623 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY);
2624}
2625
313a3dc7
CO		 2626void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2627{
f5f48ee1
SY		 2628 /* Address WBINVD may be executed by guest */
2629 if (need_emulate_wbinvd(vcpu)) {
2630 if (kvm_x86_ops->has_wbinvd_exit())
2631 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2632 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2633 smp_call_function_single(vcpu->cpu,
2634 wbinvd_ipi, NULL, 1);
2635 }
2636
313a3dc7 2637 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2638
0dd6a6ed
ZA		 2639 /* Apply any externally detected TSC adjustments (due to suspend) */
2640 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2641 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2642 vcpu->arch.tsc_offset_adjustment = 0;
2643 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
2644 }
8f6055cb 2645
48434c20 2646 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5
ZA		 2647 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2648 native_read_tsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2649 if (tsc_delta < 0)
2650 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2651 if (check_tsc_unstable()) {
b183aa58
ZA		 2652 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2653 vcpu->arch.last_guest_tsc);
2654 kvm_x86_ops->write_tsc_offset(vcpu, offset);
c285545f 2655 vcpu->arch.tsc_catchup = 1;
c285545f 2656 }
d98d07ca
MT		 2657 /*
2658 * On a host with synchronized TSC, there is no need to update
2659 * kvmclock on vcpu->cpu migration
2660 */
2661 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
2662 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2663 if (vcpu->cpu != cpu)
2664 kvm_migrate_timers(vcpu);
e48672fa 2665 vcpu->cpu = cpu;
6b7d7e76 2666 }
c9aaa895
GC		 2667
2668 accumulate_steal_time(vcpu);
2669 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2670}
2671
2672void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2673{
02daab21 2674 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2675 kvm_put_guest_fpu(vcpu);
6f526ec5 2676 vcpu->arch.last_host_tsc = native_read_tsc();
313a3dc7
CO		 2677}
2678
313a3dc7
CO		 2679static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2680 struct kvm_lapic_state *s)
2681{
ad312c7c 2682 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2683
2684 return 0;
2685}
2686
2687static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2688 struct kvm_lapic_state *s)
2689{
64eb0620 2690 kvm_apic_post_state_restore(vcpu, s);
cb142eb7 2691 update_cr8_intercept(vcpu);
313a3dc7
CO		 2692
2693 return 0;
2694}
2695
f77bc6a4
ZX		 2696static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2697 struct kvm_interrupt *irq)
2698{
a50abc3b 2699 if (irq->irq < 0 || irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4
ZX		 2700 return -EINVAL;
2701 if (irqchip_in_kernel(vcpu->kvm))
2702 return -ENXIO;
f77bc6a4 2703
66fd3f7f 2704 kvm_queue_interrupt(vcpu, irq->irq, false);
3842d135 2705 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4 2706
f77bc6a4
ZX		 2707 return 0;
2708}
2709
c4abb7c9
JK		 2710static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2711{
c4abb7c9 2712 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2713
2714 return 0;
2715}
2716
b209749f
AK		 2717static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2718 struct kvm_tpr_access_ctl *tac)
2719{
2720 if (tac->flags)
2721 return -EINVAL;
2722 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2723 return 0;
2724}
2725
890ca9ae
YH		 2726static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2727 u64 mcg_cap)
2728{
2729 int r;
2730 unsigned bank_num = mcg_cap & 0xff, bank;
2731
2732 r = -EINVAL;
a9e38c3e 2733 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
YH		 2734 goto out;
2735 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2736 goto out;
2737 r = 0;
2738 vcpu->arch.mcg_cap = mcg_cap;
2739 /* Init IA32_MCG_CTL to all 1s */
2740 if (mcg_cap & MCG_CTL_P)
2741 vcpu->arch.mcg_ctl = ~(u64)0;
2742 /* Init IA32_MCi_CTL to all 1s */
2743 for (bank = 0; bank < bank_num; bank++)
2744 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2745out:
2746 return r;
2747}
2748
2749static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2750 struct kvm_x86_mce *mce)
2751{
2752 u64 mcg_cap = vcpu->arch.mcg_cap;
2753 unsigned bank_num = mcg_cap & 0xff;
2754 u64 *banks = vcpu->arch.mce_banks;
2755
2756 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2757 return -EINVAL;
2758 /*
2759 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2760 * reporting is disabled
2761 */
2762 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2763 vcpu->arch.mcg_ctl != ~(u64)0)
2764 return 0;
2765 banks += 4 * mce->bank;
2766 /*
2767 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2768 * reporting is disabled for the bank
2769 */
2770 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2771 return 0;
2772 if (mce->status & MCI_STATUS_UC) {
2773 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2774 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 2775 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
YH		 2776 return 0;
2777 }
2778 if (banks[1] & MCI_STATUS_VAL)
2779 mce->status |= MCI_STATUS_OVER;
2780 banks[2] = mce->addr;
2781 banks[3] = mce->misc;
2782 vcpu->arch.mcg_status = mce->mcg_status;
2783 banks[1] = mce->status;
2784 kvm_queue_exception(vcpu, MC_VECTOR);
2785 } else if (!(banks[1] & MCI_STATUS_VAL)
2786 || !(banks[1] & MCI_STATUS_UC)) {
2787 if (banks[1] & MCI_STATUS_VAL)
2788 mce->status |= MCI_STATUS_OVER;
2789 banks[2] = mce->addr;
2790 banks[3] = mce->misc;
2791 banks[1] = mce->status;
2792 } else
2793 banks[1] |= MCI_STATUS_OVER;
2794 return 0;
2795}
2796
3cfc3092
JK		 2797static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2798 struct kvm_vcpu_events *events)
2799{
7460fb4a 2800 process_nmi(vcpu);
03b82a30
JK		 2801 events->exception.injected =
2802 vcpu->arch.exception.pending &&
2803 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2804 events->exception.nr = vcpu->arch.exception.nr;
2805 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 2806 events->exception.pad = 0;
3cfc3092
JK		 2807 events->exception.error_code = vcpu->arch.exception.error_code;
2808
03b82a30
JK		 2809 events->interrupt.injected =
2810 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2811 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2812 events->interrupt.soft = 0;
48005f64
JK		 2813 events->interrupt.shadow =
2814 kvm_x86_ops->get_interrupt_shadow(vcpu,
2815 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
3cfc3092
JK		 2816
2817 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 2818 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 2819 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 2820 events->nmi.pad = 0;
3cfc3092
JK		 2821
2822 events->sipi_vector = vcpu->arch.sipi_vector;
2823
dab4b911 2824 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2825 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2826 | KVM_VCPUEVENT_VALID_SHADOW);
97e69aa6 2827 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 2828}
2829
2830static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2831 struct kvm_vcpu_events *events)
2832{
dab4b911 2833 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2834 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2835 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 2836 return -EINVAL;
2837
7460fb4a 2838 process_nmi(vcpu);
3cfc3092
JK		 2839 vcpu->arch.exception.pending = events->exception.injected;
2840 vcpu->arch.exception.nr = events->exception.nr;
2841 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2842 vcpu->arch.exception.error_code = events->exception.error_code;
2843
2844 vcpu->arch.interrupt.pending = events->interrupt.injected;
2845 vcpu->arch.interrupt.nr = events->interrupt.nr;
2846 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 2847 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2848 kvm_x86_ops->set_interrupt_shadow(vcpu,
2849 events->interrupt.shadow);
3cfc3092
JK		 2850
2851 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2852 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2853 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2854 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2855
dab4b911
JK		 2856 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR)
2857 vcpu->arch.sipi_vector = events->sipi_vector;
3cfc3092 2858
3842d135
AK		 2859 kvm_make_request(KVM_REQ_EVENT, vcpu);
2860
3cfc3092
JK		 2861 return 0;
2862}
2863
a1efbe77
JK		 2864static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2865 struct kvm_debugregs *dbgregs)
2866{
a1efbe77
JK		 2867 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2868 dbgregs->dr6 = vcpu->arch.dr6;
2869 dbgregs->dr7 = vcpu->arch.dr7;
2870 dbgregs->flags = 0;
97e69aa6 2871 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 2872}
2873
2874static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2875 struct kvm_debugregs *dbgregs)
2876{
2877 if (dbgregs->flags)
2878 return -EINVAL;
2879
a1efbe77
JK		 2880 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2881 vcpu->arch.dr6 = dbgregs->dr6;
2882 vcpu->arch.dr7 = dbgregs->dr7;
2883
a1efbe77
JK		 2884 return 0;
2885}
2886
2d5b5a66
SY		 2887static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2888 struct kvm_xsave *guest_xsave)
2889{
2890 if (cpu_has_xsave)
2891 memcpy(guest_xsave->region,
2892 &vcpu->arch.guest_fpu.state->xsave,
f45755b8 2893 xstate_size);
2d5b5a66
SY		 2894 else {
2895 memcpy(guest_xsave->region,
2896 &vcpu->arch.guest_fpu.state->fxsave,
2897 sizeof(struct i387_fxsave_struct));
2898 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2899 XSTATE_FPSSE;
2900 }
2901}
2902
2903static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
2904 struct kvm_xsave *guest_xsave)
2905{
2906 u64 xstate_bv =
2907 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
2908
2909 if (cpu_has_xsave)
2910 memcpy(&vcpu->arch.guest_fpu.state->xsave,
f45755b8 2911 guest_xsave->region, xstate_size);
2d5b5a66
SY		 2912 else {
2913 if (xstate_bv & ~XSTATE_FPSSE)
2914 return -EINVAL;
2915 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
2916 guest_xsave->region, sizeof(struct i387_fxsave_struct));
2917 }
2918 return 0;
2919}
2920
2921static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
2922 struct kvm_xcrs *guest_xcrs)
2923{
2924 if (!cpu_has_xsave) {
2925 guest_xcrs->nr_xcrs = 0;
2926 return;
2927 }
2928
2929 guest_xcrs->nr_xcrs = 1;
2930 guest_xcrs->flags = 0;
2931 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
2932 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
2933}
2934
2935static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
2936 struct kvm_xcrs *guest_xcrs)
2937{
2938 int i, r = 0;
2939
2940 if (!cpu_has_xsave)
2941 return -EINVAL;
2942
2943 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
2944 return -EINVAL;
2945
2946 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
2947 /* Only support XCR0 currently */
2948 if (guest_xcrs->xcrs[0].xcr == XCR_XFEATURE_ENABLED_MASK) {
2949 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
2950 guest_xcrs->xcrs[0].value);
2951 break;
2952 }
2953 if (r)
2954 r = -EINVAL;
2955 return r;
2956}
2957
1c0b28c2
EM		 2958/*
2959 * kvm_set_guest_paused() indicates to the guest kernel that it has been
2960 * stopped by the hypervisor. This function will be called from the host only.
2961 * EINVAL is returned when the host attempts to set the flag for a guest that
2962 * does not support pv clocks.
2963 */
2964static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
2965{
1c0b28c2
EM		 2966 if (!vcpu->arch.time_page)
2967 return -EINVAL;
51d59c6b 2968 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 2969 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2970 return 0;
2971}
2972
313a3dc7
CO		 2973long kvm_arch_vcpu_ioctl(struct file *filp,
2974 unsigned int ioctl, unsigned long arg)
2975{
2976 struct kvm_vcpu *vcpu = filp->private_data;
2977 void __user *argp = (void __user *)arg;
2978 int r;
d1ac91d8
AK		 2979 union {
2980 struct kvm_lapic_state *lapic;
2981 struct kvm_xsave *xsave;
2982 struct kvm_xcrs *xcrs;
2983 void *buffer;
2984 } u;
2985
2986 u.buffer = NULL;
313a3dc7
CO		 2987 switch (ioctl) {
2988 case KVM_GET_LAPIC: {
2204ae3c
MT		 2989 r = -EINVAL;
2990 if (!vcpu->arch.apic)
2991 goto out;
d1ac91d8 2992 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 2993
b772ff36 2994 r = -ENOMEM;
d1ac91d8 2995 if (!u.lapic)
b772ff36 2996 goto out;
d1ac91d8 2997 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 2998 if (r)
2999 goto out;
3000 r = -EFAULT;
d1ac91d8 3001 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3002 goto out;
3003 r = 0;
3004 break;
3005 }
3006 case KVM_SET_LAPIC: {
2204ae3c
MT		 3007 r = -EINVAL;
3008 if (!vcpu->arch.apic)
3009 goto out;
ff5c2c03 3010 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3011 if (IS_ERR(u.lapic))
3012 return PTR_ERR(u.lapic);
ff5c2c03 3013
d1ac91d8 3014 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3015 break;
3016 }
f77bc6a4
ZX		 3017 case KVM_INTERRUPT: {
3018 struct kvm_interrupt irq;
3019
3020 r = -EFAULT;
3021 if (copy_from_user(&irq, argp, sizeof irq))
3022 goto out;
3023 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3024 break;
3025 }
c4abb7c9
JK		 3026 case KVM_NMI: {
3027 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3028 break;
3029 }
313a3dc7
CO		 3030 case KVM_SET_CPUID: {
3031 struct kvm_cpuid __user *cpuid_arg = argp;
3032 struct kvm_cpuid cpuid;
3033
3034 r = -EFAULT;
3035 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3036 goto out;
3037 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3038 break;
3039 }
07716717
DK		 3040 case KVM_SET_CPUID2: {
3041 struct kvm_cpuid2 __user *cpuid_arg = argp;
3042 struct kvm_cpuid2 cpuid;
3043
3044 r = -EFAULT;
3045 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3046 goto out;
3047 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3048 cpuid_arg->entries);
07716717
DK		 3049 break;
3050 }
3051 case KVM_GET_CPUID2: {
3052 struct kvm_cpuid2 __user *cpuid_arg = argp;
3053 struct kvm_cpuid2 cpuid;
3054
3055 r = -EFAULT;
3056 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3057 goto out;
3058 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3059 cpuid_arg->entries);
07716717
DK		 3060 if (r)
3061 goto out;
3062 r = -EFAULT;
3063 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3064 goto out;
3065 r = 0;
3066 break;
3067 }
313a3dc7
CO		 3068 case KVM_GET_MSRS:
3069 r = msr_io(vcpu, argp, kvm_get_msr, 1);
3070 break;
3071 case KVM_SET_MSRS:
3072 r = msr_io(vcpu, argp, do_set_msr, 0);
3073 break;
b209749f
AK		 3074 case KVM_TPR_ACCESS_REPORTING: {
3075 struct kvm_tpr_access_ctl tac;
3076
3077 r = -EFAULT;
3078 if (copy_from_user(&tac, argp, sizeof tac))
3079 goto out;
3080 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3081 if (r)
3082 goto out;
3083 r = -EFAULT;
3084 if (copy_to_user(argp, &tac, sizeof tac))
3085 goto out;
3086 r = 0;
3087 break;
3088 };
b93463aa
AK		 3089 case KVM_SET_VAPIC_ADDR: {
3090 struct kvm_vapic_addr va;
3091
3092 r = -EINVAL;
3093 if (!irqchip_in_kernel(vcpu->kvm))
3094 goto out;
3095 r = -EFAULT;
3096 if (copy_from_user(&va, argp, sizeof va))
3097 goto out;
3098 r = 0;
3099 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
3100 break;
3101 }
890ca9ae
YH		 3102 case KVM_X86_SETUP_MCE: {
3103 u64 mcg_cap;
3104
3105 r = -EFAULT;
3106 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3107 goto out;
3108 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3109 break;
3110 }
3111 case KVM_X86_SET_MCE: {
3112 struct kvm_x86_mce mce;
3113
3114 r = -EFAULT;
3115 if (copy_from_user(&mce, argp, sizeof mce))
3116 goto out;
3117 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3118 break;
3119 }
3cfc3092
JK		 3120 case KVM_GET_VCPU_EVENTS: {
3121 struct kvm_vcpu_events events;
3122
3123 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3124
3125 r = -EFAULT;
3126 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3127 break;
3128 r = 0;
3129 break;
3130 }
3131 case KVM_SET_VCPU_EVENTS: {
3132 struct kvm_vcpu_events events;
3133
3134 r = -EFAULT;
3135 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3136 break;
3137
3138 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3139 break;
3140 }
a1efbe77
JK		 3141 case KVM_GET_DEBUGREGS: {
3142 struct kvm_debugregs dbgregs;
3143
3144 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3145
3146 r = -EFAULT;
3147 if (copy_to_user(argp, &dbgregs,
3148 sizeof(struct kvm_debugregs)))
3149 break;
3150 r = 0;
3151 break;
3152 }
3153 case KVM_SET_DEBUGREGS: {
3154 struct kvm_debugregs dbgregs;
3155
3156 r = -EFAULT;
3157 if (copy_from_user(&dbgregs, argp,
3158 sizeof(struct kvm_debugregs)))
3159 break;
3160
3161 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3162 break;
3163 }
2d5b5a66 3164 case KVM_GET_XSAVE: {
d1ac91d8 3165 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3166 r = -ENOMEM;
d1ac91d8 3167 if (!u.xsave)
2d5b5a66
SY		 3168 break;
3169
d1ac91d8 3170 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3171
3172 r = -EFAULT;
d1ac91d8 3173 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3174 break;
3175 r = 0;
3176 break;
3177 }
3178 case KVM_SET_XSAVE: {
ff5c2c03 3179 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3180 if (IS_ERR(u.xsave))
3181 return PTR_ERR(u.xsave);
2d5b5a66 3182
d1ac91d8 3183 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3184 break;
3185 }
3186 case KVM_GET_XCRS: {
d1ac91d8 3187 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3188 r = -ENOMEM;
d1ac91d8 3189 if (!u.xcrs)
2d5b5a66
SY		 3190 break;
3191
d1ac91d8 3192 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3193
3194 r = -EFAULT;
d1ac91d8 3195 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3196 sizeof(struct kvm_xcrs)))
3197 break;
3198 r = 0;
3199 break;
3200 }
3201 case KVM_SET_XCRS: {
ff5c2c03 3202 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3203 if (IS_ERR(u.xcrs))
3204 return PTR_ERR(u.xcrs);
2d5b5a66 3205
d1ac91d8 3206 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3207 break;
3208 }
92a1f12d
JR		 3209 case KVM_SET_TSC_KHZ: {
3210 u32 user_tsc_khz;
3211
3212 r = -EINVAL;
92a1f12d
JR		 3213 user_tsc_khz = (u32)arg;
3214
3215 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3216 goto out;
3217
cc578287
ZA		 3218 if (user_tsc_khz == 0)
3219 user_tsc_khz = tsc_khz;
3220
3221 kvm_set_tsc_khz(vcpu, user_tsc_khz);
92a1f12d
JR		 3222
3223 r = 0;
3224 goto out;
3225 }
3226 case KVM_GET_TSC_KHZ: {
cc578287 3227 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3228 goto out;
3229 }
1c0b28c2
EM		 3230 case KVM_KVMCLOCK_CTRL: {
3231 r = kvm_set_guest_paused(vcpu);
3232 goto out;
3233 }
313a3dc7
CO		 3234 default:
3235 r = -EINVAL;
3236 }
3237out:
d1ac91d8 3238 kfree(u.buffer);
313a3dc7
CO		 3239 return r;
3240}
3241
5b1c1493
CO		 3242int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3243{
3244 return VM_FAULT_SIGBUS;
3245}
3246
1fe779f8
CO		 3247static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3248{
3249 int ret;
3250
3251 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3252 return -EINVAL;
1fe779f8
CO		 3253 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3254 return ret;
3255}
3256
b927a3ce
SY		 3257static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3258 u64 ident_addr)
3259{
3260 kvm->arch.ept_identity_map_addr = ident_addr;
3261 return 0;
3262}
3263
1fe779f8
CO		 3264static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3265 u32 kvm_nr_mmu_pages)
3266{
3267 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3268 return -EINVAL;
3269
79fac95e 3270 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3271
3272 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3273 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3274
79fac95e 3275 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3276 return 0;
3277}
3278
3279static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3280{
39de71ec 3281 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3282}
3283
1fe779f8
CO		 3284static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3285{
3286 int r;
3287
3288 r = 0;
3289 switch (chip->chip_id) {
3290 case KVM_IRQCHIP_PIC_MASTER:
3291 memcpy(&chip->chip.pic,
3292 &pic_irqchip(kvm)->pics[0],
3293 sizeof(struct kvm_pic_state));
3294 break;
3295 case KVM_IRQCHIP_PIC_SLAVE:
3296 memcpy(&chip->chip.pic,
3297 &pic_irqchip(kvm)->pics[1],
3298 sizeof(struct kvm_pic_state));
3299 break;
3300 case KVM_IRQCHIP_IOAPIC:
eba0226b 3301 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3302 break;
3303 default:
3304 r = -EINVAL;
3305 break;
3306 }
3307 return r;
3308}
3309
3310static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3311{
3312 int r;
3313
3314 r = 0;
3315 switch (chip->chip_id) {
3316 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3317 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3318 memcpy(&pic_irqchip(kvm)->pics[0],
3319 &chip->chip.pic,
3320 sizeof(struct kvm_pic_state));
f4f51050 3321 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3322 break;
3323 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3324 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3325 memcpy(&pic_irqchip(kvm)->pics[1],
3326 &chip->chip.pic,
3327 sizeof(struct kvm_pic_state));
f4f51050 3328 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3329 break;
3330 case KVM_IRQCHIP_IOAPIC:
eba0226b 3331 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3332 break;
3333 default:
3334 r = -EINVAL;
3335 break;
3336 }
3337 kvm_pic_update_irq(pic_irqchip(kvm));
3338 return r;
3339}
3340
e0f63cb9
SY		 3341static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3342{
3343 int r = 0;
3344
894a9c55 3345 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3346 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3347 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3348 return r;
3349}
3350
3351static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3352{
3353 int r = 0;
3354
894a9c55 3355 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3356 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3357 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3358 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3359 return r;
3360}
3361
3362static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3363{
3364 int r = 0;
3365
3366 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3367 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3368 sizeof(ps->channels));
3369 ps->flags = kvm->arch.vpit->pit_state.flags;
3370 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3371 memset(&ps->reserved, 0, sizeof(ps->reserved));
e9f42757
BK		 3372 return r;
3373}
3374
3375static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3376{
3377 int r = 0, start = 0;
3378 u32 prev_legacy, cur_legacy;
3379 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3380 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3381 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3382 if (!prev_legacy && cur_legacy)
3383 start = 1;
3384 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3385 sizeof(kvm->arch.vpit->pit_state.channels));
3386 kvm->arch.vpit->pit_state.flags = ps->flags;
3387 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3388 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3389 return r;
3390}
3391
52d939a0
MT		 3392static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3393 struct kvm_reinject_control *control)
3394{
3395 if (!kvm->arch.vpit)
3396 return -ENXIO;
894a9c55 3397 mutex_lock(&kvm->arch.vpit->pit_state.lock);
26ef1924 3398 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
894a9c55 3399 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3400 return 0;
3401}
3402
95d4c16c 3403/**
60c34612
TY		 3404 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3405 * @kvm: kvm instance
3406 * @log: slot id and address to which we copy the log
95d4c16c 3407 *
60c34612
TY		 3408 * We need to keep it in mind that VCPU threads can write to the bitmap
3409 * concurrently. So, to avoid losing data, we keep the following order for
3410 * each bit:
95d4c16c 3411 *
60c34612
TY		 3412 * 1. Take a snapshot of the bit and clear it if needed.
3413 * 2. Write protect the corresponding page.
3414 * 3. Flush TLB's if needed.
3415 * 4. Copy the snapshot to the userspace.
95d4c16c 3416 *
60c34612
TY		 3417 * Between 2 and 3, the guest may write to the page using the remaining TLB
3418 * entry. This is not a problem because the page will be reported dirty at
3419 * step 4 using the snapshot taken before and step 3 ensures that successive
3420 * writes will be logged for the next call.
5bb064dc 3421 */
60c34612 3422int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3423{
7850ac54 3424 int r;
5bb064dc 3425 struct kvm_memory_slot *memslot;
60c34612
TY		 3426 unsigned long n, i;
3427 unsigned long *dirty_bitmap;
3428 unsigned long *dirty_bitmap_buffer;
3429 bool is_dirty = false;
5bb064dc 3430
79fac95e 3431 mutex_lock(&kvm->slots_lock);
5bb064dc 3432
b050b015 3433 r = -EINVAL;
bbacc0c1 3434 if (log->slot >= KVM_USER_MEM_SLOTS)
b050b015
MT		 3435 goto out;
3436
28a37544 3437 memslot = id_to_memslot(kvm->memslots, log->slot);
60c34612
TY		 3438
3439 dirty_bitmap = memslot->dirty_bitmap;
b050b015 3440 r = -ENOENT;
60c34612 3441 if (!dirty_bitmap)
b050b015
MT		 3442 goto out;
3443
87bf6e7d 3444 n = kvm_dirty_bitmap_bytes(memslot);
b050b015 3445
60c34612
TY		 3446 dirty_bitmap_buffer = dirty_bitmap + n / sizeof(long);
3447 memset(dirty_bitmap_buffer, 0, n);
b050b015 3448
60c34612 3449 spin_lock(&kvm->mmu_lock);
b050b015 3450
60c34612
TY		 3451 for (i = 0; i < n / sizeof(long); i++) {
3452 unsigned long mask;
3453 gfn_t offset;
cdfca7b3 3454
60c34612
TY		 3455 if (!dirty_bitmap[i])
3456 continue;
b050b015 3457
60c34612 3458 is_dirty = true;
914ebccd 3459
60c34612
TY		 3460 mask = xchg(&dirty_bitmap[i], 0);
3461 dirty_bitmap_buffer[i] = mask;
edde99ce 3462
60c34612
TY		 3463 offset = i * BITS_PER_LONG;
3464 kvm_mmu_write_protect_pt_masked(kvm, memslot, offset, mask);
5bb064dc 3465 }
60c34612
TY		 3466 if (is_dirty)
3467 kvm_flush_remote_tlbs(kvm);
3468
3469 spin_unlock(&kvm->mmu_lock);
3470
3471 r = -EFAULT;
3472 if (copy_to_user(log->dirty_bitmap, dirty_bitmap_buffer, n))
3473 goto out;
b050b015 3474
5bb064dc
ZX		 3475 r = 0;
3476out:
79fac95e 3477 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3478 return r;
3479}
3480
23d43cf9
CD		 3481int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event)
3482{
3483 if (!irqchip_in_kernel(kvm))
3484 return -ENXIO;
3485
3486 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3487 irq_event->irq, irq_event->level);
3488 return 0;
3489}
3490
1fe779f8
CO		 3491long kvm_arch_vm_ioctl(struct file *filp,
3492 unsigned int ioctl, unsigned long arg)
3493{
3494 struct kvm *kvm = filp->private_data;
3495 void __user *argp = (void __user *)arg;
367e1319 3496 int r = -ENOTTY;
f0d66275
DH		 3497 /*
3498 * This union makes it completely explicit to gcc-3.x
3499 * that these two variables' stack usage should be
3500 * combined, not added together.
3501 */
3502 union {
3503 struct kvm_pit_state ps;
e9f42757 3504 struct kvm_pit_state2 ps2;
c5ff41ce 3505 struct kvm_pit_config pit_config;
f0d66275 3506 } u;
1fe779f8
CO		 3507
3508 switch (ioctl) {
3509 case KVM_SET_TSS_ADDR:
3510 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 3511 break;
b927a3ce
SY		 3512 case KVM_SET_IDENTITY_MAP_ADDR: {
3513 u64 ident_addr;
3514
3515 r = -EFAULT;
3516 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3517 goto out;
3518 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 3519 break;
3520 }
1fe779f8
CO		 3521 case KVM_SET_NR_MMU_PAGES:
3522 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 3523 break;
3524 case KVM_GET_NR_MMU_PAGES:
3525 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3526 break;
3ddea128
MT		 3527 case KVM_CREATE_IRQCHIP: {
3528 struct kvm_pic *vpic;
3529
3530 mutex_lock(&kvm->lock);
3531 r = -EEXIST;
3532 if (kvm->arch.vpic)
3533 goto create_irqchip_unlock;
3e515705
AK		 3534 r = -EINVAL;
3535 if (atomic_read(&kvm->online_vcpus))
3536 goto create_irqchip_unlock;
1fe779f8 3537 r = -ENOMEM;
3ddea128
MT		 3538 vpic = kvm_create_pic(kvm);
3539 if (vpic) {
1fe779f8
CO		 3540 r = kvm_ioapic_init(kvm);
3541 if (r) {
175504cd 3542 mutex_lock(&kvm->slots_lock);
72bb2fcd 3543 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
743eeb0b
SL		 3544 &vpic->dev_master);
3545 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3546 &vpic->dev_slave);
3547 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3548 &vpic->dev_eclr);
175504cd 3549 mutex_unlock(&kvm->slots_lock);
3ddea128
MT		 3550 kfree(vpic);
3551 goto create_irqchip_unlock;
1fe779f8
CO		 3552 }
3553 } else
3ddea128
MT		 3554 goto create_irqchip_unlock;
3555 smp_wmb();
3556 kvm->arch.vpic = vpic;
3557 smp_wmb();
399ec807
AK		 3558 r = kvm_setup_default_irq_routing(kvm);
3559 if (r) {
175504cd 3560 mutex_lock(&kvm->slots_lock);
3ddea128 3561 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 3562 kvm_ioapic_destroy(kvm);
3563 kvm_destroy_pic(kvm);
3ddea128 3564 mutex_unlock(&kvm->irq_lock);
175504cd 3565 mutex_unlock(&kvm->slots_lock);
399ec807 3566 }
3ddea128
MT		 3567 create_irqchip_unlock:
3568 mutex_unlock(&kvm->lock);
1fe779f8 3569 break;
3ddea128 3570 }
7837699f 3571 case KVM_CREATE_PIT:
c5ff41ce
JK		 3572 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3573 goto create_pit;
3574 case KVM_CREATE_PIT2:
3575 r = -EFAULT;
3576 if (copy_from_user(&u.pit_config, argp,
3577 sizeof(struct kvm_pit_config)))
3578 goto out;
3579 create_pit:
79fac95e 3580 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3581 r = -EEXIST;
3582 if (kvm->arch.vpit)
3583 goto create_pit_unlock;
7837699f 3584 r = -ENOMEM;
c5ff41ce 3585 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3586 if (kvm->arch.vpit)
3587 r = 0;
269e05e4 3588 create_pit_unlock:
79fac95e 3589 mutex_unlock(&kvm->slots_lock);
7837699f 3590 break;
1fe779f8
CO		 3591 case KVM_GET_IRQCHIP: {
3592 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3593 struct kvm_irqchip *chip;
1fe779f8 3594
ff5c2c03
SL		 3595 chip = memdup_user(argp, sizeof(*chip));
3596 if (IS_ERR(chip)) {
3597 r = PTR_ERR(chip);
1fe779f8 3598 goto out;
ff5c2c03
SL		 3599 }
3600
1fe779f8
CO		 3601 r = -ENXIO;
3602 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3603 goto get_irqchip_out;
3604 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3605 if (r)
f0d66275 3606 goto get_irqchip_out;
1fe779f8 3607 r = -EFAULT;
f0d66275
DH		 3608 if (copy_to_user(argp, chip, sizeof *chip))
3609 goto get_irqchip_out;
1fe779f8 3610 r = 0;
f0d66275
DH		 3611 get_irqchip_out:
3612 kfree(chip);
1fe779f8
CO		 3613 break;
3614 }
3615 case KVM_SET_IRQCHIP: {
3616 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3617 struct kvm_irqchip *chip;
1fe779f8 3618
ff5c2c03
SL		 3619 chip = memdup_user(argp, sizeof(*chip));
3620 if (IS_ERR(chip)) {
3621 r = PTR_ERR(chip);
1fe779f8 3622 goto out;
ff5c2c03
SL		 3623 }
3624
1fe779f8
CO		 3625 r = -ENXIO;
3626 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3627 goto set_irqchip_out;
3628 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3629 if (r)
f0d66275 3630 goto set_irqchip_out;
1fe779f8 3631 r = 0;
f0d66275
DH		 3632 set_irqchip_out:
3633 kfree(chip);
1fe779f8
CO		 3634 break;
3635 }
e0f63cb9 3636 case KVM_GET_PIT: {
e0f63cb9 3637 r = -EFAULT;
f0d66275 3638 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3639 goto out;
3640 r = -ENXIO;
3641 if (!kvm->arch.vpit)
3642 goto out;
f0d66275 3643 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3644 if (r)
3645 goto out;
3646 r = -EFAULT;
f0d66275 3647 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3648 goto out;
3649 r = 0;
3650 break;
3651 }
3652 case KVM_SET_PIT: {
e0f63cb9 3653 r = -EFAULT;
f0d66275 3654 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3655 goto out;
3656 r = -ENXIO;
3657 if (!kvm->arch.vpit)
3658 goto out;
f0d66275 3659 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3660 break;
3661 }
e9f42757
BK		 3662 case KVM_GET_PIT2: {
3663 r = -ENXIO;
3664 if (!kvm->arch.vpit)
3665 goto out;
3666 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3667 if (r)
3668 goto out;
3669 r = -EFAULT;
3670 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3671 goto out;
3672 r = 0;
3673 break;
3674 }
3675 case KVM_SET_PIT2: {
3676 r = -EFAULT;
3677 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3678 goto out;
3679 r = -ENXIO;
3680 if (!kvm->arch.vpit)
3681 goto out;
3682 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 3683 break;
3684 }
52d939a0
MT		 3685 case KVM_REINJECT_CONTROL: {
3686 struct kvm_reinject_control control;
3687 r = -EFAULT;
3688 if (copy_from_user(&control, argp, sizeof(control)))
3689 goto out;
3690 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 3691 break;
3692 }
ffde22ac
ES		 3693 case KVM_XEN_HVM_CONFIG: {
3694 r = -EFAULT;
3695 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3696 sizeof(struct kvm_xen_hvm_config)))
3697 goto out;
3698 r = -EINVAL;
3699 if (kvm->arch.xen_hvm_config.flags)
3700 goto out;
3701 r = 0;
3702 break;
3703 }
afbcf7ab 3704 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3705 struct kvm_clock_data user_ns;
3706 u64 now_ns;
3707 s64 delta;
3708
3709 r = -EFAULT;
3710 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3711 goto out;
3712
3713 r = -EINVAL;
3714 if (user_ns.flags)
3715 goto out;
3716
3717 r = 0;
395c6b0a 3718 local_irq_disable();
759379dd 3719 now_ns = get_kernel_ns();
afbcf7ab 3720 delta = user_ns.clock - now_ns;
395c6b0a 3721 local_irq_enable();
afbcf7ab
GC		 3722 kvm->arch.kvmclock_offset = delta;
3723 break;
3724 }
3725 case KVM_GET_CLOCK: {
afbcf7ab
GC		 3726 struct kvm_clock_data user_ns;
3727 u64 now_ns;
3728
395c6b0a 3729 local_irq_disable();
759379dd 3730 now_ns = get_kernel_ns();
afbcf7ab 3731 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 3732 local_irq_enable();
afbcf7ab 3733 user_ns.flags = 0;
97e69aa6 3734 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 3735
3736 r = -EFAULT;
3737 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3738 goto out;
3739 r = 0;
3740 break;
3741 }
3742
1fe779f8
CO		 3743 default:
3744 ;
3745 }
3746out:
3747 return r;
3748}
3749
a16b043c 3750static void kvm_init_msr_list(void)
043405e1
CO		 3751{
3752 u32 dummy[2];
3753 unsigned i, j;
3754
e3267cbb
GC		 3755 /* skip the first msrs in the list. KVM-specific */
3756 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3757 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3758 continue;
3759 if (j < i)
3760 msrs_to_save[j] = msrs_to_save[i];
3761 j++;
3762 }
3763 num_msrs_to_save = j;
3764}
3765
bda9020e
MT		 3766static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3767 const void *v)
bbd9b64e 3768{
70252a10
AK		 3769 int handled = 0;
3770 int n;
3771
3772 do {
3773 n = min(len, 8);
3774 if (!(vcpu->arch.apic &&
3775 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
3776 && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3777 break;
3778 handled += n;
3779 addr += n;
3780 len -= n;
3781 v += n;
3782 } while (len);
bbd9b64e 3783
70252a10 3784 return handled;
bbd9b64e
CO		 3785}
3786
bda9020e 3787static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3788{
70252a10
AK		 3789 int handled = 0;
3790 int n;
3791
3792 do {
3793 n = min(len, 8);
3794 if (!(vcpu->arch.apic &&
3795 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
3796 && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3797 break;
3798 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
3799 handled += n;
3800 addr += n;
3801 len -= n;
3802 v += n;
3803 } while (len);
bbd9b64e 3804
70252a10 3805 return handled;
bbd9b64e
CO		 3806}
3807
2dafc6c2
GN		 3808static void kvm_set_segment(struct kvm_vcpu *vcpu,
3809 struct kvm_segment *var, int seg)
3810{
3811 kvm_x86_ops->set_segment(vcpu, var, seg);
3812}
3813
3814void kvm_get_segment(struct kvm_vcpu *vcpu,
3815 struct kvm_segment *var, int seg)
3816{
3817 kvm_x86_ops->get_segment(vcpu, var, seg);
3818}
3819
e459e322 3820gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
02f59dc9
JR		 3821{
3822 gpa_t t_gpa;
ab9ae313 3823 struct x86_exception exception;
02f59dc9
JR		 3824
3825 BUG_ON(!mmu_is_nested(vcpu));
3826
3827 /* NPT walks are always user-walks */
3828 access |= PFERR_USER_MASK;
ab9ae313 3829 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception);
02f59dc9
JR		 3830
3831 return t_gpa;
3832}
3833
ab9ae313
AK		 3834gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
3835 struct x86_exception *exception)
1871c602
GN		 3836{
3837 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 3838 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3839}
3840
ab9ae313
AK		 3841 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
3842 struct x86_exception *exception)
1871c602
GN		 3843{
3844 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3845 access |= PFERR_FETCH_MASK;
ab9ae313 3846 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3847}
3848
ab9ae313
AK		 3849gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
3850 struct x86_exception *exception)
1871c602
GN		 3851{
3852 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3853 access |= PFERR_WRITE_MASK;
ab9ae313 3854 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3855}
3856
3857/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 3858gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
3859 struct x86_exception *exception)
1871c602 3860{
ab9ae313 3861 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 3862}
3863
3864static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3865 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 3866 struct x86_exception *exception)
bbd9b64e
CO		 3867{
3868 void *data = val;
10589a46 3869 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 3870
3871 while (bytes) {
14dfe855 3872 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 3873 exception);
bbd9b64e 3874 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 3875 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 3876 int ret;
3877
bcc55cba 3878 if (gpa == UNMAPPED_GVA)
ab9ae313 3879 return X86EMUL_PROPAGATE_FAULT;
77c2002e 3880 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46 3881 if (ret < 0) {
c3cd7ffa 3882 r = X86EMUL_IO_NEEDED;
10589a46
MT		 3883 goto out;
3884 }
bbd9b64e 3885
77c2002e
IE		 3886 bytes -= toread;
3887 data += toread;
3888 addr += toread;
bbd9b64e 3889 }
10589a46 3890out:
10589a46 3891 return r;
bbd9b64e 3892}
77c2002e 3893
1871c602 3894/* used for instruction fetching */
0f65dd70
AK		 3895static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
3896 gva_t addr, void *val, unsigned int bytes,
bcc55cba 3897 struct x86_exception *exception)
1871c602 3898{
0f65dd70 3899 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 3900 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 3901
1871c602 3902 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
bcc55cba
AK		 3903 access | PFERR_FETCH_MASK,
3904 exception);
1871c602
GN		 3905}
3906
064aea77 3907int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 3908 gva_t addr, void *val, unsigned int bytes,
bcc55cba 3909 struct x86_exception *exception)
1871c602 3910{
0f65dd70 3911 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 3912 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 3913
1871c602 3914 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 3915 exception);
1871c602 3916}
064aea77 3917EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 3918
0f65dd70
AK		 3919static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
3920 gva_t addr, void *val, unsigned int bytes,
bcc55cba 3921 struct x86_exception *exception)
1871c602 3922{
0f65dd70 3923 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 3924 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 3925}
3926
6a4d7550 3927int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 3928 gva_t addr, void *val,
2dafc6c2 3929 unsigned int bytes,
bcc55cba 3930 struct x86_exception *exception)
77c2002e 3931{
0f65dd70 3932 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 3933 void *data = val;
3934 int r = X86EMUL_CONTINUE;
3935
3936 while (bytes) {
14dfe855
JR		 3937 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
3938 PFERR_WRITE_MASK,
ab9ae313 3939 exception);
77c2002e
IE		 3940 unsigned offset = addr & (PAGE_SIZE-1);
3941 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
3942 int ret;
3943
bcc55cba 3944 if (gpa == UNMAPPED_GVA)
ab9ae313 3945 return X86EMUL_PROPAGATE_FAULT;
77c2002e
IE		 3946 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
3947 if (ret < 0) {
c3cd7ffa 3948 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 3949 goto out;
3950 }
3951
3952 bytes -= towrite;
3953 data += towrite;
3954 addr += towrite;
3955 }
3956out:
3957 return r;
3958}
6a4d7550 3959EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 3960
af7cc7d1
XG		 3961static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
3962 gpa_t *gpa, struct x86_exception *exception,
3963 bool write)
3964{
97d64b78
AK		 3965 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
3966 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 3967
97d64b78
AK		 3968 if (vcpu_match_mmio_gva(vcpu, gva)
3969 && !permission_fault(vcpu->arch.walk_mmu, vcpu->arch.access, access)) {
bebb106a
XG		 3970 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
3971 (gva & (PAGE_SIZE - 1));
4f022648 3972 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 3973 return 1;
3974 }
3975
af7cc7d1
XG		 3976 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3977
3978 if (*gpa == UNMAPPED_GVA)
3979 return -1;
3980
3981 /* For APIC access vmexit */
3982 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3983 return 1;
3984
4f022648
XG		 3985 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
3986 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 3987 return 1;
4f022648 3988 }
bebb106a 3989
af7cc7d1
XG		 3990 return 0;
3991}
3992
3200f405 3993int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 3994 const void *val, int bytes)
bbd9b64e
CO		 3995{
3996 int ret;
3997
3998 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 3999 if (ret < 0)
bbd9b64e 4000 return 0;
f57f2ef5 4001 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4002 return 1;
4003}
4004
77d197b2
XG		 4005struct read_write_emulator_ops {
4006 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4007 int bytes);
4008 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4009 void *val, int bytes);
4010 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4011 int bytes, void *val);
4012 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4013 void *val, int bytes);
4014 bool write;
4015};
4016
4017static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4018{
4019 if (vcpu->mmio_read_completed) {
77d197b2 4020 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4021 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4022 vcpu->mmio_read_completed = 0;
4023 return 1;
4024 }
4025
4026 return 0;
4027}
4028
4029static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4030 void *val, int bytes)
4031{
4032 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
4033}
4034
4035static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4036 void *val, int bytes)
4037{
4038 return emulator_write_phys(vcpu, gpa, val, bytes);
4039}
4040
4041static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4042{
4043 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4044 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4045}
4046
4047static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4048 void *val, int bytes)
4049{
4050 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4051 return X86EMUL_IO_NEEDED;
4052}
4053
4054static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4055 void *val, int bytes)
4056{
f78146b0
AK		 4057 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4058
87da7e66 4059 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4060 return X86EMUL_CONTINUE;
4061}
4062
0fbe9b0b 4063static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4064 .read_write_prepare = read_prepare,
4065 .read_write_emulate = read_emulate,
4066 .read_write_mmio = vcpu_mmio_read,
4067 .read_write_exit_mmio = read_exit_mmio,
4068};
4069
0fbe9b0b 4070static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4071 .read_write_emulate = write_emulate,
4072 .read_write_mmio = write_mmio,
4073 .read_write_exit_mmio = write_exit_mmio,
4074 .write = true,
4075};
4076
22388a3c
XG		 4077static int emulator_read_write_onepage(unsigned long addr, void *val,
4078 unsigned int bytes,
4079 struct x86_exception *exception,
4080 struct kvm_vcpu *vcpu,
0fbe9b0b 4081 const struct read_write_emulator_ops *ops)
bbd9b64e 4082{
af7cc7d1
XG		 4083 gpa_t gpa;
4084 int handled, ret;
22388a3c 4085 bool write = ops->write;
f78146b0 4086 struct kvm_mmio_fragment *frag;
10589a46 4087
22388a3c 4088 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 4089
af7cc7d1 4090 if (ret < 0)
bbd9b64e 4091 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 4092
4093 /* For APIC access vmexit */
af7cc7d1 4094 if (ret)
bbd9b64e
CO		 4095 goto mmio;
4096
22388a3c 4097 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4098 return X86EMUL_CONTINUE;
4099
4100mmio:
4101 /*
4102 * Is this MMIO handled locally?
4103 */
22388a3c 4104 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4105 if (handled == bytes)
bbd9b64e 4106 return X86EMUL_CONTINUE;
bbd9b64e 4107
70252a10
AK		 4108 gpa += handled;
4109 bytes -= handled;
4110 val += handled;
4111
87da7e66
XG		 4112 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4113 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4114 frag->gpa = gpa;
4115 frag->data = val;
4116 frag->len = bytes;
f78146b0 4117 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4118}
4119
22388a3c
XG		 4120int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr,
4121 void *val, unsigned int bytes,
4122 struct x86_exception *exception,
0fbe9b0b 4123 const struct read_write_emulator_ops *ops)
bbd9b64e 4124{
0f65dd70 4125 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4126 gpa_t gpa;
4127 int rc;
4128
4129 if (ops->read_write_prepare &&
4130 ops->read_write_prepare(vcpu, val, bytes))
4131 return X86EMUL_CONTINUE;
4132
4133 vcpu->mmio_nr_fragments = 0;
0f65dd70 4134
bbd9b64e
CO		 4135 /* Crossing a page boundary? */
4136 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4137 int now;
bbd9b64e
CO		 4138
4139 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4140 rc = emulator_read_write_onepage(addr, val, now, exception,
4141 vcpu, ops);
4142
bbd9b64e
CO		 4143 if (rc != X86EMUL_CONTINUE)
4144 return rc;
4145 addr += now;
4146 val += now;
4147 bytes -= now;
4148 }
22388a3c 4149
f78146b0
AK		 4150 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4151 vcpu, ops);
4152 if (rc != X86EMUL_CONTINUE)
4153 return rc;
4154
4155 if (!vcpu->mmio_nr_fragments)
4156 return rc;
4157
4158 gpa = vcpu->mmio_fragments[0].gpa;
4159
4160 vcpu->mmio_needed = 1;
4161 vcpu->mmio_cur_fragment = 0;
4162
87da7e66 4163 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4164 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4165 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4166 vcpu->run->mmio.phys_addr = gpa;
4167
4168 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4169}
4170
4171static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4172 unsigned long addr,
4173 void *val,
4174 unsigned int bytes,
4175 struct x86_exception *exception)
4176{
4177 return emulator_read_write(ctxt, addr, val, bytes,
4178 exception, &read_emultor);
4179}
4180
4181int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4182 unsigned long addr,
4183 const void *val,
4184 unsigned int bytes,
4185 struct x86_exception *exception)
4186{
4187 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4188 exception, &write_emultor);
bbd9b64e 4189}
bbd9b64e 4190
daea3e73
AK		 4191#define CMPXCHG_TYPE(t, ptr, old, new) \
4192 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4193
4194#ifdef CONFIG_X86_64
4195# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4196#else
4197# define CMPXCHG64(ptr, old, new) \
9749a6c0 4198 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4199#endif
4200
0f65dd70
AK		 4201static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4202 unsigned long addr,
bbd9b64e
CO		 4203 const void *old,
4204 const void *new,
4205 unsigned int bytes,
0f65dd70 4206 struct x86_exception *exception)
bbd9b64e 4207{
0f65dd70 4208 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4209 gpa_t gpa;
4210 struct page *page;
4211 char *kaddr;
4212 bool exchanged;
2bacc55c 4213
daea3e73
AK		 4214 /* guests cmpxchg8b have to be emulated atomically */
4215 if (bytes > 8 || (bytes & (bytes - 1)))
4216 goto emul_write;
10589a46 4217
daea3e73 4218 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4219
daea3e73
AK		 4220 if (gpa == UNMAPPED_GVA ||
4221 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4222 goto emul_write;
2bacc55c 4223
daea3e73
AK		 4224 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4225 goto emul_write;
72dc67a6 4226
daea3e73 4227 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
32cad84f 4228 if (is_error_page(page))
c19b8bd6 4229 goto emul_write;
72dc67a6 4230
8fd75e12 4231 kaddr = kmap_atomic(page);
daea3e73
AK		 4232 kaddr += offset_in_page(gpa);
4233 switch (bytes) {
4234 case 1:
4235 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4236 break;
4237 case 2:
4238 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4239 break;
4240 case 4:
4241 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4242 break;
4243 case 8:
4244 exchanged = CMPXCHG64(kaddr, old, new);
4245 break;
4246 default:
4247 BUG();
2bacc55c 4248 }
8fd75e12 4249 kunmap_atomic(kaddr);
daea3e73
AK		 4250 kvm_release_page_dirty(page);
4251
4252 if (!exchanged)
4253 return X86EMUL_CMPXCHG_FAILED;
4254
f57f2ef5 4255 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4256
4257 return X86EMUL_CONTINUE;
4a5f48f6 4258
3200f405 4259emul_write:
daea3e73 4260 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4261
0f65dd70 4262 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4263}
4264
cf8f70bf
GN		 4265static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4266{
4267 /* TODO: String I/O for in kernel device */
4268 int r;
4269
4270 if (vcpu->arch.pio.in)
4271 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
4272 vcpu->arch.pio.size, pd);
4273 else
4274 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
4275 vcpu->arch.pio.port, vcpu->arch.pio.size,
4276 pd);
4277 return r;
4278}
4279
6f6fbe98
XG		 4280static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4281 unsigned short port, void *val,
4282 unsigned int count, bool in)
cf8f70bf 4283{
6f6fbe98 4284 trace_kvm_pio(!in, port, size, count);
cf8f70bf
GN		 4285
4286 vcpu->arch.pio.port = port;
6f6fbe98 4287 vcpu->arch.pio.in = in;
7972995b 4288 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4289 vcpu->arch.pio.size = size;
4290
4291 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4292 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4293 return 1;
4294 }
4295
4296 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4297 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4298 vcpu->run->io.size = size;
4299 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4300 vcpu->run->io.count = count;
4301 vcpu->run->io.port = port;
4302
4303 return 0;
4304}
4305
6f6fbe98
XG		 4306static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4307 int size, unsigned short port, void *val,
4308 unsigned int count)
cf8f70bf 4309{
ca1d4a9e 4310 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4311 int ret;
ca1d4a9e 4312
6f6fbe98
XG		 4313 if (vcpu->arch.pio.count)
4314 goto data_avail;
cf8f70bf 4315
6f6fbe98
XG		 4316 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4317 if (ret) {
4318data_avail:
4319 memcpy(val, vcpu->arch.pio_data, size * count);
7972995b 4320 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4321 return 1;
4322 }
4323
cf8f70bf
GN		 4324 return 0;
4325}
4326
6f6fbe98
XG		 4327static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4328 int size, unsigned short port,
4329 const void *val, unsigned int count)
4330{
4331 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4332
4333 memcpy(vcpu->arch.pio_data, val, size * count);
4334 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4335}
4336
bbd9b64e
CO		 4337static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4338{
4339 return kvm_x86_ops->get_segment_base(vcpu, seg);
4340}
4341
3cb16fe7 4342static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4343{
3cb16fe7 4344 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4345}
4346
f5f48ee1
SY		 4347int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4348{
4349 if (!need_emulate_wbinvd(vcpu))
4350 return X86EMUL_CONTINUE;
4351
4352 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4353 int cpu = get_cpu();
4354
4355 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4356 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4357 wbinvd_ipi, NULL, 1);
2eec7343 4358 put_cpu();
f5f48ee1 4359 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4360 } else
4361 wbinvd();
f5f48ee1
SY		 4362 return X86EMUL_CONTINUE;
4363}
4364EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4365
bcaf5cc5
AK		 4366static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4367{
4368 kvm_emulate_wbinvd(emul_to_vcpu(ctxt));
4369}
4370
717746e3 4371int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
bbd9b64e 4372{
717746e3 4373 return _kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4374}
4375
717746e3 4376int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
bbd9b64e 4377{
338dbc97 4378
717746e3 4379 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4380}
4381
52a46617 4382static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4383{
52a46617 4384 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4385}
4386
717746e3 4387static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4388{
717746e3 4389 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4390 unsigned long value;
4391
4392 switch (cr) {
4393 case 0:
4394 value = kvm_read_cr0(vcpu);
4395 break;
4396 case 2:
4397 value = vcpu->arch.cr2;
4398 break;
4399 case 3:
9f8fe504 4400 value = kvm_read_cr3(vcpu);
52a46617
GN		 4401 break;
4402 case 4:
4403 value = kvm_read_cr4(vcpu);
4404 break;
4405 case 8:
4406 value = kvm_get_cr8(vcpu);
4407 break;
4408 default:
a737f256 4409 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 4410 return 0;
4411 }
4412
4413 return value;
4414}
4415
717746e3 4416static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4417{
717746e3 4418 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4419 int res = 0;
4420
52a46617
GN		 4421 switch (cr) {
4422 case 0:
49a9b07e 4423 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4424 break;
4425 case 2:
4426 vcpu->arch.cr2 = val;
4427 break;
4428 case 3:
2390218b 4429 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4430 break;
4431 case 4:
a83b29c6 4432 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4433 break;
4434 case 8:
eea1cff9 4435 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4436 break;
4437 default:
a737f256 4438 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 4439 res = -1;
52a46617 4440 }
0f12244f
GN		 4441
4442 return res;
52a46617
GN		 4443}
4444
4cee4798
KW		 4445static void emulator_set_rflags(struct x86_emulate_ctxt *ctxt, ulong val)
4446{
4447 kvm_set_rflags(emul_to_vcpu(ctxt), val);
4448}
4449
717746e3 4450static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4451{
717746e3 4452 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4453}
4454
4bff1e86 4455static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4456{
4bff1e86 4457 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4458}
4459
4bff1e86 4460static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4461{
4bff1e86 4462 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4463}
4464
1ac9d0cf
AK		 4465static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4466{
4467 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4468}
4469
4470static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4471{
4472 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4473}
4474
4bff1e86
AK		 4475static unsigned long emulator_get_cached_segment_base(
4476 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4477{
4bff1e86 4478 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4479}
4480
1aa36616
AK		 4481static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4482 struct desc_struct *desc, u32 *base3,
4483 int seg)
2dafc6c2
GN		 4484{
4485 struct kvm_segment var;
4486
4bff1e86 4487 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4488 *selector = var.selector;
2dafc6c2 4489
378a8b09
GN		 4490 if (var.unusable) {
4491 memset(desc, 0, sizeof(*desc));
2dafc6c2 4492 return false;
378a8b09 4493 }
2dafc6c2
GN		 4494
4495 if (var.g)
4496 var.limit >>= 12;
4497 set_desc_limit(desc, var.limit);
4498 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4499#ifdef CONFIG_X86_64
4500 if (base3)
4501 *base3 = var.base >> 32;
4502#endif
2dafc6c2
GN		 4503 desc->type = var.type;
4504 desc->s = var.s;
4505 desc->dpl = var.dpl;
4506 desc->p = var.present;
4507 desc->avl = var.avl;
4508 desc->l = var.l;
4509 desc->d = var.db;
4510 desc->g = var.g;
4511
4512 return true;
4513}
4514
1aa36616
AK		 4515static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4516 struct desc_struct *desc, u32 base3,
4517 int seg)
2dafc6c2 4518{
4bff1e86 4519 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 4520 struct kvm_segment var;
4521
1aa36616 4522 var.selector = selector;
2dafc6c2 4523 var.base = get_desc_base(desc);
5601d05b
GN		 4524#ifdef CONFIG_X86_64
4525 var.base |= ((u64)base3) << 32;
4526#endif
2dafc6c2
GN		 4527 var.limit = get_desc_limit(desc);
4528 if (desc->g)
4529 var.limit = (var.limit << 12) | 0xfff;
4530 var.type = desc->type;
4531 var.present = desc->p;
4532 var.dpl = desc->dpl;
4533 var.db = desc->d;
4534 var.s = desc->s;
4535 var.l = desc->l;
4536 var.g = desc->g;
4537 var.avl = desc->avl;
4538 var.present = desc->p;
4539 var.unusable = !var.present;
4540 var.padding = 0;
4541
4542 kvm_set_segment(vcpu, &var, seg);
4543 return;
4544}
4545
717746e3
AK		 4546static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4547 u32 msr_index, u64 *pdata)
4548{
4549 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4550}
4551
4552static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4553 u32 msr_index, u64 data)
4554{
8fe8ab46
WA		 4555 struct msr_data msr;
4556
4557 msr.data = data;
4558 msr.index = msr_index;
4559 msr.host_initiated = false;
4560 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 4561}
4562
222d21aa
AK		 4563static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4564 u32 pmc, u64 *pdata)
4565{
4566 return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata);
4567}
4568
6c3287f7
AK		 4569static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4570{
4571 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4572}
4573
5037f6f3
AK		 4574static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4575{
4576 preempt_disable();
5197b808 4577 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 4578 /*
4579 * CR0.TS may reference the host fpu state, not the guest fpu state,
4580 * so it may be clear at this point.
4581 */
4582 clts();
4583}
4584
4585static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4586{
4587 preempt_enable();
4588}
4589
2953538e 4590static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 4591 struct x86_instruction_info *info,
c4f035c6
AK		 4592 enum x86_intercept_stage stage)
4593{
2953538e 4594 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 4595}
4596
0017f93a 4597static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
bdb42f5a
SB		 4598 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4599{
0017f93a 4600 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
bdb42f5a
SB		 4601}
4602
dd856efa
AK		 4603static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
4604{
4605 return kvm_register_read(emul_to_vcpu(ctxt), reg);
4606}
4607
4608static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
4609{
4610 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
4611}
4612
0225fb50 4613static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 4614 .read_gpr = emulator_read_gpr,
4615 .write_gpr = emulator_write_gpr,
1871c602 4616 .read_std = kvm_read_guest_virt_system,
2dafc6c2 4617 .write_std = kvm_write_guest_virt_system,
1871c602 4618 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 4619 .read_emulated = emulator_read_emulated,
4620 .write_emulated = emulator_write_emulated,
4621 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 4622 .invlpg = emulator_invlpg,
cf8f70bf
GN		 4623 .pio_in_emulated = emulator_pio_in_emulated,
4624 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 4625 .get_segment = emulator_get_segment,
4626 .set_segment = emulator_set_segment,
5951c442 4627 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 4628 .get_gdt = emulator_get_gdt,
160ce1f1 4629 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 4630 .set_gdt = emulator_set_gdt,
4631 .set_idt = emulator_set_idt,
52a46617
GN		 4632 .get_cr = emulator_get_cr,
4633 .set_cr = emulator_set_cr,
4cee4798 4634 .set_rflags = emulator_set_rflags,
9c537244 4635 .cpl = emulator_get_cpl,
35aa5375
GN		 4636 .get_dr = emulator_get_dr,
4637 .set_dr = emulator_set_dr,
717746e3
AK		 4638 .set_msr = emulator_set_msr,
4639 .get_msr = emulator_get_msr,
222d21aa 4640 .read_pmc = emulator_read_pmc,
6c3287f7 4641 .halt = emulator_halt,
bcaf5cc5 4642 .wbinvd = emulator_wbinvd,
d6aa1000 4643 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 4644 .get_fpu = emulator_get_fpu,
4645 .put_fpu = emulator_put_fpu,
c4f035c6 4646 .intercept = emulator_intercept,
bdb42f5a 4647 .get_cpuid = emulator_get_cpuid,
bbd9b64e
CO		 4648};
4649
95cb2295
GN		 4650static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4651{
4652 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4653 /*
4654 * an sti; sti; sequence only disable interrupts for the first
4655 * instruction. So, if the last instruction, be it emulated or
4656 * not, left the system with the INT_STI flag enabled, it
4657 * means that the last instruction is an sti. We should not
4658 * leave the flag on in this case. The same goes for mov ss
4659 */
4660 if (!(int_shadow & mask))
4661 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4662}
4663
54b8486f
GN		 4664static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4665{
4666 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 4667 if (ctxt->exception.vector == PF_VECTOR)
6389ee94 4668 kvm_propagate_fault(vcpu, &ctxt->exception);
da9cb575
AK		 4669 else if (ctxt->exception.error_code_valid)
4670 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4671 ctxt->exception.error_code);
54b8486f 4672 else
da9cb575 4673 kvm_queue_exception(vcpu, ctxt->exception.vector);
54b8486f
GN		 4674}
4675
dd856efa 4676static void init_decode_cache(struct x86_emulate_ctxt *ctxt)
b5c9ff73 4677{
9dac77fa 4678 memset(&ctxt->twobyte, 0,
dd856efa 4679 (void *)&ctxt->_regs - (void *)&ctxt->twobyte);
b5c9ff73 4680
9dac77fa
AK		 4681 ctxt->fetch.start = 0;
4682 ctxt->fetch.end = 0;
4683 ctxt->io_read.pos = 0;
4684 ctxt->io_read.end = 0;
4685 ctxt->mem_read.pos = 0;
4686 ctxt->mem_read.end = 0;
b5c9ff73
TY		 4687}
4688
8ec4722d
MG		 4689static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4690{
adf52235 4691 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 4692 int cs_db, cs_l;
4693
8ec4722d
MG		 4694 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4695
adf52235
TY		 4696 ctxt->eflags = kvm_get_rflags(vcpu);
4697 ctxt->eip = kvm_rip_read(vcpu);
4698 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4699 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
4700 cs_l ? X86EMUL_MODE_PROT64 :
4701 cs_db ? X86EMUL_MODE_PROT32 :
4702 X86EMUL_MODE_PROT16;
4703 ctxt->guest_mode = is_guest_mode(vcpu);
4704
dd856efa 4705 init_decode_cache(ctxt);
7ae441ea 4706 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 4707}
4708
71f9833b 4709int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 4710{
9d74191a 4711 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 4712 int ret;
4713
4714 init_emulate_ctxt(vcpu);
4715
9dac77fa
AK		 4716 ctxt->op_bytes = 2;
4717 ctxt->ad_bytes = 2;
4718 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 4719 ret = emulate_int_real(ctxt, irq);
63995653
MG		 4720
4721 if (ret != X86EMUL_CONTINUE)
4722 return EMULATE_FAIL;
4723
9dac77fa 4724 ctxt->eip = ctxt->_eip;
9d74191a
TY		 4725 kvm_rip_write(vcpu, ctxt->eip);
4726 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 4727
4728 if (irq == NMI_VECTOR)
7460fb4a 4729 vcpu->arch.nmi_pending = 0;
63995653
MG		 4730 else
4731 vcpu->arch.interrupt.pending = false;
4732
4733 return EMULATE_DONE;
4734}
4735EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4736
6d77dbfc
GN		 4737static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4738{
fc3a9157
JR		 4739 int r = EMULATE_DONE;
4740
6d77dbfc
GN		 4741 ++vcpu->stat.insn_emulation_fail;
4742 trace_kvm_emulate_insn_failed(vcpu);
fc3a9157
JR		 4743 if (!is_guest_mode(vcpu)) {
4744 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4745 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4746 vcpu->run->internal.ndata = 0;
4747 r = EMULATE_FAIL;
4748 }
6d77dbfc 4749 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 4750
4751 return r;
6d77dbfc
GN		 4752}
4753
93c05d3e
XG		 4754static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
4755 bool write_fault_to_shadow_pgtable)
a6f177ef 4756{
95b3cf69 4757 gpa_t gpa = cr2;
8e3d9d06 4758 pfn_t pfn;
a6f177ef 4759
95b3cf69
XG		 4760 if (!vcpu->arch.mmu.direct_map) {
4761 /*
4762 * Write permission should be allowed since only
4763 * write access need to be emulated.
4764 */
4765 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
22368028 4766
95b3cf69
XG		 4767 /*
4768 * If the mapping is invalid in guest, let cpu retry
4769 * it to generate fault.
4770 */
4771 if (gpa == UNMAPPED_GVA)
4772 return true;
4773 }
a6f177ef 4774
8e3d9d06
XG		 4775 /*
4776 * Do not retry the unhandleable instruction if it faults on the
4777 * readonly host memory, otherwise it will goto a infinite loop:
4778 * retry instruction -> write #PF -> emulation fail -> retry
4779 * instruction -> ...
4780 */
4781 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 4782
4783 /*
4784 * If the instruction failed on the error pfn, it can not be fixed,
4785 * report the error to userspace.
4786 */
4787 if (is_error_noslot_pfn(pfn))
4788 return false;
4789
4790 kvm_release_pfn_clean(pfn);
4791
4792 /* The instructions are well-emulated on direct mmu. */
4793 if (vcpu->arch.mmu.direct_map) {
4794 unsigned int indirect_shadow_pages;
4795
4796 spin_lock(&vcpu->kvm->mmu_lock);
4797 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
4798 spin_unlock(&vcpu->kvm->mmu_lock);
4799
4800 if (indirect_shadow_pages)
4801 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
4802
a6f177ef 4803 return true;
8e3d9d06 4804 }
a6f177ef 4805
95b3cf69
XG		 4806 /*
4807 * if emulation was due to access to shadowed page table
4808 * and it failed try to unshadow page and re-enter the
4809 * guest to let CPU execute the instruction.
4810 */
4811 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 4812
4813 /*
4814 * If the access faults on its page table, it can not
4815 * be fixed by unprotecting shadow page and it should
4816 * be reported to userspace.
4817 */
4818 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 4819}
4820
1cb3f3ae
XG		 4821static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
4822 unsigned long cr2, int emulation_type)
4823{
4824 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4825 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
4826
4827 last_retry_eip = vcpu->arch.last_retry_eip;
4828 last_retry_addr = vcpu->arch.last_retry_addr;
4829
4830 /*
4831 * If the emulation is caused by #PF and it is non-page_table
4832 * writing instruction, it means the VM-EXIT is caused by shadow
4833 * page protected, we can zap the shadow page and retry this
4834 * instruction directly.
4835 *
4836 * Note: if the guest uses a non-page-table modifying instruction
4837 * on the PDE that points to the instruction, then we will unmap
4838 * the instruction and go to an infinite loop. So, we cache the
4839 * last retried eip and the last fault address, if we meet the eip
4840 * and the address again, we can break out of the potential infinite
4841 * loop.
4842 */
4843 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
4844
4845 if (!(emulation_type & EMULTYPE_RETRY))
4846 return false;
4847
4848 if (x86_page_table_writing_insn(ctxt))
4849 return false;
4850
4851 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
4852 return false;
4853
4854 vcpu->arch.last_retry_eip = ctxt->eip;
4855 vcpu->arch.last_retry_addr = cr2;
4856
4857 if (!vcpu->arch.mmu.direct_map)
4858 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
4859
22368028 4860 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 4861
4862 return true;
4863}
4864
716d51ab
GN		 4865static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
4866static int complete_emulated_pio(struct kvm_vcpu *vcpu);
4867
51d8b661
AP		 4868int x86_emulate_instruction(struct kvm_vcpu *vcpu,
4869 unsigned long cr2,
dc25e89e
AP		 4870 int emulation_type,
4871 void *insn,
4872 int insn_len)
bbd9b64e 4873{
95cb2295 4874 int r;
9d74191a 4875 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 4876 bool writeback = true;
93c05d3e 4877 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 4878
93c05d3e
XG		 4879 /*
4880 * Clear write_fault_to_shadow_pgtable here to ensure it is
4881 * never reused.
4882 */
4883 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 4884 kvm_clear_exception_queue(vcpu);
8d7d8102 4885
571008da 4886 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 4887 init_emulate_ctxt(vcpu);
9d74191a
TY		 4888 ctxt->interruptibility = 0;
4889 ctxt->have_exception = false;
4890 ctxt->perm_ok = false;
bbd9b64e 4891
9d74191a 4892 ctxt->only_vendor_specific_insn
4005996e
AK		 4893 = emulation_type & EMULTYPE_TRAP_UD;
4894
9d74191a 4895 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 4896
e46479f8 4897 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 4898 ++vcpu->stat.insn_emulation;
1d2887e2 4899 if (r != EMULATION_OK) {
4005996e
AK		 4900 if (emulation_type & EMULTYPE_TRAP_UD)
4901 return EMULATE_FAIL;
93c05d3e
XG		 4902 if (reexecute_instruction(vcpu, cr2,
4903 write_fault_to_spt))
bbd9b64e 4904 return EMULATE_DONE;
6d77dbfc
GN		 4905 if (emulation_type & EMULTYPE_SKIP)
4906 return EMULATE_FAIL;
4907 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4908 }
4909 }
4910
ba8afb6b 4911 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 4912 kvm_rip_write(vcpu, ctxt->_eip);
ba8afb6b
GN		 4913 return EMULATE_DONE;
4914 }
4915
1cb3f3ae
XG		 4916 if (retry_instruction(ctxt, cr2, emulation_type))
4917 return EMULATE_DONE;
4918
7ae441ea 4919 /* this is needed for vmware backdoor interface to work since it
4d2179e1 4920 changes registers values during IO operation */
7ae441ea
GN		 4921 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
4922 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 4923 emulator_invalidate_register_cache(ctxt);
7ae441ea 4924 }
4d2179e1 4925
5cd21917 4926restart:
9d74191a 4927 r = x86_emulate_insn(ctxt);
bbd9b64e 4928
775fde86
JR		 4929 if (r == EMULATION_INTERCEPTED)
4930 return EMULATE_DONE;
4931
d2ddd1c4 4932 if (r == EMULATION_FAILED) {
93c05d3e 4933 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt))
c3cd7ffa
GN		 4934 return EMULATE_DONE;
4935
6d77dbfc 4936 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4937 }
4938
9d74191a 4939 if (ctxt->have_exception) {
54b8486f 4940 inject_emulated_exception(vcpu);
d2ddd1c4
GN		 4941 r = EMULATE_DONE;
4942 } else if (vcpu->arch.pio.count) {
3457e419
GN		 4943 if (!vcpu->arch.pio.in)
4944 vcpu->arch.pio.count = 0;
716d51ab 4945 else {
7ae441ea 4946 writeback = false;
716d51ab
GN		 4947 vcpu->arch.complete_userspace_io = complete_emulated_pio;
4948 }
e85d28f8 4949 r = EMULATE_DO_MMIO;
7ae441ea
GN		 4950 } else if (vcpu->mmio_needed) {
4951 if (!vcpu->mmio_is_write)
4952 writeback = false;
e85d28f8 4953 r = EMULATE_DO_MMIO;
716d51ab 4954 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 4955 } else if (r == EMULATION_RESTART)
5cd21917 4956 goto restart;
d2ddd1c4
GN		 4957 else
4958 r = EMULATE_DONE;
f850e2e6 4959
7ae441ea 4960 if (writeback) {
9d74191a
TY		 4961 toggle_interruptibility(vcpu, ctxt->interruptibility);
4962 kvm_set_rflags(vcpu, ctxt->eflags);
7ae441ea 4963 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea 4964 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 4965 kvm_rip_write(vcpu, ctxt->eip);
7ae441ea
GN		 4966 } else
4967 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 4968
4969 return r;
de7d789a 4970}
51d8b661 4971EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 4972
cf8f70bf 4973int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 4974{
cf8f70bf 4975 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 4976 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
4977 size, port, &val, 1);
cf8f70bf 4978 /* do not return to emulator after return from userspace */
7972995b 4979 vcpu->arch.pio.count = 0;
de7d789a
CO		 4980 return ret;
4981}
cf8f70bf 4982EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 4983
8cfdc000
ZA		 4984static void tsc_bad(void *info)
4985{
0a3aee0d 4986 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 4987}
4988
4989static void tsc_khz_changed(void *data)
c8076604 4990{
8cfdc000
ZA		 4991 struct cpufreq_freqs *freq = data;
4992 unsigned long khz = 0;
4993
4994 if (data)
4995 khz = freq->new;
4996 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4997 khz = cpufreq_quick_get(raw_smp_processor_id());
4998 if (!khz)
4999 khz = tsc_khz;
0a3aee0d 5000 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5001}
5002
c8076604
GH		 5003static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5004 void *data)
5005{
5006 struct cpufreq_freqs *freq = data;
5007 struct kvm *kvm;
5008 struct kvm_vcpu *vcpu;
5009 int i, send_ipi = 0;
5010
8cfdc000
ZA		 5011 /*
5012 * We allow guests to temporarily run on slowing clocks,
5013 * provided we notify them after, or to run on accelerating
5014 * clocks, provided we notify them before. Thus time never
5015 * goes backwards.
5016 *
5017 * However, we have a problem. We can't atomically update
5018 * the frequency of a given CPU from this function; it is
5019 * merely a notifier, which can be called from any CPU.
5020 * Changing the TSC frequency at arbitrary points in time
5021 * requires a recomputation of local variables related to
5022 * the TSC for each VCPU. We must flag these local variables
5023 * to be updated and be sure the update takes place with the
5024 * new frequency before any guests proceed.
5025 *
5026 * Unfortunately, the combination of hotplug CPU and frequency
5027 * change creates an intractable locking scenario; the order
5028 * of when these callouts happen is undefined with respect to
5029 * CPU hotplug, and they can race with each other. As such,
5030 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5031 * undefined; you can actually have a CPU frequency change take
5032 * place in between the computation of X and the setting of the
5033 * variable. To protect against this problem, all updates of
5034 * the per_cpu tsc_khz variable are done in an interrupt
5035 * protected IPI, and all callers wishing to update the value
5036 * must wait for a synchronous IPI to complete (which is trivial
5037 * if the caller is on the CPU already). This establishes the
5038 * necessary total order on variable updates.
5039 *
5040 * Note that because a guest time update may take place
5041 * anytime after the setting of the VCPU's request bit, the
5042 * correct TSC value must be set before the request. However,
5043 * to ensure the update actually makes it to any guest which
5044 * starts running in hardware virtualization between the set
5045 * and the acquisition of the spinlock, we must also ping the
5046 * CPU after setting the request bit.
5047 *
5048 */
5049
c8076604
GH		 5050 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5051 return 0;
5052 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5053 return 0;
8cfdc000
ZA		 5054
5055 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5056
e935b837 5057 raw_spin_lock(&kvm_lock);
c8076604 5058 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5059 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5060 if (vcpu->cpu != freq->cpu)
5061 continue;
c285545f 5062 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5063 if (vcpu->cpu != smp_processor_id())
8cfdc000 5064 send_ipi = 1;
c8076604
GH		 5065 }
5066 }
e935b837 5067 raw_spin_unlock(&kvm_lock);
c8076604
GH		 5068
5069 if (freq->old < freq->new && send_ipi) {
5070 /*
5071 * We upscale the frequency. Must make the guest
5072 * doesn't see old kvmclock values while running with
5073 * the new frequency, otherwise we risk the guest sees
5074 * time go backwards.
5075 *
5076 * In case we update the frequency for another cpu
5077 * (which might be in guest context) send an interrupt
5078 * to kick the cpu out of guest context. Next time
5079 * guest context is entered kvmclock will be updated,
5080 * so the guest will not see stale values.
5081 */
8cfdc000 5082 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5083 }
5084 return 0;
5085}
5086
5087static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5088 .notifier_call = kvmclock_cpufreq_notifier
5089};
5090
5091static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5092 unsigned long action, void *hcpu)
5093{
5094 unsigned int cpu = (unsigned long)hcpu;
5095
5096 switch (action) {
5097 case CPU_ONLINE:
5098 case CPU_DOWN_FAILED:
5099 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5100 break;
5101 case CPU_DOWN_PREPARE:
5102 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5103 break;
5104 }
5105 return NOTIFY_OK;
5106}
5107
5108static struct notifier_block kvmclock_cpu_notifier_block = {
5109 .notifier_call = kvmclock_cpu_notifier,
5110 .priority = -INT_MAX
c8076604
GH		 5111};
5112
b820cc0c
ZA		 5113static void kvm_timer_init(void)
5114{
5115 int cpu;
5116
c285545f 5117 max_tsc_khz = tsc_khz;
8cfdc000 5118 register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
b820cc0c 5119 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5120#ifdef CONFIG_CPU_FREQ
5121 struct cpufreq_policy policy;
5122 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5123 cpu = get_cpu();
5124 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5125 if (policy.cpuinfo.max_freq)
5126 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5127 put_cpu();
c285545f 5128#endif
b820cc0c
ZA		 5129 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5130 CPUFREQ_TRANSITION_NOTIFIER);
5131 }
c285545f 5132 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 5133 for_each_online_cpu(cpu)
5134 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
b820cc0c
ZA		 5135}
5136
ff9d07a0
ZY		 5137static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5138
f5132b01 5139int kvm_is_in_guest(void)
ff9d07a0 5140{
086c9855 5141 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 5142}
5143
5144static int kvm_is_user_mode(void)
5145{
5146 int user_mode = 3;
dcf46b94 5147
086c9855
AS		 5148 if (__this_cpu_read(current_vcpu))
5149 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 5150
ff9d07a0
ZY		 5151 return user_mode != 0;
5152}
5153
5154static unsigned long kvm_get_guest_ip(void)
5155{
5156 unsigned long ip = 0;
dcf46b94 5157
086c9855
AS		 5158 if (__this_cpu_read(current_vcpu))
5159 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 5160
ff9d07a0
ZY		 5161 return ip;
5162}
5163
5164static struct perf_guest_info_callbacks kvm_guest_cbs = {
5165 .is_in_guest = kvm_is_in_guest,
5166 .is_user_mode = kvm_is_user_mode,
5167 .get_guest_ip = kvm_get_guest_ip,
5168};
5169
5170void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5171{
086c9855 5172 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 5173}
5174EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5175
5176void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5177{
086c9855 5178 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 5179}
5180EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5181
ce88decf
XG		 5182static void kvm_set_mmio_spte_mask(void)
5183{
5184 u64 mask;
5185 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5186
5187 /*
5188 * Set the reserved bits and the present bit of an paging-structure
5189 * entry to generate page fault with PFER.RSV = 1.
5190 */
5191 mask = ((1ull << (62 - maxphyaddr + 1)) - 1) << maxphyaddr;
5192 mask |= 1ull;
5193
5194#ifdef CONFIG_X86_64
5195 /*
5196 * If reserved bit is not supported, clear the present bit to disable
5197 * mmio page fault.
5198 */
5199 if (maxphyaddr == 52)
5200 mask &= ~1ull;
5201#endif
5202
5203 kvm_mmu_set_mmio_spte_mask(mask);
5204}
5205
16e8d74d
MT		 5206#ifdef CONFIG_X86_64
5207static void pvclock_gtod_update_fn(struct work_struct *work)
5208{
d828199e
MT		 5209 struct kvm *kvm;
5210
5211 struct kvm_vcpu *vcpu;
5212 int i;
5213
5214 raw_spin_lock(&kvm_lock);
5215 list_for_each_entry(kvm, &vm_list, vm_list)
5216 kvm_for_each_vcpu(i, vcpu, kvm)
5217 set_bit(KVM_REQ_MASTERCLOCK_UPDATE, &vcpu->requests);
5218 atomic_set(&kvm_guest_has_master_clock, 0);
5219 raw_spin_unlock(&kvm_lock);
16e8d74d
MT		 5220}
5221
5222static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5223
5224/*
5225 * Notification about pvclock gtod data update.
5226 */
5227static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5228 void *priv)
5229{
5230 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5231 struct timekeeper *tk = priv;
5232
5233 update_pvclock_gtod(tk);
5234
5235 /* disable master clock if host does not trust, or does not
5236 * use, TSC clocksource
5237 */
5238 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5239 atomic_read(&kvm_guest_has_master_clock) != 0)
5240 queue_work(system_long_wq, &pvclock_gtod_work);
5241
5242 return 0;
5243}
5244
5245static struct notifier_block pvclock_gtod_notifier = {
5246 .notifier_call = pvclock_gtod_notify,
5247};
5248#endif
5249
f8c16bba 5250int kvm_arch_init(void *opaque)
043405e1 5251{
b820cc0c 5252 int r;
f8c16bba
ZX		 5253 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
5254
f8c16bba
ZX		 5255 if (kvm_x86_ops) {
5256 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 5257 r = -EEXIST;
5258 goto out;
f8c16bba
ZX		 5259 }
5260
5261 if (!ops->cpu_has_kvm_support()) {
5262 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 5263 r = -EOPNOTSUPP;
5264 goto out;
f8c16bba
ZX		 5265 }
5266 if (ops->disabled_by_bios()) {
5267 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 5268 r = -EOPNOTSUPP;
5269 goto out;
f8c16bba
ZX		 5270 }
5271
97db56ce
AK		 5272 r = kvm_mmu_module_init();
5273 if (r)
5274 goto out;
5275
ce88decf 5276 kvm_set_mmio_spte_mask();
97db56ce
AK		 5277 kvm_init_msr_list();
5278
f8c16bba 5279 kvm_x86_ops = ops;
7b52345e 5280 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 5281 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 5282
b820cc0c 5283 kvm_timer_init();
c8076604 5284
ff9d07a0
ZY		 5285 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5286
2acf923e
DC		 5287 if (cpu_has_xsave)
5288 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5289
c5cc421b 5290 kvm_lapic_init();
16e8d74d
MT		 5291#ifdef CONFIG_X86_64
5292 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5293#endif
5294
f8c16bba 5295 return 0;
56c6d28a
ZX		 5296
5297out:
56c6d28a 5298 return r;
043405e1 5299}
8776e519 5300
f8c16bba
ZX		 5301void kvm_arch_exit(void)
5302{
ff9d07a0
ZY		 5303 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5304
888d256e
JK		 5305 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5306 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5307 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 5308 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
16e8d74d
MT		 5309#ifdef CONFIG_X86_64
5310 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5311#endif
f8c16bba 5312 kvm_x86_ops = NULL;
56c6d28a
ZX		 5313 kvm_mmu_module_exit();
5314}
f8c16bba 5315
8776e519
HB		 5316int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5317{
5318 ++vcpu->stat.halt_exits;
5319 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 5320 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 5321 return 1;
5322 } else {
5323 vcpu->run->exit_reason = KVM_EXIT_HLT;
5324 return 0;
5325 }
5326}
5327EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5328
55cd8e5a
GN		 5329int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
5330{
5331 u64 param, ingpa, outgpa, ret;
5332 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
5333 bool fast, longmode;
5334 int cs_db, cs_l;
5335
5336 /*
5337 * hypercall generates UD from non zero cpl and real mode
5338 * per HYPER-V spec
5339 */
3eeb3288 5340 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 5341 kvm_queue_exception(vcpu, UD_VECTOR);
5342 return 0;
5343 }
5344
5345 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5346 longmode = is_long_mode(vcpu) && cs_l == 1;
5347
5348 if (!longmode) {
ccd46936
GN		 5349 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
5350 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
5351 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
5352 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
5353 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
5354 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 5355 }
5356#ifdef CONFIG_X86_64
5357 else {
5358 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
5359 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
5360 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
5361 }
5362#endif
5363
5364 code = param & 0xffff;
5365 fast = (param >> 16) & 0x1;
5366 rep_cnt = (param >> 32) & 0xfff;
5367 rep_idx = (param >> 48) & 0xfff;
5368
5369 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
5370
c25bc163
GN		 5371 switch (code) {
5372 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
5373 kvm_vcpu_on_spin(vcpu);
5374 break;
5375 default:
5376 res = HV_STATUS_INVALID_HYPERCALL_CODE;
5377 break;
5378 }
55cd8e5a
GN		 5379
5380 ret = res | (((u64)rep_done & 0xfff) << 32);
5381 if (longmode) {
5382 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5383 } else {
5384 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
5385 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
5386 }
5387
5388 return 1;
5389}
5390
8776e519
HB		 5391int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5392{
5393 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 5394 int r = 1;
8776e519 5395
55cd8e5a
GN		 5396 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5397 return kvm_hv_hypercall(vcpu);
5398
5fdbf976
MT		 5399 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5400 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5401 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5402 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5403 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 5404
229456fc 5405 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 5406
8776e519
HB		 5407 if (!is_long_mode(vcpu)) {
5408 nr &= 0xFFFFFFFF;
5409 a0 &= 0xFFFFFFFF;
5410 a1 &= 0xFFFFFFFF;
5411 a2 &= 0xFFFFFFFF;
5412 a3 &= 0xFFFFFFFF;
5413 }
5414
07708c4a
JK		 5415 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5416 ret = -KVM_EPERM;
5417 goto out;
5418 }
5419
8776e519 5420 switch (nr) {
b93463aa
AK		 5421 case KVM_HC_VAPIC_POLL_IRQ:
5422 ret = 0;
5423 break;
8776e519
HB		 5424 default:
5425 ret = -KVM_ENOSYS;
5426 break;
5427 }
07708c4a 5428out:
5fdbf976 5429 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 5430 ++vcpu->stat.hypercalls;
2f333bcb 5431 return r;
8776e519
HB		 5432}
5433EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5434
b6785def 5435static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 5436{
d6aa1000 5437 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 5438 char instruction[3];
5fdbf976 5439 unsigned long rip = kvm_rip_read(vcpu);
8776e519 5440
8776e519
HB		 5441 /*
5442 * Blow out the MMU to ensure that no other VCPU has an active mapping
5443 * to ensure that the updated hypercall appears atomically across all
5444 * VCPUs.
5445 */
5446 kvm_mmu_zap_all(vcpu->kvm);
5447
8776e519 5448 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 5449
9d74191a 5450 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 5451}
5452
b6c7a5dc
HB		 5453/*
5454 * Check if userspace requested an interrupt window, and that the
5455 * interrupt window is open.
5456 *
5457 * No need to exit to userspace if we already have an interrupt queued.
5458 */
851ba692 5459static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 5460{
8061823a 5461 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 5462 vcpu->run->request_interrupt_window &&
5df56646 5463 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 5464}
5465
851ba692 5466static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 5467{
851ba692
AK		 5468 struct kvm_run *kvm_run = vcpu->run;
5469
91586a3b 5470 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 5471 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 5472 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 5473 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 5474 kvm_run->ready_for_interrupt_injection = 1;
4531220b 5475 else
b6c7a5dc 5476 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 5477 kvm_arch_interrupt_allowed(vcpu) &&
5478 !kvm_cpu_has_interrupt(vcpu) &&
5479 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 5480}
5481
4484141a 5482static int vapic_enter(struct kvm_vcpu *vcpu)
b93463aa
AK		 5483{
5484 struct kvm_lapic *apic = vcpu->arch.apic;
5485 struct page *page;
5486
5487 if (!apic || !apic->vapic_addr)
4484141a 5488 return 0;
b93463aa
AK		 5489
5490 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
4484141a
XG		 5491 if (is_error_page(page))
5492 return -EFAULT;
72dc67a6
IE		 5493
5494 vcpu->arch.apic->vapic_page = page;
4484141a 5495 return 0;
b93463aa
AK		 5496}
5497
5498static void vapic_exit(struct kvm_vcpu *vcpu)
5499{
5500 struct kvm_lapic *apic = vcpu->arch.apic;
f656ce01 5501 int idx;
b93463aa
AK		 5502
5503 if (!apic || !apic->vapic_addr)
5504 return;
5505
f656ce01 5506 idx = srcu_read_lock(&vcpu->kvm->srcu);
b93463aa
AK		 5507 kvm_release_page_dirty(apic->vapic_page);
5508 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f656ce01 5509 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 5510}
5511
95ba8273
GN		 5512static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5513{
5514 int max_irr, tpr;
5515
5516 if (!kvm_x86_ops->update_cr8_intercept)
5517 return;
5518
88c808fd
AK		 5519 if (!vcpu->arch.apic)
5520 return;
5521
8db3baa2
GN		 5522 if (!vcpu->arch.apic->vapic_addr)
5523 max_irr = kvm_lapic_find_highest_irr(vcpu);
5524 else
5525 max_irr = -1;
95ba8273
GN		 5526
5527 if (max_irr != -1)
5528 max_irr >>= 4;
5529
5530 tpr = kvm_lapic_get_cr8(vcpu);
5531
5532 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5533}
5534
851ba692 5535static void inject_pending_event(struct kvm_vcpu *vcpu)
95ba8273
GN		 5536{
5537 /* try to reinject previous events if any */
b59bb7bd 5538 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 5539 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5540 vcpu->arch.exception.has_error_code,
5541 vcpu->arch.exception.error_code);
b59bb7bd
GN		 5542 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5543 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 5544 vcpu->arch.exception.error_code,
5545 vcpu->arch.exception.reinject);
b59bb7bd
GN		 5546 return;
5547 }
5548
95ba8273
GN		 5549 if (vcpu->arch.nmi_injected) {
5550 kvm_x86_ops->set_nmi(vcpu);
5551 return;
5552 }
5553
5554 if (vcpu->arch.interrupt.pending) {
66fd3f7f 5555 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5556 return;
5557 }
5558
5559 /* try to inject new event if pending */
5560 if (vcpu->arch.nmi_pending) {
5561 if (kvm_x86_ops->nmi_allowed(vcpu)) {
7460fb4a 5562 --vcpu->arch.nmi_pending;
95ba8273
GN		 5563 vcpu->arch.nmi_injected = true;
5564 kvm_x86_ops->set_nmi(vcpu);
5565 }
c7c9c56c 5566 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
95ba8273 5567 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 5568 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5569 false);
5570 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5571 }
5572 }
5573}
5574
2acf923e
DC		 5575static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
5576{
5577 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
5578 !vcpu->guest_xcr0_loaded) {
5579 /* kvm_set_xcr() also depends on this */
5580 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
5581 vcpu->guest_xcr0_loaded = 1;
5582 }
5583}
5584
5585static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
5586{
5587 if (vcpu->guest_xcr0_loaded) {
5588 if (vcpu->arch.xcr0 != host_xcr0)
5589 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
5590 vcpu->guest_xcr0_loaded = 0;
5591 }
5592}
5593
7460fb4a
AK		 5594static void process_nmi(struct kvm_vcpu *vcpu)
5595{
5596 unsigned limit = 2;
5597
5598 /*
5599 * x86 is limited to one NMI running, and one NMI pending after it.
5600 * If an NMI is already in progress, limit further NMIs to just one.
5601 * Otherwise, allow two (and we'll inject the first one immediately).
5602 */
5603 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
5604 limit = 1;
5605
5606 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
5607 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
5608 kvm_make_request(KVM_REQ_EVENT, vcpu);
5609}
5610
d828199e
MT		 5611static void kvm_gen_update_masterclock(struct kvm *kvm)
5612{
5613#ifdef CONFIG_X86_64
5614 int i;
5615 struct kvm_vcpu *vcpu;
5616 struct kvm_arch *ka = &kvm->arch;
5617
5618 spin_lock(&ka->pvclock_gtod_sync_lock);
5619 kvm_make_mclock_inprogress_request(kvm);
5620 /* no guest entries from this point */
5621 pvclock_update_vm_gtod_copy(kvm);
5622
5623 kvm_for_each_vcpu(i, vcpu, kvm)
5624 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
5625
5626 /* guest entries allowed */
5627 kvm_for_each_vcpu(i, vcpu, kvm)
5628 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
5629
5630 spin_unlock(&ka->pvclock_gtod_sync_lock);
5631#endif
5632}
5633
c7c9c56c
YZ		 5634static void update_eoi_exitmap(struct kvm_vcpu *vcpu)
5635{
5636 u64 eoi_exit_bitmap[4];
5637
5638 memset(eoi_exit_bitmap, 0, 32);
5639
5640 kvm_ioapic_calculate_eoi_exitmap(vcpu, eoi_exit_bitmap);
5641 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
5642}
5643
851ba692 5644static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 5645{
5646 int r;
6a8b1d13 5647 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 5648 vcpu->run->request_interrupt_window;
d6185f20 5649 bool req_immediate_exit = 0;
b6c7a5dc 5650
3e007509 5651 if (vcpu->requests) {
a8eeb04a 5652 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 5653 kvm_mmu_unload(vcpu);
a8eeb04a 5654 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 5655 __kvm_migrate_timers(vcpu);
d828199e
MT		 5656 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
5657 kvm_gen_update_masterclock(vcpu->kvm);
34c238a1
ZA		 5658 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
5659 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 5660 if (unlikely(r))
5661 goto out;
5662 }
a8eeb04a 5663 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 5664 kvm_mmu_sync_roots(vcpu);
a8eeb04a 5665 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
d4acf7e7 5666 kvm_x86_ops->tlb_flush(vcpu);
a8eeb04a 5667 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 5668 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 5669 r = 0;
5670 goto out;
5671 }
a8eeb04a 5672 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 5673 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 5674 r = 0;
5675 goto out;
5676 }
a8eeb04a 5677 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 5678 vcpu->fpu_active = 0;
5679 kvm_x86_ops->fpu_deactivate(vcpu);
5680 }
af585b92
GN		 5681 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
5682 /* Page is swapped out. Do synthetic halt */
5683 vcpu->arch.apf.halted = true;
5684 r = 1;
5685 goto out;
5686 }
c9aaa895
GC		 5687 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
5688 record_steal_time(vcpu);
7460fb4a
AK		 5689 if (kvm_check_request(KVM_REQ_NMI, vcpu))
5690 process_nmi(vcpu);
d6185f20
NHE		 5691 req_immediate_exit =
5692 kvm_check_request(KVM_REQ_IMMEDIATE_EXIT, vcpu);
f5132b01
GN		 5693 if (kvm_check_request(KVM_REQ_PMU, vcpu))
5694 kvm_handle_pmu_event(vcpu);
5695 if (kvm_check_request(KVM_REQ_PMI, vcpu))
5696 kvm_deliver_pmi(vcpu);
c7c9c56c
YZ		 5697 if (kvm_check_request(KVM_REQ_EOIBITMAP, vcpu))
5698 update_eoi_exitmap(vcpu);
2f52d58c 5699 }
b93463aa 5700
b463a6f7
AK		 5701 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
5702 inject_pending_event(vcpu);
5703
5704 /* enable NMI/IRQ window open exits if needed */
7460fb4a 5705 if (vcpu->arch.nmi_pending)
b463a6f7 5706 kvm_x86_ops->enable_nmi_window(vcpu);
c7c9c56c 5707 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
b463a6f7
AK		 5708 kvm_x86_ops->enable_irq_window(vcpu);
5709
5710 if (kvm_lapic_enabled(vcpu)) {
c7c9c56c
YZ		 5711 /*
5712 * Update architecture specific hints for APIC
5713 * virtual interrupt delivery.
5714 */
5715 if (kvm_x86_ops->hwapic_irr_update)
5716 kvm_x86_ops->hwapic_irr_update(vcpu,
5717 kvm_lapic_find_highest_irr(vcpu));
b463a6f7
AK		 5718 update_cr8_intercept(vcpu);
5719 kvm_lapic_sync_to_vapic(vcpu);
5720 }
5721 }
5722
d8368af8
AK		 5723 r = kvm_mmu_reload(vcpu);
5724 if (unlikely(r)) {
d905c069 5725 goto cancel_injection;
d8368af8
AK		 5726 }
5727
b6c7a5dc
HB		 5728 preempt_disable();
5729
5730 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 5731 if (vcpu->fpu_active)
5732 kvm_load_guest_fpu(vcpu);
2acf923e 5733 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 5734
6b7e2d09
XG		 5735 vcpu->mode = IN_GUEST_MODE;
5736
5737 /* We should set ->mode before check ->requests,
5738 * see the comment in make_all_cpus_request.
5739 */
5740 smp_mb();
b6c7a5dc 5741
d94e1dc9 5742 local_irq_disable();
32f88400 5743
6b7e2d09 5744 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 5745 || need_resched() || signal_pending(current)) {
6b7e2d09 5746 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 5747 smp_wmb();
6c142801
AK		 5748 local_irq_enable();
5749 preempt_enable();
5750 r = 1;
d905c069 5751 goto cancel_injection;
6c142801
AK		 5752 }
5753
f656ce01 5754 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
3200f405 5755
d6185f20
NHE		 5756 if (req_immediate_exit)
5757 smp_send_reschedule(vcpu->cpu);
5758
b6c7a5dc
HB		 5759 kvm_guest_enter();
5760
42dbaa5a 5761 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 5762 set_debugreg(0, 7);
5763 set_debugreg(vcpu->arch.eff_db[0], 0);
5764 set_debugreg(vcpu->arch.eff_db[1], 1);
5765 set_debugreg(vcpu->arch.eff_db[2], 2);
5766 set_debugreg(vcpu->arch.eff_db[3], 3);
5767 }
b6c7a5dc 5768
229456fc 5769 trace_kvm_entry(vcpu->vcpu_id);
851ba692 5770 kvm_x86_ops->run(vcpu);
b6c7a5dc 5771
24f1e32c
FW		 5772 /*
5773 * If the guest has used debug registers, at least dr7
5774 * will be disabled while returning to the host.
5775 * If we don't have active breakpoints in the host, we don't
5776 * care about the messed up debug address registers. But if
5777 * we have some of them active, restore the old state.
5778 */
59d8eb53 5779 if (hw_breakpoint_active())
24f1e32c 5780 hw_breakpoint_restore();
42dbaa5a 5781
886b470c
MT		 5782 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu,
5783 native_read_tsc());
1d5f066e 5784
6b7e2d09 5785 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 5786 smp_wmb();
b6c7a5dc
HB		 5787 local_irq_enable();
5788
5789 ++vcpu->stat.exits;
5790
5791 /*
5792 * We must have an instruction between local_irq_enable() and
5793 * kvm_guest_exit(), so the timer interrupt isn't delayed by
5794 * the interrupt shadow. The stat.exits increment will do nicely.
5795 * But we need to prevent reordering, hence this barrier():
5796 */
5797 barrier();
5798
5799 kvm_guest_exit();
5800
5801 preempt_enable();
5802
f656ce01 5803 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 5804
b6c7a5dc
HB		 5805 /*
5806 * Profile KVM exit RIPs:
5807 */
5808 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 5809 unsigned long rip = kvm_rip_read(vcpu);
5810 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 5811 }
5812
cc578287
ZA		 5813 if (unlikely(vcpu->arch.tsc_always_catchup))
5814 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 5815
5cfb1d5a
MT		 5816 if (vcpu->arch.apic_attention)
5817 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 5818
851ba692 5819 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 5820 return r;
5821
5822cancel_injection:
5823 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 5824 if (unlikely(vcpu->arch.apic_attention))
5825 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 5826out:
5827 return r;
5828}
b6c7a5dc 5829
09cec754 5830
851ba692 5831static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 5832{
5833 int r;
f656ce01 5834 struct kvm *kvm = vcpu->kvm;
d7690175
MT		 5835
5836 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 5837 pr_debug("vcpu %d received sipi with vector # %x\n",
5838 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 5839 kvm_lapic_reset(vcpu);
8b6e4547 5840 r = kvm_vcpu_reset(vcpu);
d7690175
MT		 5841 if (r)
5842 return r;
5843 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 5844 }
5845
f656ce01 5846 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
4484141a
XG		 5847 r = vapic_enter(vcpu);
5848 if (r) {
5849 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
5850 return r;
5851 }
d7690175
MT		 5852
5853 r = 1;
5854 while (r > 0) {
af585b92
GN		 5855 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
5856 !vcpu->arch.apf.halted)
851ba692 5857 r = vcpu_enter_guest(vcpu);
d7690175 5858 else {
f656ce01 5859 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 5860 kvm_vcpu_block(vcpu);
f656ce01 5861 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
a8eeb04a 5862 if (kvm_check_request(KVM_REQ_UNHALT, vcpu))
09cec754
GN		 5863 {
5864 switch(vcpu->arch.mp_state) {
5865 case KVM_MP_STATE_HALTED:
d7690175 5866 vcpu->arch.mp_state =
09cec754
GN		 5867 KVM_MP_STATE_RUNNABLE;
5868 case KVM_MP_STATE_RUNNABLE:
af585b92 5869 vcpu->arch.apf.halted = false;
09cec754
GN		 5870 break;
5871 case KVM_MP_STATE_SIPI_RECEIVED:
5872 default:
5873 r = -EINTR;
5874 break;
5875 }
5876 }
d7690175
MT		 5877 }
5878
09cec754
GN		 5879 if (r <= 0)
5880 break;
5881
5882 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
5883 if (kvm_cpu_has_pending_timer(vcpu))
5884 kvm_inject_pending_timer_irqs(vcpu);
5885
851ba692 5886 if (dm_request_for_irq_injection(vcpu)) {
09cec754 5887 r = -EINTR;
851ba692 5888 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5889 ++vcpu->stat.request_irq_exits;
5890 }
af585b92
GN		 5891
5892 kvm_check_async_pf_completion(vcpu);
5893
09cec754
GN		 5894 if (signal_pending(current)) {
5895 r = -EINTR;
851ba692 5896 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5897 ++vcpu->stat.signal_exits;
5898 }
5899 if (need_resched()) {
f656ce01 5900 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
09cec754 5901 kvm_resched(vcpu);
f656ce01 5902 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 5903 }
b6c7a5dc
HB		 5904 }
5905
f656ce01 5906 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc 5907
b93463aa
AK		 5908 vapic_exit(vcpu);
5909
b6c7a5dc
HB		 5910 return r;
5911}
5912
716d51ab
GN		 5913static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
5914{
5915 int r;
5916 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5917 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
5918 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
5919 if (r != EMULATE_DONE)
5920 return 0;
5921 return 1;
5922}
5923
5924static int complete_emulated_pio(struct kvm_vcpu *vcpu)
5925{
5926 BUG_ON(!vcpu->arch.pio.count);
5927
5928 return complete_emulated_io(vcpu);
5929}
5930
f78146b0
AK		 5931/*
5932 * Implements the following, as a state machine:
5933 *
5934 * read:
5935 * for each fragment
87da7e66
XG		 5936 * for each mmio piece in the fragment
5937 * write gpa, len
5938 * exit
5939 * copy data
f78146b0
AK		 5940 * execute insn
5941 *
5942 * write:
5943 * for each fragment
87da7e66
XG		 5944 * for each mmio piece in the fragment
5945 * write gpa, len
5946 * copy data
5947 * exit
f78146b0 5948 */
716d51ab 5949static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 5950{
5951 struct kvm_run *run = vcpu->run;
f78146b0 5952 struct kvm_mmio_fragment *frag;
87da7e66 5953 unsigned len;
5287f194 5954
716d51ab 5955 BUG_ON(!vcpu->mmio_needed);
5287f194 5956
716d51ab 5957 /* Complete previous fragment */
87da7e66
XG		 5958 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
5959 len = min(8u, frag->len);
716d51ab 5960 if (!vcpu->mmio_is_write)
87da7e66
XG		 5961 memcpy(frag->data, run->mmio.data, len);
5962
5963 if (frag->len <= 8) {
5964 /* Switch to the next fragment. */
5965 frag++;
5966 vcpu->mmio_cur_fragment++;
5967 } else {
5968 /* Go forward to the next mmio piece. */
5969 frag->data += len;
5970 frag->gpa += len;
5971 frag->len -= len;
5972 }
5973
716d51ab
GN		 5974 if (vcpu->mmio_cur_fragment == vcpu->mmio_nr_fragments) {
5975 vcpu->mmio_needed = 0;
cef4dea0 5976 if (vcpu->mmio_is_write)
716d51ab
GN		 5977 return 1;
5978 vcpu->mmio_read_completed = 1;
5979 return complete_emulated_io(vcpu);
5980 }
87da7e66 5981
716d51ab
GN		 5982 run->exit_reason = KVM_EXIT_MMIO;
5983 run->mmio.phys_addr = frag->gpa;
5984 if (vcpu->mmio_is_write)
87da7e66
XG		 5985 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
5986 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 5987 run->mmio.is_write = vcpu->mmio_is_write;
5988 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
5989 return 0;
5287f194
AK		 5990}
5991
716d51ab 5992
b6c7a5dc
HB		 5993int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
5994{
5995 int r;
5996 sigset_t sigsaved;
5997
e5c30142
AK		 5998 if (!tsk_used_math(current) && init_fpu(current))
5999 return -ENOMEM;
6000
ac9f6dc0
AK		 6001 if (vcpu->sigset_active)
6002 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6003
a4535290 6004 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 6005 kvm_vcpu_block(vcpu);
d7690175 6006 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 6007 r = -EAGAIN;
6008 goto out;
b6c7a5dc
HB		 6009 }
6010
b6c7a5dc 6011 /* re-sync apic's tpr */
eea1cff9
AP		 6012 if (!irqchip_in_kernel(vcpu->kvm)) {
6013 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6014 r = -EINVAL;
6015 goto out;
6016 }
6017 }
b6c7a5dc 6018
716d51ab
GN		 6019 if (unlikely(vcpu->arch.complete_userspace_io)) {
6020 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6021 vcpu->arch.complete_userspace_io = NULL;
6022 r = cui(vcpu);
6023 if (r <= 0)
6024 goto out;
6025 } else
6026 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 6027
851ba692 6028 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 6029
6030out:
f1d86e46 6031 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 6032 if (vcpu->sigset_active)
6033 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6034
b6c7a5dc
HB		 6035 return r;
6036}
6037
6038int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6039{
7ae441ea
GN		 6040 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6041 /*
6042 * We are here if userspace calls get_regs() in the middle of
6043 * instruction emulation. Registers state needs to be copied
4a969980 6044 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 6045 * that usually, but some bad designed PV devices (vmware
6046 * backdoor interface) need this to work
6047 */
dd856efa 6048 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 6049 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6050 }
5fdbf976
MT		 6051 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6052 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6053 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6054 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6055 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6056 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6057 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6058 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 6059#ifdef CONFIG_X86_64
5fdbf976
MT		 6060 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6061 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6062 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6063 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6064 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6065 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6066 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6067 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 6068#endif
6069
5fdbf976 6070 regs->rip = kvm_rip_read(vcpu);
91586a3b 6071 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 6072
b6c7a5dc
HB		 6073 return 0;
6074}
6075
6076int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6077{
7ae441ea
GN		 6078 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6079 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6080
5fdbf976
MT		 6081 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6082 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6083 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6084 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6085 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6086 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6087 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6088 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 6089#ifdef CONFIG_X86_64
5fdbf976
MT		 6090 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6091 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6092 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6093 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6094 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6095 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6096 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6097 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 6098#endif
6099
5fdbf976 6100 kvm_rip_write(vcpu, regs->rip);
91586a3b 6101 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 6102
b4f14abd
JK		 6103 vcpu->arch.exception.pending = false;
6104
3842d135
AK		 6105 kvm_make_request(KVM_REQ_EVENT, vcpu);
6106
b6c7a5dc
HB		 6107 return 0;
6108}
6109
b6c7a5dc
HB		 6110void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6111{
6112 struct kvm_segment cs;
6113
3e6e0aab 6114 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 6115 *db = cs.db;
6116 *l = cs.l;
6117}
6118EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6119
6120int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6121 struct kvm_sregs *sregs)
6122{
89a27f4d 6123 struct desc_ptr dt;
b6c7a5dc 6124
3e6e0aab
GT		 6125 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6126 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6127 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6128 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6129 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6130 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6131
3e6e0aab
GT		 6132 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6133 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 6134
6135 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 6136 sregs->idt.limit = dt.size;
6137 sregs->idt.base = dt.address;
b6c7a5dc 6138 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 6139 sregs->gdt.limit = dt.size;
6140 sregs->gdt.base = dt.address;
b6c7a5dc 6141
4d4ec087 6142 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 6143 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 6144 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 6145 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 6146 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 6147 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 6148 sregs->apic_base = kvm_get_apic_base(vcpu);
6149
923c61bb 6150 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 6151
36752c9b 6152 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 6153 set_bit(vcpu->arch.interrupt.nr,
6154 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 6155
b6c7a5dc
HB		 6156 return 0;
6157}
6158
62d9f0db
MT		 6159int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
6160 struct kvm_mp_state *mp_state)
6161{
62d9f0db 6162 mp_state->mp_state = vcpu->arch.mp_state;
62d9f0db
MT		 6163 return 0;
6164}
6165
6166int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
6167 struct kvm_mp_state *mp_state)
6168{
62d9f0db 6169 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 6170 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 6171 return 0;
6172}
6173
7f3d35fd
KW		 6174int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
6175 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 6176{
9d74191a 6177 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 6178 int ret;
e01c2426 6179
8ec4722d 6180 init_emulate_ctxt(vcpu);
c697518a 6181
7f3d35fd 6182 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 6183 has_error_code, error_code);
c697518a 6184
c697518a 6185 if (ret)
19d04437 6186 return EMULATE_FAIL;
37817f29 6187
9d74191a
TY		 6188 kvm_rip_write(vcpu, ctxt->eip);
6189 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 6190 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 6191 return EMULATE_DONE;
37817f29
IE		 6192}
6193EXPORT_SYMBOL_GPL(kvm_task_switch);
6194
b6c7a5dc
HB		 6195int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
6196 struct kvm_sregs *sregs)
6197{
6198 int mmu_reset_needed = 0;
63f42e02 6199 int pending_vec, max_bits, idx;
89a27f4d 6200 struct desc_ptr dt;
b6c7a5dc 6201
6d1068b3
PM		 6202 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
6203 return -EINVAL;
6204
89a27f4d
GN		 6205 dt.size = sregs->idt.limit;
6206 dt.address = sregs->idt.base;
b6c7a5dc 6207 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 6208 dt.size = sregs->gdt.limit;
6209 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 6210 kvm_x86_ops->set_gdt(vcpu, &dt);
6211
ad312c7c 6212 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 6213 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 6214 vcpu->arch.cr3 = sregs->cr3;
aff48baa 6215 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 6216
2d3ad1f4 6217 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 6218
f6801dff 6219 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 6220 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 6221 kvm_set_apic_base(vcpu, sregs->apic_base);
6222
4d4ec087 6223 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 6224 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 6225 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 6226
fc78f519 6227 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 6228 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c 6229 if (sregs->cr4 & X86_CR4_OSXSAVE)
00b27a3e 6230 kvm_update_cpuid(vcpu);
63f42e02
XG		 6231
6232 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 6233 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 6234 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 6235 mmu_reset_needed = 1;
6236 }
63f42e02 6237 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 6238
6239 if (mmu_reset_needed)
6240 kvm_mmu_reset_context(vcpu);
6241
a50abc3b 6242 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 6243 pending_vec = find_first_bit(
6244 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
6245 if (pending_vec < max_bits) {
66fd3f7f 6246 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 6247 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 6248 }
6249
3e6e0aab
GT		 6250 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6251 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6252 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6253 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6254 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6255 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6256
3e6e0aab
GT		 6257 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6258 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 6259
5f0269f5
ME		 6260 update_cr8_intercept(vcpu);
6261
9c3e4aab 6262 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 6263 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 6264 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 6265 !is_protmode(vcpu))
9c3e4aab
MT		 6266 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6267
3842d135
AK		 6268 kvm_make_request(KVM_REQ_EVENT, vcpu);
6269
b6c7a5dc
HB		 6270 return 0;
6271}
6272
d0bfb940
JK		 6273int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
6274 struct kvm_guest_debug *dbg)
b6c7a5dc 6275{
355be0b9 6276 unsigned long rflags;
ae675ef0 6277 int i, r;
b6c7a5dc 6278
4f926bf2
JK		 6279 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
6280 r = -EBUSY;
6281 if (vcpu->arch.exception.pending)
2122ff5e 6282 goto out;
4f926bf2
JK		 6283 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
6284 kvm_queue_exception(vcpu, DB_VECTOR);
6285 else
6286 kvm_queue_exception(vcpu, BP_VECTOR);
6287 }
6288
91586a3b
JK		 6289 /*
6290 * Read rflags as long as potentially injected trace flags are still
6291 * filtered out.
6292 */
6293 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 6294
6295 vcpu->guest_debug = dbg->control;
6296 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
6297 vcpu->guest_debug = 0;
6298
6299 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 6300 for (i = 0; i < KVM_NR_DB_REGS; ++i)
6301 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 6302 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 6303 } else {
6304 for (i = 0; i < KVM_NR_DB_REGS; i++)
6305 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 6306 }
c8639010 6307 kvm_update_dr7(vcpu);
ae675ef0 6308
f92653ee
JK		 6309 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6310 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
6311 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 6312
91586a3b
JK		 6313 /*
6314 * Trigger an rflags update that will inject or remove the trace
6315 * flags.
6316 */
6317 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 6318
c8639010 6319 kvm_x86_ops->update_db_bp_intercept(vcpu);
b6c7a5dc 6320
4f926bf2 6321 r = 0;
d0bfb940 6322
2122ff5e 6323out:
b6c7a5dc
HB		 6324
6325 return r;
6326}
6327
8b006791
ZX		 6328/*
6329 * Translate a guest virtual address to a guest physical address.
6330 */
6331int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
6332 struct kvm_translation *tr)
6333{
6334 unsigned long vaddr = tr->linear_address;
6335 gpa_t gpa;
f656ce01 6336 int idx;
8b006791 6337
f656ce01 6338 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 6339 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 6340 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 6341 tr->physical_address = gpa;
6342 tr->valid = gpa != UNMAPPED_GVA;
6343 tr->writeable = 1;
6344 tr->usermode = 0;
8b006791
ZX		 6345
6346 return 0;
6347}
6348
d0752060
HB		 6349int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6350{
98918833
SY		 6351 struct i387_fxsave_struct *fxsave =
6352 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 6353
d0752060
HB		 6354 memcpy(fpu->fpr, fxsave->st_space, 128);
6355 fpu->fcw = fxsave->cwd;
6356 fpu->fsw = fxsave->swd;
6357 fpu->ftwx = fxsave->twd;
6358 fpu->last_opcode = fxsave->fop;
6359 fpu->last_ip = fxsave->rip;
6360 fpu->last_dp = fxsave->rdp;
6361 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
6362
d0752060
HB		 6363 return 0;
6364}
6365
6366int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6367{
98918833
SY		 6368 struct i387_fxsave_struct *fxsave =
6369 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 6370
d0752060
HB		 6371 memcpy(fxsave->st_space, fpu->fpr, 128);
6372 fxsave->cwd = fpu->fcw;
6373 fxsave->swd = fpu->fsw;
6374 fxsave->twd = fpu->ftwx;
6375 fxsave->fop = fpu->last_opcode;
6376 fxsave->rip = fpu->last_ip;
6377 fxsave->rdp = fpu->last_dp;
6378 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
6379
d0752060
HB		 6380 return 0;
6381}
6382
10ab25cd 6383int fx_init(struct kvm_vcpu *vcpu)
d0752060 6384{
10ab25cd
JK		 6385 int err;
6386
6387 err = fpu_alloc(&vcpu->arch.guest_fpu);
6388 if (err)
6389 return err;
6390
98918833 6391 fpu_finit(&vcpu->arch.guest_fpu);
d0752060 6392
2acf923e
DC		 6393 /*
6394 * Ensure guest xcr0 is valid for loading
6395 */
6396 vcpu->arch.xcr0 = XSTATE_FP;
6397
ad312c7c 6398 vcpu->arch.cr0 |= X86_CR0_ET;
10ab25cd
JK		 6399
6400 return 0;
d0752060
HB		 6401}
6402EXPORT_SYMBOL_GPL(fx_init);
6403
98918833
SY		 6404static void fx_free(struct kvm_vcpu *vcpu)
6405{
6406 fpu_free(&vcpu->arch.guest_fpu);
6407}
6408
d0752060
HB		 6409void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
6410{
2608d7a1 6411 if (vcpu->guest_fpu_loaded)
d0752060
HB		 6412 return;
6413
2acf923e
DC		 6414 /*
6415 * Restore all possible states in the guest,
6416 * and assume host would use all available bits.
6417 * Guest xcr0 would be loaded later.
6418 */
6419 kvm_put_guest_xcr0(vcpu);
d0752060 6420 vcpu->guest_fpu_loaded = 1;
b1a74bf8 6421 __kernel_fpu_begin();
98918833 6422 fpu_restore_checking(&vcpu->arch.guest_fpu);
0c04851c 6423 trace_kvm_fpu(1);
d0752060 6424}
d0752060
HB		 6425
6426void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
6427{
2acf923e
DC		 6428 kvm_put_guest_xcr0(vcpu);
6429
d0752060
HB		 6430 if (!vcpu->guest_fpu_loaded)
6431 return;
6432
6433 vcpu->guest_fpu_loaded = 0;
98918833 6434 fpu_save_init(&vcpu->arch.guest_fpu);
b1a74bf8 6435 __kernel_fpu_end();
f096ed85 6436 ++vcpu->stat.fpu_reload;
a8eeb04a 6437 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
0c04851c 6438 trace_kvm_fpu(0);
d0752060 6439}
e9b11c17
ZX		 6440
6441void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
6442{
12f9a48f 6443 kvmclock_reset(vcpu);
7f1ea208 6444
f5f48ee1 6445 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
98918833 6446 fx_free(vcpu);
e9b11c17
ZX		 6447 kvm_x86_ops->vcpu_free(vcpu);
6448}
6449
6450struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
6451 unsigned int id)
6452{
6755bae8
ZA		 6453 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6454 printk_once(KERN_WARNING
6455 "kvm: SMP vm created on host with unstable TSC; "
6456 "guest TSC will not be reliable\n");
26e5215f
AK		 6457 return kvm_x86_ops->vcpu_create(kvm, id);
6458}
e9b11c17 6459
26e5215f
AK		 6460int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
6461{
6462 int r;
e9b11c17 6463
0bed3b56 6464 vcpu->arch.mtrr_state.have_fixed = 1;
9fc77441
MT		 6465 r = vcpu_load(vcpu);
6466 if (r)
6467 return r;
8b6e4547 6468 r = kvm_vcpu_reset(vcpu);
e9b11c17
ZX		 6469 if (r == 0)
6470 r = kvm_mmu_setup(vcpu);
6471 vcpu_put(vcpu);
e9b11c17 6472
26e5215f 6473 return r;
e9b11c17
ZX		 6474}
6475
42897d86
MT		 6476int kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
6477{
6478 int r;
8fe8ab46 6479 struct msr_data msr;
42897d86
MT		 6480
6481 r = vcpu_load(vcpu);
6482 if (r)
6483 return r;
8fe8ab46
WA		 6484 msr.data = 0x0;
6485 msr.index = MSR_IA32_TSC;
6486 msr.host_initiated = true;
6487 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 6488 vcpu_put(vcpu);
6489
6490 return r;
6491}
6492
d40ccc62 6493void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 6494{
9fc77441 6495 int r;
344d9588
GN		 6496 vcpu->arch.apf.msr_val = 0;
6497
9fc77441
MT		 6498 r = vcpu_load(vcpu);
6499 BUG_ON(r);
e9b11c17
ZX		 6500 kvm_mmu_unload(vcpu);
6501 vcpu_put(vcpu);
6502
98918833 6503 fx_free(vcpu);
e9b11c17
ZX		 6504 kvm_x86_ops->vcpu_free(vcpu);
6505}
6506
8b6e4547 6507static int kvm_vcpu_reset(struct kvm_vcpu *vcpu)
e9b11c17 6508{
7460fb4a
AK		 6509 atomic_set(&vcpu->arch.nmi_queued, 0);
6510 vcpu->arch.nmi_pending = 0;
448fa4a9
JK		 6511 vcpu->arch.nmi_injected = false;
6512
42dbaa5a
JK		 6513 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
6514 vcpu->arch.dr6 = DR6_FIXED_1;
6515 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 6516 kvm_update_dr7(vcpu);
42dbaa5a 6517
3842d135 6518 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 6519 vcpu->arch.apf.msr_val = 0;
c9aaa895 6520 vcpu->arch.st.msr_val = 0;
3842d135 6521
12f9a48f
GC		 6522 kvmclock_reset(vcpu);
6523
af585b92
GN		 6524 kvm_clear_async_pf_completion_queue(vcpu);
6525 kvm_async_pf_hash_reset(vcpu);
6526 vcpu->arch.apf.halted = false;
3842d135 6527
f5132b01
GN		 6528 kvm_pmu_reset(vcpu);
6529
66f7b72e
JS		 6530 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
6531 vcpu->arch.regs_avail = ~0;
6532 vcpu->arch.regs_dirty = ~0;
6533
e9b11c17
ZX		 6534 return kvm_x86_ops->vcpu_reset(vcpu);
6535}
6536
10474ae8 6537int kvm_arch_hardware_enable(void *garbage)
e9b11c17 6538{
ca84d1a2
ZA		 6539 struct kvm *kvm;
6540 struct kvm_vcpu *vcpu;
6541 int i;
0dd6a6ed
ZA		 6542 int ret;
6543 u64 local_tsc;
6544 u64 max_tsc = 0;
6545 bool stable, backwards_tsc = false;
18863bdd
AK		 6546
6547 kvm_shared_msr_cpu_online();
0dd6a6ed
ZA		 6548 ret = kvm_x86_ops->hardware_enable(garbage);
6549 if (ret != 0)
6550 return ret;
6551
6552 local_tsc = native_read_tsc();
6553 stable = !check_tsc_unstable();
6554 list_for_each_entry(kvm, &vm_list, vm_list) {
6555 kvm_for_each_vcpu(i, vcpu, kvm) {
6556 if (!stable && vcpu->cpu == smp_processor_id())
6557 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
6558 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
6559 backwards_tsc = true;
6560 if (vcpu->arch.last_host_tsc > max_tsc)
6561 max_tsc = vcpu->arch.last_host_tsc;
6562 }
6563 }
6564 }
6565
6566 /*
6567 * Sometimes, even reliable TSCs go backwards. This happens on
6568 * platforms that reset TSC during suspend or hibernate actions, but
6569 * maintain synchronization. We must compensate. Fortunately, we can
6570 * detect that condition here, which happens early in CPU bringup,
6571 * before any KVM threads can be running. Unfortunately, we can't
6572 * bring the TSCs fully up to date with real time, as we aren't yet far
6573 * enough into CPU bringup that we know how much real time has actually
6574 * elapsed; our helper function, get_kernel_ns() will be using boot
6575 * variables that haven't been updated yet.
6576 *
6577 * So we simply find the maximum observed TSC above, then record the
6578 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
6579 * the adjustment will be applied. Note that we accumulate
6580 * adjustments, in case multiple suspend cycles happen before some VCPU
6581 * gets a chance to run again. In the event that no KVM threads get a
6582 * chance to run, we will miss the entire elapsed period, as we'll have
6583 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
6584 * loose cycle time. This isn't too big a deal, since the loss will be
6585 * uniform across all VCPUs (not to mention the scenario is extremely
6586 * unlikely). It is possible that a second hibernate recovery happens
6587 * much faster than a first, causing the observed TSC here to be
6588 * smaller; this would require additional padding adjustment, which is
6589 * why we set last_host_tsc to the local tsc observed here.
6590 *
6591 * N.B. - this code below runs only on platforms with reliable TSC,
6592 * as that is the only way backwards_tsc is set above. Also note
6593 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
6594 * have the same delta_cyc adjustment applied if backwards_tsc
6595 * is detected. Note further, this adjustment is only done once,
6596 * as we reset last_host_tsc on all VCPUs to stop this from being
6597 * called multiple times (one for each physical CPU bringup).
6598 *
4a969980 6599 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 6600 * will be compensated by the logic in vcpu_load, which sets the TSC to
6601 * catchup mode. This will catchup all VCPUs to real time, but cannot
6602 * guarantee that they stay in perfect synchronization.
6603 */
6604 if (backwards_tsc) {
6605 u64 delta_cyc = max_tsc - local_tsc;
6606 list_for_each_entry(kvm, &vm_list, vm_list) {
6607 kvm_for_each_vcpu(i, vcpu, kvm) {
6608 vcpu->arch.tsc_offset_adjustment += delta_cyc;
6609 vcpu->arch.last_host_tsc = local_tsc;
d828199e
MT		 6610 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
6611 &vcpu->requests);
0dd6a6ed
ZA		 6612 }
6613
6614 /*
6615 * We have to disable TSC offset matching.. if you were
6616 * booting a VM while issuing an S4 host suspend....
6617 * you may have some problem. Solving this issue is
6618 * left as an exercise to the reader.
6619 */
6620 kvm->arch.last_tsc_nsec = 0;
6621 kvm->arch.last_tsc_write = 0;
6622 }
6623
6624 }
6625 return 0;
e9b11c17
ZX		 6626}
6627
6628void kvm_arch_hardware_disable(void *garbage)
6629{
6630 kvm_x86_ops->hardware_disable(garbage);
3548bab5 6631 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 6632}
6633
6634int kvm_arch_hardware_setup(void)
6635{
6636 return kvm_x86_ops->hardware_setup();
6637}
6638
6639void kvm_arch_hardware_unsetup(void)
6640{
6641 kvm_x86_ops->hardware_unsetup();
6642}
6643
6644void kvm_arch_check_processor_compat(void *rtn)
6645{
6646 kvm_x86_ops->check_processor_compatibility(rtn);
6647}
6648
3e515705
AK		 6649bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
6650{
6651 return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL);
6652}
6653
54e9818f
GN		 6654struct static_key kvm_no_apic_vcpu __read_mostly;
6655
e9b11c17
ZX		 6656int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
6657{
6658 struct page *page;
6659 struct kvm *kvm;
6660 int r;
6661
6662 BUG_ON(vcpu->kvm == NULL);
6663 kvm = vcpu->kvm;
6664
9aabc88f 6665 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
c5af89b6 6666 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 6667 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 6668 else
a4535290 6669 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 6670
6671 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
6672 if (!page) {
6673 r = -ENOMEM;
6674 goto fail;
6675 }
ad312c7c 6676 vcpu->arch.pio_data = page_address(page);
e9b11c17 6677
cc578287 6678 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 6679
e9b11c17
ZX		 6680 r = kvm_mmu_create(vcpu);
6681 if (r < 0)
6682 goto fail_free_pio_data;
6683
6684 if (irqchip_in_kernel(kvm)) {
6685 r = kvm_create_lapic(vcpu);
6686 if (r < 0)
6687 goto fail_mmu_destroy;
54e9818f
GN		 6688 } else
6689 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 6690
890ca9ae
YH		 6691 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
6692 GFP_KERNEL);
6693 if (!vcpu->arch.mce_banks) {
6694 r = -ENOMEM;
443c39bc 6695 goto fail_free_lapic;
890ca9ae
YH		 6696 }
6697 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
6698
f5f48ee1
SY		 6699 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL))
6700 goto fail_free_mce_banks;
6701
66f7b72e
JS		 6702 r = fx_init(vcpu);
6703 if (r)
6704 goto fail_free_wbinvd_dirty_mask;
6705
ba904635 6706 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
af585b92 6707 kvm_async_pf_hash_reset(vcpu);
f5132b01 6708 kvm_pmu_init(vcpu);
af585b92 6709
e9b11c17 6710 return 0;
66f7b72e
JS		 6711fail_free_wbinvd_dirty_mask:
6712 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 6713fail_free_mce_banks:
6714 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 6715fail_free_lapic:
6716 kvm_free_lapic(vcpu);
e9b11c17
ZX		 6717fail_mmu_destroy:
6718 kvm_mmu_destroy(vcpu);
6719fail_free_pio_data:
ad312c7c 6720 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 6721fail:
6722 return r;
6723}
6724
6725void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
6726{
f656ce01
MT		 6727 int idx;
6728
f5132b01 6729 kvm_pmu_destroy(vcpu);
36cb93fd 6730 kfree(vcpu->arch.mce_banks);
e9b11c17 6731 kvm_free_lapic(vcpu);
f656ce01 6732 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 6733 kvm_mmu_destroy(vcpu);
f656ce01 6734 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 6735 free_page((unsigned long)vcpu->arch.pio_data);
54e9818f
GN		 6736 if (!irqchip_in_kernel(vcpu->kvm))
6737 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 6738}
d19a9cd2 6739
e08b9637 6740int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 6741{
e08b9637
CO		 6742 if (type)
6743 return -EINVAL;
6744
f05e70ac 6745 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 6746 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 6747
5550af4d
SY		 6748 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
6749 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 6750 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
6751 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
6752 &kvm->arch.irq_sources_bitmap);
5550af4d 6753
038f8c11 6754 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 6755 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 6756 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
6757
6758 pvclock_update_vm_gtod_copy(kvm);
53f658b3 6759
d89f5eff 6760 return 0;
d19a9cd2
ZX		 6761}
6762
6763static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
6764{
9fc77441
MT		 6765 int r;
6766 r = vcpu_load(vcpu);
6767 BUG_ON(r);
d19a9cd2
ZX		 6768 kvm_mmu_unload(vcpu);
6769 vcpu_put(vcpu);
6770}
6771
6772static void kvm_free_vcpus(struct kvm *kvm)
6773{
6774 unsigned int i;
988a2cae 6775 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 6776
6777 /*
6778 * Unpin any mmu pages first.
6779 */
af585b92
GN		 6780 kvm_for_each_vcpu(i, vcpu, kvm) {
6781 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 6782 kvm_unload_vcpu_mmu(vcpu);
af585b92 6783 }
988a2cae
GN		 6784 kvm_for_each_vcpu(i, vcpu, kvm)
6785 kvm_arch_vcpu_free(vcpu);
6786
6787 mutex_lock(&kvm->lock);
6788 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
6789 kvm->vcpus[i] = NULL;
d19a9cd2 6790
988a2cae
GN		 6791 atomic_set(&kvm->online_vcpus, 0);
6792 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 6793}
6794
ad8ba2cd
SY		 6795void kvm_arch_sync_events(struct kvm *kvm)
6796{
ba4cef31 6797 kvm_free_all_assigned_devices(kvm);
aea924f6 6798 kvm_free_pit(kvm);
ad8ba2cd
SY		 6799}
6800
d19a9cd2
ZX		 6801void kvm_arch_destroy_vm(struct kvm *kvm)
6802{
6eb55818 6803 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 6804 kfree(kvm->arch.vpic);
6805 kfree(kvm->arch.vioapic);
d19a9cd2 6806 kvm_free_vcpus(kvm);
3d45830c
AK		 6807 if (kvm->arch.apic_access_page)
6808 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 6809 if (kvm->arch.ept_identity_pagetable)
6810 put_page(kvm->arch.ept_identity_pagetable);
1e08ec4a 6811 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
d19a9cd2 6812}
0de10343 6813
db3fe4eb
TY		 6814void kvm_arch_free_memslot(struct kvm_memory_slot *free,
6815 struct kvm_memory_slot *dont)
6816{
6817 int i;
6818
d89cc617
TY		 6819 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
6820 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
6821 kvm_kvfree(free->arch.rmap[i]);
6822 free->arch.rmap[i] = NULL;
77d11309 6823 }
d89cc617
TY		 6824 if (i == 0)
6825 continue;
6826
6827 if (!dont || free->arch.lpage_info[i - 1] !=
6828 dont->arch.lpage_info[i - 1]) {
6829 kvm_kvfree(free->arch.lpage_info[i - 1]);
6830 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 6831 }
6832 }
6833}
6834
6835int kvm_arch_create_memslot(struct kvm_memory_slot *slot, unsigned long npages)
6836{
6837 int i;
6838
d89cc617 6839 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
db3fe4eb
TY		 6840 unsigned long ugfn;
6841 int lpages;
d89cc617 6842 int level = i + 1;
db3fe4eb
TY		 6843
6844 lpages = gfn_to_index(slot->base_gfn + npages - 1,
6845 slot->base_gfn, level) + 1;
6846
d89cc617
TY		 6847 slot->arch.rmap[i] =
6848 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
6849 if (!slot->arch.rmap[i])
77d11309 6850 goto out_free;
d89cc617
TY		 6851 if (i == 0)
6852 continue;
77d11309 6853
d89cc617
TY		 6854 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
6855 sizeof(*slot->arch.lpage_info[i - 1]));
6856 if (!slot->arch.lpage_info[i - 1])
db3fe4eb
TY		 6857 goto out_free;
6858
6859 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 6860 slot->arch.lpage_info[i - 1][0].write_count = 1;
db3fe4eb 6861 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 6862 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
db3fe4eb
TY		 6863 ugfn = slot->userspace_addr >> PAGE_SHIFT;
6864 /*
6865 * If the gfn and userspace address are not aligned wrt each
6866 * other, or if explicitly asked to, disable large page
6867 * support for this slot
6868 */
6869 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
6870 !kvm_largepages_enabled()) {
6871 unsigned long j;
6872
6873 for (j = 0; j < lpages; ++j)
d89cc617 6874 slot->arch.lpage_info[i - 1][j].write_count = 1;
db3fe4eb
TY		 6875 }
6876 }
6877
6878 return 0;
6879
6880out_free:
d89cc617
TY		 6881 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
6882 kvm_kvfree(slot->arch.rmap[i]);
6883 slot->arch.rmap[i] = NULL;
6884 if (i == 0)
6885 continue;
6886
6887 kvm_kvfree(slot->arch.lpage_info[i - 1]);
6888 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 6889 }
6890 return -ENOMEM;
6891}
6892
f7784b8e
MT		 6893int kvm_arch_prepare_memory_region(struct kvm *kvm,
6894 struct kvm_memory_slot *memslot,
0de10343 6895 struct kvm_memory_slot old,
f7784b8e 6896 struct kvm_userspace_memory_region *mem,
f82a8cfe 6897 bool user_alloc)
0de10343 6898{
f7784b8e 6899 int npages = memslot->npages;
7ac77099
AK		 6900 int map_flags = MAP_PRIVATE | MAP_ANONYMOUS;
6901
6902 /* Prevent internal slot pages from being moved by fork()/COW. */
bbacc0c1 6903 if (memslot->id >= KVM_USER_MEM_SLOTS)
7ac77099 6904 map_flags = MAP_SHARED | MAP_ANONYMOUS;
0de10343
ZX		 6905
6906 /*To keep backward compatibility with older userspace,
4a969980 6907 *x86 needs to handle !user_alloc case.
0de10343
ZX		 6908 */
6909 if (!user_alloc) {
aab2eb7a 6910 if (npages && !old.npages) {
604b38ac
AA		 6911 unsigned long userspace_addr;
6912
6be5ceb0 6913 userspace_addr = vm_mmap(NULL, 0,
604b38ac
AA		 6914 npages * PAGE_SIZE,
6915 PROT_READ | PROT_WRITE,
7ac77099 6916 map_flags,
604b38ac 6917 0);
0de10343 6918
604b38ac
AA		 6919 if (IS_ERR((void *)userspace_addr))
6920 return PTR_ERR((void *)userspace_addr);
6921
604b38ac 6922 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 6923 }
6924 }
6925
f7784b8e
MT		 6926
6927 return 0;
6928}
6929
6930void kvm_arch_commit_memory_region(struct kvm *kvm,
6931 struct kvm_userspace_memory_region *mem,
6932 struct kvm_memory_slot old,
f82a8cfe 6933 bool user_alloc)
f7784b8e
MT		 6934{
6935
48c0e4e9 6936 int nr_mmu_pages = 0, npages = mem->memory_size >> PAGE_SHIFT;
f7784b8e 6937
aab2eb7a 6938 if (!user_alloc && !old.user_alloc && old.npages && !npages) {
f7784b8e
MT		 6939 int ret;
6940
bfce281c 6941 ret = vm_munmap(old.userspace_addr,
f7784b8e 6942 old.npages * PAGE_SIZE);
f7784b8e
MT		 6943 if (ret < 0)
6944 printk(KERN_WARNING
6945 "kvm_vm_ioctl_set_memory_region: "
6946 "failed to munmap memory\n");
6947 }
6948
48c0e4e9
XG		 6949 if (!kvm->arch.n_requested_mmu_pages)
6950 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
6951
48c0e4e9 6952 if (nr_mmu_pages)
0de10343 6953 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
c972f3b1
TY		 6954 /*
6955 * Write protect all pages for dirty logging.
6956 * Existing largepage mappings are destroyed here and new ones will
6957 * not be created until the end of the logging.
6958 */
9d1beefb 6959 if (npages && (mem->flags & KVM_MEM_LOG_DIRTY_PAGES))
c972f3b1 6960 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
3b4dc3a0
MT		 6961 /*
6962 * If memory slot is created, or moved, we need to clear all
6963 * mmio sptes.
6964 */
6965 if (npages && old.base_gfn != mem->guest_phys_addr >> PAGE_SHIFT) {
6966 kvm_mmu_zap_all(kvm);
6967 kvm_reload_remote_mmus(kvm);
6968 }
0de10343 6969}
1d737c8a 6970
2df72e9b 6971void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f
MT		 6972{
6973 kvm_mmu_zap_all(kvm);
8986ecc0 6974 kvm_reload_remote_mmus(kvm);
34d4cb8f
MT		 6975}
6976
2df72e9b
MT		 6977void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
6978 struct kvm_memory_slot *slot)
6979{
6980 kvm_arch_flush_shadow_all(kvm);
6981}
6982
1d737c8a
ZX		 6983int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
6984{
af585b92
GN		 6985 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6986 !vcpu->arch.apf.halted)
6987 || !list_empty_careful(&vcpu->async_pf.done)
a1b37100 6988 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
7460fb4a 6989 || atomic_read(&vcpu->arch.nmi_queued) ||
a1b37100
GN		 6990 (kvm_arch_interrupt_allowed(vcpu) &&
6991 kvm_cpu_has_interrupt(vcpu));
1d737c8a 6992}
5736199a 6993
b6d33834 6994int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 6995{
b6d33834 6996 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 6997}
78646121
GN		 6998
6999int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
7000{
7001 return kvm_x86_ops->interrupt_allowed(vcpu);
7002}
229456fc 7003
f92653ee
JK		 7004bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
7005{
7006 unsigned long current_rip = kvm_rip_read(vcpu) +
7007 get_segment_base(vcpu, VCPU_SREG_CS);
7008
7009 return current_rip == linear_rip;
7010}
7011EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
7012
94fe45da
JK		 7013unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
7014{
7015 unsigned long rflags;
7016
7017 rflags = kvm_x86_ops->get_rflags(vcpu);
7018 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 7019 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 7020 return rflags;
7021}
7022EXPORT_SYMBOL_GPL(kvm_get_rflags);
7023
7024void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
7025{
7026 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 7027 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 7028 rflags |= X86_EFLAGS_TF;
94fe45da 7029 kvm_x86_ops->set_rflags(vcpu, rflags);
3842d135 7030 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 7031}
7032EXPORT_SYMBOL_GPL(kvm_set_rflags);
7033
56028d08
GN		 7034void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
7035{
7036 int r;
7037
fb67e14f 7038 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
c4806acd 7039 is_error_page(work->page))
56028d08
GN		 7040 return;
7041
7042 r = kvm_mmu_reload(vcpu);
7043 if (unlikely(r))
7044 return;
7045
fb67e14f
XG		 7046 if (!vcpu->arch.mmu.direct_map &&
7047 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
7048 return;
7049
56028d08
GN		 7050 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
7051}
7052
af585b92
GN		 7053static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
7054{
7055 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
7056}
7057
7058static inline u32 kvm_async_pf_next_probe(u32 key)
7059{
7060 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
7061}
7062
7063static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7064{
7065 u32 key = kvm_async_pf_hash_fn(gfn);
7066
7067 while (vcpu->arch.apf.gfns[key] != ~0)
7068 key = kvm_async_pf_next_probe(key);
7069
7070 vcpu->arch.apf.gfns[key] = gfn;
7071}
7072
7073static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
7074{
7075 int i;
7076 u32 key = kvm_async_pf_hash_fn(gfn);
7077
7078 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 7079 (vcpu->arch.apf.gfns[key] != gfn &&
7080 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 7081 key = kvm_async_pf_next_probe(key);
7082
7083 return key;
7084}
7085
7086bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7087{
7088 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
7089}
7090
7091static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7092{
7093 u32 i, j, k;
7094
7095 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
7096 while (true) {
7097 vcpu->arch.apf.gfns[i] = ~0;
7098 do {
7099 j = kvm_async_pf_next_probe(j);
7100 if (vcpu->arch.apf.gfns[j] == ~0)
7101 return;
7102 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
7103 /*
7104 * k lies cyclically in ]i,j]
7105 * | i.k.j |
7106 * |....j i.k.| or |.k..j i...|
7107 */
7108 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
7109 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
7110 i = j;
7111 }
7112}
7113
7c90705b
GN		 7114static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
7115{
7116
7117 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
7118 sizeof(val));
7119}
7120
af585b92
GN		 7121void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
7122 struct kvm_async_pf *work)
7123{
6389ee94
AK		 7124 struct x86_exception fault;
7125
7c90705b 7126 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 7127 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 7128
7129 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 7130 (vcpu->arch.apf.send_user_only &&
7131 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 7132 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
7133 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 7134 fault.vector = PF_VECTOR;
7135 fault.error_code_valid = true;
7136 fault.error_code = 0;
7137 fault.nested_page_fault = false;
7138 fault.address = work->arch.token;
7139 kvm_inject_page_fault(vcpu, &fault);
7c90705b 7140 }
af585b92
GN		 7141}
7142
7143void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
7144 struct kvm_async_pf *work)
7145{
6389ee94
AK		 7146 struct x86_exception fault;
7147
7c90705b
GN		 7148 trace_kvm_async_pf_ready(work->arch.token, work->gva);
7149 if (is_error_page(work->page))
7150 work->arch.token = ~0; /* broadcast wakeup */
7151 else
7152 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
7153
7154 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
7155 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 7156 fault.vector = PF_VECTOR;
7157 fault.error_code_valid = true;
7158 fault.error_code = 0;
7159 fault.nested_page_fault = false;
7160 fault.address = work->arch.token;
7161 kvm_inject_page_fault(vcpu, &fault);
7c90705b 7162 }
e6d53e3b 7163 vcpu->arch.apf.halted = false;
a4fa1635 7164 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 7165}
7166
7167bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
7168{
7169 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
7170 return true;
7171 else
7172 return !kvm_event_needs_reinjection(vcpu) &&
7173 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 7174}
7175
229456fc
MT		 7176EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
7177EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
7178EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
7179EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
7180EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 7181EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 7182EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 7183EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 7184EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 7185EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 7186EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 7187EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
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