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KVM: MMU: allow the vm to shrink the kvm mmu shadow caches
[linux.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 *
8 * Authors:
9 * Avi Kivity <[email protected]>
10 * Yaniv Kamay <[email protected]>
11 *
12 * This work is licensed under the terms of the GNU GPL, version 2. See
13 * the COPYING file in the top-level directory.
14 *
15 */
16
edf88417 17#include <linux/kvm_host.h>
313a3dc7 18#include "irq.h"
1d737c8a 19#include "mmu.h"
7837699f 20#include "i8254.h"
37817f29 21#include "tss.h"
313a3dc7 22
18068523 23#include <linux/clocksource.h>
313a3dc7
CO		 24#include <linux/kvm.h>
25#include <linux/fs.h>
26#include <linux/vmalloc.h>
5fb76f9b 27#include <linux/module.h>
0de10343 28#include <linux/mman.h>
2bacc55c 29#include <linux/highmem.h>
043405e1
CO		 30
31#include <asm/uaccess.h>
d825ed0a 32#include <asm/msr.h>
a5f61300 33#include <asm/desc.h>
043405e1 34
313a3dc7 35#define MAX_IO_MSRS 256
a03490ed
CO		 36#define CR0_RESERVED_BITS \
37 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
38 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
39 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))
40#define CR4_RESERVED_BITS \
41 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
42 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \
43 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \
44 | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
45
46#define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
50a37eb4
JR		 47/* EFER defaults:
48 * - enable syscall per default because its emulated by KVM
49 * - enable LME and LMA per default on 64 bit KVM
50 */
51#ifdef CONFIG_X86_64
52static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffafeULL;
53#else
54static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffffeULL;
55#endif
313a3dc7 56
ba1389b7
AK		 57#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
58#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 59
674eea0f
AK		 60static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
61 struct kvm_cpuid_entry2 __user *entries);
62
97896d04
ZX		 63struct kvm_x86_ops *kvm_x86_ops;
64
417bc304 65struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 66 { "pf_fixed", VCPU_STAT(pf_fixed) },
67 { "pf_guest", VCPU_STAT(pf_guest) },
68 { "tlb_flush", VCPU_STAT(tlb_flush) },
69 { "invlpg", VCPU_STAT(invlpg) },
70 { "exits", VCPU_STAT(exits) },
71 { "io_exits", VCPU_STAT(io_exits) },
72 { "mmio_exits", VCPU_STAT(mmio_exits) },
73 { "signal_exits", VCPU_STAT(signal_exits) },
74 { "irq_window", VCPU_STAT(irq_window_exits) },
75 { "halt_exits", VCPU_STAT(halt_exits) },
76 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 77 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 78 { "request_irq", VCPU_STAT(request_irq_exits) },
79 { "irq_exits", VCPU_STAT(irq_exits) },
80 { "host_state_reload", VCPU_STAT(host_state_reload) },
81 { "efer_reload", VCPU_STAT(efer_reload) },
82 { "fpu_reload", VCPU_STAT(fpu_reload) },
83 { "insn_emulation", VCPU_STAT(insn_emulation) },
84 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
4cee5764
AK		 85 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
86 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
87 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
88 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
89 { "mmu_flooded", VM_STAT(mmu_flooded) },
90 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 91 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
0f74a24c 92 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 93 { "largepages", VM_STAT(lpages) },
417bc304
HB		 94 { NULL }
95};
96
97
5fb76f9b
CO		 98unsigned long segment_base(u16 selector)
99{
100 struct descriptor_table gdt;
a5f61300 101 struct desc_struct *d;
5fb76f9b
CO		 102 unsigned long table_base;
103 unsigned long v;
104
105 if (selector == 0)
106 return 0;
107
108 asm("sgdt %0" : "=m"(gdt));
109 table_base = gdt.base;
110
111 if (selector & 4) { /* from ldt */
112 u16 ldt_selector;
113
114 asm("sldt %0" : "=g"(ldt_selector));
115 table_base = segment_base(ldt_selector);
116 }
a5f61300
AK		 117 d = (struct desc_struct *)(table_base + (selector & ~7));
118 v = d->base0 | ((unsigned long)d->base1 << 16) |
119 ((unsigned long)d->base2 << 24);
5fb76f9b 120#ifdef CONFIG_X86_64
a5f61300
AK		 121 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
122 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
5fb76f9b
CO		 123#endif
124 return v;
125}
126EXPORT_SYMBOL_GPL(segment_base);
127
6866b83e
CO		 128u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
129{
130 if (irqchip_in_kernel(vcpu->kvm))
ad312c7c 131 return vcpu->arch.apic_base;
6866b83e 132 else
ad312c7c 133 return vcpu->arch.apic_base;
6866b83e
CO		 134}
135EXPORT_SYMBOL_GPL(kvm_get_apic_base);
136
137void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
138{
139 /* TODO: reserve bits check */
140 if (irqchip_in_kernel(vcpu->kvm))
141 kvm_lapic_set_base(vcpu, data);
142 else
ad312c7c 143 vcpu->arch.apic_base = data;
6866b83e
CO		 144}
145EXPORT_SYMBOL_GPL(kvm_set_apic_base);
146
298101da
AK		 147void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
148{
ad312c7c
ZX		 149 WARN_ON(vcpu->arch.exception.pending);
150 vcpu->arch.exception.pending = true;
151 vcpu->arch.exception.has_error_code = false;
152 vcpu->arch.exception.nr = nr;
298101da
AK		 153}
154EXPORT_SYMBOL_GPL(kvm_queue_exception);
155
c3c91fee
AK		 156void kvm_inject_page_fault(struct kvm_vcpu *vcpu, unsigned long addr,
157 u32 error_code)
158{
159 ++vcpu->stat.pf_guest;
71c4dfaf
JR		 160 if (vcpu->arch.exception.pending) {
161 if (vcpu->arch.exception.nr == PF_VECTOR) {
162 printk(KERN_DEBUG "kvm: inject_page_fault:"
163 " double fault 0x%lx\n", addr);
164 vcpu->arch.exception.nr = DF_VECTOR;
165 vcpu->arch.exception.error_code = 0;
166 } else if (vcpu->arch.exception.nr == DF_VECTOR) {
167 /* triple fault -> shutdown */
168 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
169 }
c3c91fee
AK		 170 return;
171 }
ad312c7c 172 vcpu->arch.cr2 = addr;
c3c91fee
AK		 173 kvm_queue_exception_e(vcpu, PF_VECTOR, error_code);
174}
175
298101da
AK		 176void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
177{
ad312c7c
ZX		 178 WARN_ON(vcpu->arch.exception.pending);
179 vcpu->arch.exception.pending = true;
180 vcpu->arch.exception.has_error_code = true;
181 vcpu->arch.exception.nr = nr;
182 vcpu->arch.exception.error_code = error_code;
298101da
AK		 183}
184EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
185
186static void __queue_exception(struct kvm_vcpu *vcpu)
187{
ad312c7c
ZX		 188 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
189 vcpu->arch.exception.has_error_code,
190 vcpu->arch.exception.error_code);
298101da
AK		 191}
192
a03490ed
CO		 193/*
194 * Load the pae pdptrs. Return true is they are all valid.
195 */
196int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3)
197{
198 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
199 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
200 int i;
201 int ret;
ad312c7c 202 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
a03490ed 203
a03490ed
CO		 204 ret = kvm_read_guest_page(vcpu->kvm, pdpt_gfn, pdpte,
205 offset * sizeof(u64), sizeof(pdpte));
206 if (ret < 0) {
207 ret = 0;
208 goto out;
209 }
210 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
211 if ((pdpte[i] & 1) && (pdpte[i] & 0xfffffff0000001e6ull)) {
212 ret = 0;
213 goto out;
214 }
215 }
216 ret = 1;
217
ad312c7c 218 memcpy(vcpu->arch.pdptrs, pdpte, sizeof(vcpu->arch.pdptrs));
a03490ed 219out:
a03490ed
CO		 220
221 return ret;
222}
cc4b6871 223EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 224
d835dfec
AK		 225static bool pdptrs_changed(struct kvm_vcpu *vcpu)
226{
ad312c7c 227 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
d835dfec
AK		 228 bool changed = true;
229 int r;
230
231 if (is_long_mode(vcpu) || !is_pae(vcpu))
232 return false;
233
ad312c7c 234 r = kvm_read_guest(vcpu->kvm, vcpu->arch.cr3 & ~31u, pdpte, sizeof(pdpte));
d835dfec
AK		 235 if (r < 0)
236 goto out;
ad312c7c 237 changed = memcmp(pdpte, vcpu->arch.pdptrs, sizeof(pdpte)) != 0;
d835dfec 238out:
d835dfec
AK		 239
240 return changed;
241}
242
2d3ad1f4 243void kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed
CO		 244{
245 if (cr0 & CR0_RESERVED_BITS) {
246 printk(KERN_DEBUG "set_cr0: 0x%lx #GP, reserved bits 0x%lx\n",
ad312c7c 247 cr0, vcpu->arch.cr0);
c1a5d4f9 248 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 249 return;
250 }
251
252 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) {
253 printk(KERN_DEBUG "set_cr0: #GP, CD == 0 && NW == 1\n");
c1a5d4f9 254 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 255 return;
256 }
257
258 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) {
259 printk(KERN_DEBUG "set_cr0: #GP, set PG flag "
260 "and a clear PE flag\n");
c1a5d4f9 261 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 262 return;
263 }
264
265 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
266#ifdef CONFIG_X86_64
ad312c7c 267 if ((vcpu->arch.shadow_efer & EFER_LME)) {
a03490ed
CO		 268 int cs_db, cs_l;
269
270 if (!is_pae(vcpu)) {
271 printk(KERN_DEBUG "set_cr0: #GP, start paging "
272 "in long mode while PAE is disabled\n");
c1a5d4f9 273 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 274 return;
275 }
276 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
277 if (cs_l) {
278 printk(KERN_DEBUG "set_cr0: #GP, start paging "
279 "in long mode while CS.L == 1\n");
c1a5d4f9 280 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 281 return;
282
283 }
284 } else
285#endif
ad312c7c 286 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
a03490ed
CO		 287 printk(KERN_DEBUG "set_cr0: #GP, pdptrs "
288 "reserved bits\n");
c1a5d4f9 289 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 290 return;
291 }
292
293 }
294
295 kvm_x86_ops->set_cr0(vcpu, cr0);
ad312c7c 296 vcpu->arch.cr0 = cr0;
a03490ed 297
a03490ed 298 kvm_mmu_reset_context(vcpu);
a03490ed
CO		 299 return;
300}
2d3ad1f4 301EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 302
2d3ad1f4 303void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 304{
2d3ad1f4 305 kvm_set_cr0(vcpu, (vcpu->arch.cr0 & ~0x0ful) | (msw & 0x0f));
a03490ed 306}
2d3ad1f4 307EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 308
2d3ad1f4 309void kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed
CO		 310{
311 if (cr4 & CR4_RESERVED_BITS) {
312 printk(KERN_DEBUG "set_cr4: #GP, reserved bits\n");
c1a5d4f9 313 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 314 return;
315 }
316
317 if (is_long_mode(vcpu)) {
318 if (!(cr4 & X86_CR4_PAE)) {
319 printk(KERN_DEBUG "set_cr4: #GP, clearing PAE while "
320 "in long mode\n");
c1a5d4f9 321 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 322 return;
323 }
324 } else if (is_paging(vcpu) && !is_pae(vcpu) && (cr4 & X86_CR4_PAE)
ad312c7c 325 && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
a03490ed 326 printk(KERN_DEBUG "set_cr4: #GP, pdptrs reserved bits\n");
c1a5d4f9 327 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 328 return;
329 }
330
331 if (cr4 & X86_CR4_VMXE) {
332 printk(KERN_DEBUG "set_cr4: #GP, setting VMXE\n");
c1a5d4f9 333 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 334 return;
335 }
336 kvm_x86_ops->set_cr4(vcpu, cr4);
ad312c7c 337 vcpu->arch.cr4 = cr4;
a03490ed 338 kvm_mmu_reset_context(vcpu);
a03490ed 339}
2d3ad1f4 340EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 341
2d3ad1f4 342void kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 343{
ad312c7c 344 if (cr3 == vcpu->arch.cr3 && !pdptrs_changed(vcpu)) {
d835dfec
AK		 345 kvm_mmu_flush_tlb(vcpu);
346 return;
347 }
348
a03490ed
CO		 349 if (is_long_mode(vcpu)) {
350 if (cr3 & CR3_L_MODE_RESERVED_BITS) {
351 printk(KERN_DEBUG "set_cr3: #GP, reserved bits\n");
c1a5d4f9 352 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 353 return;
354 }
355 } else {
356 if (is_pae(vcpu)) {
357 if (cr3 & CR3_PAE_RESERVED_BITS) {
358 printk(KERN_DEBUG
359 "set_cr3: #GP, reserved bits\n");
c1a5d4f9 360 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 361 return;
362 }
363 if (is_paging(vcpu) && !load_pdptrs(vcpu, cr3)) {
364 printk(KERN_DEBUG "set_cr3: #GP, pdptrs "
365 "reserved bits\n");
c1a5d4f9 366 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 367 return;
368 }
369 }
370 /*
371 * We don't check reserved bits in nonpae mode, because
372 * this isn't enforced, and VMware depends on this.
373 */
374 }
375
a03490ed
CO		 376 /*
377 * Does the new cr3 value map to physical memory? (Note, we
378 * catch an invalid cr3 even in real-mode, because it would
379 * cause trouble later on when we turn on paging anyway.)
380 *
381 * A real CPU would silently accept an invalid cr3 and would
382 * attempt to use it - with largely undefined (and often hard
383 * to debug) behavior on the guest side.
384 */
385 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
c1a5d4f9 386 kvm_inject_gp(vcpu, 0);
a03490ed 387 else {
ad312c7c
ZX		 388 vcpu->arch.cr3 = cr3;
389 vcpu->arch.mmu.new_cr3(vcpu);
a03490ed 390 }
a03490ed 391}
2d3ad1f4 392EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 393
2d3ad1f4 394void kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed
CO		 395{
396 if (cr8 & CR8_RESERVED_BITS) {
397 printk(KERN_DEBUG "set_cr8: #GP, reserved bits 0x%lx\n", cr8);
c1a5d4f9 398 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 399 return;
400 }
401 if (irqchip_in_kernel(vcpu->kvm))
402 kvm_lapic_set_tpr(vcpu, cr8);
403 else
ad312c7c 404 vcpu->arch.cr8 = cr8;
a03490ed 405}
2d3ad1f4 406EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 407
2d3ad1f4 408unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 409{
410 if (irqchip_in_kernel(vcpu->kvm))
411 return kvm_lapic_get_cr8(vcpu);
412 else
ad312c7c 413 return vcpu->arch.cr8;
a03490ed 414}
2d3ad1f4 415EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 416
043405e1
CO		 417/*
418 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
419 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
420 *
421 * This list is modified at module load time to reflect the
422 * capabilities of the host cpu.
423 */
424static u32 msrs_to_save[] = {
425 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
426 MSR_K6_STAR,
427#ifdef CONFIG_X86_64
428 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
429#endif
18068523 430 MSR_IA32_TIME_STAMP_COUNTER, MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
847f0ad8 431 MSR_IA32_PERF_STATUS,
043405e1
CO		 432};
433
434static unsigned num_msrs_to_save;
435
436static u32 emulated_msrs[] = {
437 MSR_IA32_MISC_ENABLE,
438};
439
15c4a640
CO		 440static void set_efer(struct kvm_vcpu *vcpu, u64 efer)
441{
f2b4b7dd 442 if (efer & efer_reserved_bits) {
15c4a640
CO		 443 printk(KERN_DEBUG "set_efer: 0x%llx #GP, reserved bits\n",
444 efer);
c1a5d4f9 445 kvm_inject_gp(vcpu, 0);
15c4a640
CO		 446 return;
447 }
448
449 if (is_paging(vcpu)
ad312c7c 450 && (vcpu->arch.shadow_efer & EFER_LME) != (efer & EFER_LME)) {
15c4a640 451 printk(KERN_DEBUG "set_efer: #GP, change LME while paging\n");
c1a5d4f9 452 kvm_inject_gp(vcpu, 0);
15c4a640
CO		 453 return;
454 }
455
456 kvm_x86_ops->set_efer(vcpu, efer);
457
458 efer &= ~EFER_LMA;
ad312c7c 459 efer |= vcpu->arch.shadow_efer & EFER_LMA;
15c4a640 460
ad312c7c 461 vcpu->arch.shadow_efer = efer;
15c4a640
CO		 462}
463
f2b4b7dd
JR		 464void kvm_enable_efer_bits(u64 mask)
465{
466 efer_reserved_bits &= ~mask;
467}
468EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
469
470
15c4a640
CO		 471/*
472 * Writes msr value into into the appropriate "register".
473 * Returns 0 on success, non-0 otherwise.
474 * Assumes vcpu_load() was already called.
475 */
476int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
477{
478 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
479}
480
313a3dc7
CO		 481/*
482 * Adapt set_msr() to msr_io()'s calling convention
483 */
484static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
485{
486 return kvm_set_msr(vcpu, index, *data);
487}
488
18068523
GOC		 489static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
490{
491 static int version;
492 struct kvm_wall_clock wc;
493 struct timespec wc_ts;
494
495 if (!wall_clock)
496 return;
497
498 version++;
499
18068523
GOC		 500 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
501
502 wc_ts = current_kernel_time();
503 wc.wc_sec = wc_ts.tv_sec;
504 wc.wc_nsec = wc_ts.tv_nsec;
505 wc.wc_version = version;
506
507 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
508
509 version++;
510 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 511}
512
513static void kvm_write_guest_time(struct kvm_vcpu *v)
514{
515 struct timespec ts;
516 unsigned long flags;
517 struct kvm_vcpu_arch *vcpu = &v->arch;
518 void *shared_kaddr;
519
520 if ((!vcpu->time_page))
521 return;
522
523 /* Keep irq disabled to prevent changes to the clock */
524 local_irq_save(flags);
525 kvm_get_msr(v, MSR_IA32_TIME_STAMP_COUNTER,
526 &vcpu->hv_clock.tsc_timestamp);
527 ktime_get_ts(&ts);
528 local_irq_restore(flags);
529
530 /* With all the info we got, fill in the values */
531
532 vcpu->hv_clock.system_time = ts.tv_nsec +
533 (NSEC_PER_SEC * (u64)ts.tv_sec);
534 /*
535 * The interface expects us to write an even number signaling that the
536 * update is finished. Since the guest won't see the intermediate
537 * state, we just write "2" at the end
538 */
539 vcpu->hv_clock.version = 2;
540
541 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
542
543 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
544 sizeof(vcpu->hv_clock));
545
546 kunmap_atomic(shared_kaddr, KM_USER0);
547
548 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
549}
550
15c4a640
CO		 551
552int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
553{
554 switch (msr) {
15c4a640
CO		 555 case MSR_EFER:
556 set_efer(vcpu, data);
557 break;
15c4a640
CO		 558 case MSR_IA32_MC0_STATUS:
559 pr_unimpl(vcpu, "%s: MSR_IA32_MC0_STATUS 0x%llx, nop\n",
b8688d51 560 __func__, data);
15c4a640
CO		 561 break;
562 case MSR_IA32_MCG_STATUS:
563 pr_unimpl(vcpu, "%s: MSR_IA32_MCG_STATUS 0x%llx, nop\n",
b8688d51 564 __func__, data);
15c4a640 565 break;
c7ac679c
JR		 566 case MSR_IA32_MCG_CTL:
567 pr_unimpl(vcpu, "%s: MSR_IA32_MCG_CTL 0x%llx, nop\n",
b8688d51 568 __func__, data);
c7ac679c 569 break;
15c4a640
CO		 570 case MSR_IA32_UCODE_REV:
571 case MSR_IA32_UCODE_WRITE:
572 case 0x200 ... 0x2ff: /* MTRRs */
573 break;
574 case MSR_IA32_APICBASE:
575 kvm_set_apic_base(vcpu, data);
576 break;
577 case MSR_IA32_MISC_ENABLE:
ad312c7c 578 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 579 break;
18068523
GOC		 580 case MSR_KVM_WALL_CLOCK:
581 vcpu->kvm->arch.wall_clock = data;
582 kvm_write_wall_clock(vcpu->kvm, data);
583 break;
584 case MSR_KVM_SYSTEM_TIME: {
585 if (vcpu->arch.time_page) {
586 kvm_release_page_dirty(vcpu->arch.time_page);
587 vcpu->arch.time_page = NULL;
588 }
589
590 vcpu->arch.time = data;
591
592 /* we verify if the enable bit is set... */
593 if (!(data & 1))
594 break;
595
596 /* ...but clean it before doing the actual write */
597 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
598
599 vcpu->arch.hv_clock.tsc_to_system_mul =
600 clocksource_khz2mult(tsc_khz, 22);
601 vcpu->arch.hv_clock.tsc_shift = 22;
602
603 down_read(&current->mm->mmap_sem);
18068523
GOC		 604 vcpu->arch.time_page =
605 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523
GOC		 606 up_read(&current->mm->mmap_sem);
607
608 if (is_error_page(vcpu->arch.time_page)) {
609 kvm_release_page_clean(vcpu->arch.time_page);
610 vcpu->arch.time_page = NULL;
611 }
612
613 kvm_write_guest_time(vcpu);
614 break;
615 }
15c4a640 616 default:
565f1fbd 617 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n", msr, data);
15c4a640
CO		 618 return 1;
619 }
620 return 0;
621}
622EXPORT_SYMBOL_GPL(kvm_set_msr_common);
623
624
625/*
626 * Reads an msr value (of 'msr_index') into 'pdata'.
627 * Returns 0 on success, non-0 otherwise.
628 * Assumes vcpu_load() was already called.
629 */
630int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
631{
632 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
633}
634
635int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
636{
637 u64 data;
638
639 switch (msr) {
640 case 0xc0010010: /* SYSCFG */
641 case 0xc0010015: /* HWCR */
642 case MSR_IA32_PLATFORM_ID:
643 case MSR_IA32_P5_MC_ADDR:
644 case MSR_IA32_P5_MC_TYPE:
645 case MSR_IA32_MC0_CTL:
646 case MSR_IA32_MCG_STATUS:
647 case MSR_IA32_MCG_CAP:
c7ac679c 648 case MSR_IA32_MCG_CTL:
15c4a640
CO		 649 case MSR_IA32_MC0_MISC:
650 case MSR_IA32_MC0_MISC+4:
651 case MSR_IA32_MC0_MISC+8:
652 case MSR_IA32_MC0_MISC+12:
653 case MSR_IA32_MC0_MISC+16:
654 case MSR_IA32_UCODE_REV:
15c4a640
CO		 655 case MSR_IA32_EBL_CR_POWERON:
656 /* MTRR registers */
657 case 0xfe:
658 case 0x200 ... 0x2ff:
659 data = 0;
660 break;
661 case 0xcd: /* fsb frequency */
662 data = 3;
663 break;
664 case MSR_IA32_APICBASE:
665 data = kvm_get_apic_base(vcpu);
666 break;
667 case MSR_IA32_MISC_ENABLE:
ad312c7c 668 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 669 break;
847f0ad8
AG		 670 case MSR_IA32_PERF_STATUS:
671 /* TSC increment by tick */
672 data = 1000ULL;
673 /* CPU multiplier */
674 data |= (((uint64_t)4ULL) << 40);
675 break;
15c4a640 676 case MSR_EFER:
ad312c7c 677 data = vcpu->arch.shadow_efer;
15c4a640 678 break;
18068523
GOC		 679 case MSR_KVM_WALL_CLOCK:
680 data = vcpu->kvm->arch.wall_clock;
681 break;
682 case MSR_KVM_SYSTEM_TIME:
683 data = vcpu->arch.time;
684 break;
15c4a640
CO		 685 default:
686 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
687 return 1;
688 }
689 *pdata = data;
690 return 0;
691}
692EXPORT_SYMBOL_GPL(kvm_get_msr_common);
693
313a3dc7
CO		 694/*
695 * Read or write a bunch of msrs. All parameters are kernel addresses.
696 *
697 * @return number of msrs set successfully.
698 */
699static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
700 struct kvm_msr_entry *entries,
701 int (*do_msr)(struct kvm_vcpu *vcpu,
702 unsigned index, u64 *data))
703{
704 int i;
705
706 vcpu_load(vcpu);
707
3200f405 708 down_read(&vcpu->kvm->slots_lock);
313a3dc7
CO		 709 for (i = 0; i < msrs->nmsrs; ++i)
710 if (do_msr(vcpu, entries[i].index, &entries[i].data))
711 break;
3200f405 712 up_read(&vcpu->kvm->slots_lock);
313a3dc7
CO		 713
714 vcpu_put(vcpu);
715
716 return i;
717}
718
719/*
720 * Read or write a bunch of msrs. Parameters are user addresses.
721 *
722 * @return number of msrs set successfully.
723 */
724static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
725 int (*do_msr)(struct kvm_vcpu *vcpu,
726 unsigned index, u64 *data),
727 int writeback)
728{
729 struct kvm_msrs msrs;
730 struct kvm_msr_entry *entries;
731 int r, n;
732 unsigned size;
733
734 r = -EFAULT;
735 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
736 goto out;
737
738 r = -E2BIG;
739 if (msrs.nmsrs >= MAX_IO_MSRS)
740 goto out;
741
742 r = -ENOMEM;
743 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
744 entries = vmalloc(size);
745 if (!entries)
746 goto out;
747
748 r = -EFAULT;
749 if (copy_from_user(entries, user_msrs->entries, size))
750 goto out_free;
751
752 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
753 if (r < 0)
754 goto out_free;
755
756 r = -EFAULT;
757 if (writeback && copy_to_user(user_msrs->entries, entries, size))
758 goto out_free;
759
760 r = n;
761
762out_free:
763 vfree(entries);
764out:
765 return r;
766}
767
e9b11c17
ZX		 768/*
769 * Make sure that a cpu that is being hot-unplugged does not have any vcpus
770 * cached on it.
771 */
772void decache_vcpus_on_cpu(int cpu)
773{
774 struct kvm *vm;
775 struct kvm_vcpu *vcpu;
776 int i;
777
778 spin_lock(&kvm_lock);
779 list_for_each_entry(vm, &vm_list, vm_list)
780 for (i = 0; i < KVM_MAX_VCPUS; ++i) {
781 vcpu = vm->vcpus[i];
782 if (!vcpu)
783 continue;
784 /*
785 * If the vcpu is locked, then it is running on some
786 * other cpu and therefore it is not cached on the
787 * cpu in question.
788 *
789 * If it's not locked, check the last cpu it executed
790 * on.
791 */
792 if (mutex_trylock(&vcpu->mutex)) {
793 if (vcpu->cpu == cpu) {
794 kvm_x86_ops->vcpu_decache(vcpu);
795 vcpu->cpu = -1;
796 }
797 mutex_unlock(&vcpu->mutex);
798 }
799 }
800 spin_unlock(&kvm_lock);
801}
802
018d00d2
ZX		 803int kvm_dev_ioctl_check_extension(long ext)
804{
805 int r;
806
807 switch (ext) {
808 case KVM_CAP_IRQCHIP:
809 case KVM_CAP_HLT:
810 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
811 case KVM_CAP_USER_MEMORY:
812 case KVM_CAP_SET_TSS_ADDR:
07716717 813 case KVM_CAP_EXT_CPUID:
18068523 814 case KVM_CAP_CLOCKSOURCE:
7837699f 815 case KVM_CAP_PIT:
a28e4f5a 816 case KVM_CAP_NOP_IO_DELAY:
018d00d2
ZX		 817 r = 1;
818 break;
774ead3a
AK		 819 case KVM_CAP_VAPIC:
820 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
821 break;
f725230a
AK		 822 case KVM_CAP_NR_VCPUS:
823 r = KVM_MAX_VCPUS;
824 break;
a988b910
AK		 825 case KVM_CAP_NR_MEMSLOTS:
826 r = KVM_MEMORY_SLOTS;
827 break;
2f333bcb
MT		 828 case KVM_CAP_PV_MMU:
829 r = !tdp_enabled;
830 break;
018d00d2
ZX		 831 default:
832 r = 0;
833 break;
834 }
835 return r;
836
837}
838
043405e1
CO		 839long kvm_arch_dev_ioctl(struct file *filp,
840 unsigned int ioctl, unsigned long arg)
841{
842 void __user *argp = (void __user *)arg;
843 long r;
844
845 switch (ioctl) {
846 case KVM_GET_MSR_INDEX_LIST: {
847 struct kvm_msr_list __user *user_msr_list = argp;
848 struct kvm_msr_list msr_list;
849 unsigned n;
850
851 r = -EFAULT;
852 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
853 goto out;
854 n = msr_list.nmsrs;
855 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
856 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
857 goto out;
858 r = -E2BIG;
859 if (n < num_msrs_to_save)
860 goto out;
861 r = -EFAULT;
862 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
863 num_msrs_to_save * sizeof(u32)))
864 goto out;
865 if (copy_to_user(user_msr_list->indices
866 + num_msrs_to_save * sizeof(u32),
867 &emulated_msrs,
868 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
869 goto out;
870 r = 0;
871 break;
872 }
674eea0f
AK		 873 case KVM_GET_SUPPORTED_CPUID: {
874 struct kvm_cpuid2 __user *cpuid_arg = argp;
875 struct kvm_cpuid2 cpuid;
876
877 r = -EFAULT;
878 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
879 goto out;
880 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
881 cpuid_arg->entries);
882 if (r)
883 goto out;
884
885 r = -EFAULT;
886 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
887 goto out;
888 r = 0;
889 break;
890 }
043405e1
CO		 891 default:
892 r = -EINVAL;
893 }
894out:
895 return r;
896}
897
313a3dc7
CO		 898void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
899{
900 kvm_x86_ops->vcpu_load(vcpu, cpu);
18068523 901 kvm_write_guest_time(vcpu);
313a3dc7
CO		 902}
903
904void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
905{
906 kvm_x86_ops->vcpu_put(vcpu);
9327fd11 907 kvm_put_guest_fpu(vcpu);
313a3dc7
CO		 908}
909
07716717 910static int is_efer_nx(void)
313a3dc7
CO		 911{
912 u64 efer;
313a3dc7
CO		 913
914 rdmsrl(MSR_EFER, efer);
07716717
DK		 915 return efer & EFER_NX;
916}
917
918static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
919{
920 int i;
921 struct kvm_cpuid_entry2 *e, *entry;
922
313a3dc7 923 entry = NULL;
ad312c7c
ZX		 924 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
925 e = &vcpu->arch.cpuid_entries[i];
313a3dc7
CO		 926 if (e->function == 0x80000001) {
927 entry = e;
928 break;
929 }
930 }
07716717 931 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
313a3dc7
CO		 932 entry->edx &= ~(1 << 20);
933 printk(KERN_INFO "kvm: guest NX capability removed\n");
934 }
935}
936
07716717 937/* when an old userspace process fills a new kernel module */
313a3dc7
CO		 938static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
939 struct kvm_cpuid *cpuid,
940 struct kvm_cpuid_entry __user *entries)
07716717
DK		 941{
942 int r, i;
943 struct kvm_cpuid_entry *cpuid_entries;
944
945 r = -E2BIG;
946 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
947 goto out;
948 r = -ENOMEM;
949 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
950 if (!cpuid_entries)
951 goto out;
952 r = -EFAULT;
953 if (copy_from_user(cpuid_entries, entries,
954 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
955 goto out_free;
956 for (i = 0; i < cpuid->nent; i++) {
ad312c7c
ZX		 957 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
958 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
959 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
960 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
961 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
962 vcpu->arch.cpuid_entries[i].index = 0;
963 vcpu->arch.cpuid_entries[i].flags = 0;
964 vcpu->arch.cpuid_entries[i].padding[0] = 0;
965 vcpu->arch.cpuid_entries[i].padding[1] = 0;
966 vcpu->arch.cpuid_entries[i].padding[2] = 0;
967 }
968 vcpu->arch.cpuid_nent = cpuid->nent;
07716717
DK		 969 cpuid_fix_nx_cap(vcpu);
970 r = 0;
971
972out_free:
973 vfree(cpuid_entries);
974out:
975 return r;
976}
977
978static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
979 struct kvm_cpuid2 *cpuid,
980 struct kvm_cpuid_entry2 __user *entries)
313a3dc7
CO		 981{
982 int r;
983
984 r = -E2BIG;
985 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
986 goto out;
987 r = -EFAULT;
ad312c7c 988 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
07716717 989 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
313a3dc7 990 goto out;
ad312c7c 991 vcpu->arch.cpuid_nent = cpuid->nent;
313a3dc7
CO		 992 return 0;
993
994out:
995 return r;
996}
997
07716717
DK		 998static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
999 struct kvm_cpuid2 *cpuid,
1000 struct kvm_cpuid_entry2 __user *entries)
1001{
1002 int r;
1003
1004 r = -E2BIG;
ad312c7c 1005 if (cpuid->nent < vcpu->arch.cpuid_nent)
07716717
DK		 1006 goto out;
1007 r = -EFAULT;
ad312c7c
ZX		 1008 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
1009 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 1010 goto out;
1011 return 0;
1012
1013out:
ad312c7c 1014 cpuid->nent = vcpu->arch.cpuid_nent;
07716717
DK		 1015 return r;
1016}
1017
1018static inline u32 bit(int bitno)
1019{
1020 return 1 << (bitno & 31);
1021}
1022
1023static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
1024 u32 index)
1025{
1026 entry->function = function;
1027 entry->index = index;
1028 cpuid_count(entry->function, entry->index,
1029 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
1030 entry->flags = 0;
1031}
1032
1033static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
1034 u32 index, int *nent, int maxnent)
1035{
1036 const u32 kvm_supported_word0_x86_features = bit(X86_FEATURE_FPU) |
1037 bit(X86_FEATURE_VME) | bit(X86_FEATURE_DE) |
1038 bit(X86_FEATURE_PSE) | bit(X86_FEATURE_TSC) |
1039 bit(X86_FEATURE_MSR) | bit(X86_FEATURE_PAE) |
1040 bit(X86_FEATURE_CX8) | bit(X86_FEATURE_APIC) |
1041 bit(X86_FEATURE_SEP) | bit(X86_FEATURE_PGE) |
1042 bit(X86_FEATURE_CMOV) | bit(X86_FEATURE_PSE36) |
1043 bit(X86_FEATURE_CLFLSH) | bit(X86_FEATURE_MMX) |
1044 bit(X86_FEATURE_FXSR) | bit(X86_FEATURE_XMM) |
1045 bit(X86_FEATURE_XMM2) | bit(X86_FEATURE_SELFSNOOP);
1046 const u32 kvm_supported_word1_x86_features = bit(X86_FEATURE_FPU) |
1047 bit(X86_FEATURE_VME) | bit(X86_FEATURE_DE) |
1048 bit(X86_FEATURE_PSE) | bit(X86_FEATURE_TSC) |
1049 bit(X86_FEATURE_MSR) | bit(X86_FEATURE_PAE) |
1050 bit(X86_FEATURE_CX8) | bit(X86_FEATURE_APIC) |
1051 bit(X86_FEATURE_PGE) |
1052 bit(X86_FEATURE_CMOV) | bit(X86_FEATURE_PSE36) |
1053 bit(X86_FEATURE_MMX) | bit(X86_FEATURE_FXSR) |
1054 bit(X86_FEATURE_SYSCALL) |
1055 (bit(X86_FEATURE_NX) && is_efer_nx()) |
1056#ifdef CONFIG_X86_64
1057 bit(X86_FEATURE_LM) |
1058#endif
1059 bit(X86_FEATURE_MMXEXT) |
1060 bit(X86_FEATURE_3DNOWEXT) |
1061 bit(X86_FEATURE_3DNOW);
1062 const u32 kvm_supported_word3_x86_features =
1063 bit(X86_FEATURE_XMM3) | bit(X86_FEATURE_CX16);
1064 const u32 kvm_supported_word6_x86_features =
1065 bit(X86_FEATURE_LAHF_LM) | bit(X86_FEATURE_CMP_LEGACY);
1066
1067 /* all func 2 cpuid_count() should be called on the same cpu */
1068 get_cpu();
1069 do_cpuid_1_ent(entry, function, index);
1070 ++*nent;
1071
1072 switch (function) {
1073 case 0:
1074 entry->eax = min(entry->eax, (u32)0xb);
1075 break;
1076 case 1:
1077 entry->edx &= kvm_supported_word0_x86_features;
1078 entry->ecx &= kvm_supported_word3_x86_features;
1079 break;
1080 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
1081 * may return different values. This forces us to get_cpu() before
1082 * issuing the first command, and also to emulate this annoying behavior
1083 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
1084 case 2: {
1085 int t, times = entry->eax & 0xff;
1086
1087 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
1088 for (t = 1; t < times && *nent < maxnent; ++t) {
1089 do_cpuid_1_ent(&entry[t], function, 0);
1090 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
1091 ++*nent;
1092 }
1093 break;
1094 }
1095 /* function 4 and 0xb have additional index. */
1096 case 4: {
14af3f3c 1097 int i, cache_type;
07716717
DK		 1098
1099 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1100 /* read more entries until cache_type is zero */
14af3f3c
HH		 1101 for (i = 1; *nent < maxnent; ++i) {
1102 cache_type = entry[i - 1].eax & 0x1f;
07716717
DK		 1103 if (!cache_type)
1104 break;
14af3f3c
HH		 1105 do_cpuid_1_ent(&entry[i], function, i);
1106 entry[i].flags |=
07716717
DK		 1107 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1108 ++*nent;
1109 }
1110 break;
1111 }
1112 case 0xb: {
14af3f3c 1113 int i, level_type;
07716717
DK		 1114
1115 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1116 /* read more entries until level_type is zero */
14af3f3c
HH		 1117 for (i = 1; *nent < maxnent; ++i) {
1118 level_type = entry[i - 1].ecx & 0xff;
07716717
DK		 1119 if (!level_type)
1120 break;
14af3f3c
HH		 1121 do_cpuid_1_ent(&entry[i], function, i);
1122 entry[i].flags |=
07716717
DK		 1123 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1124 ++*nent;
1125 }
1126 break;
1127 }
1128 case 0x80000000:
1129 entry->eax = min(entry->eax, 0x8000001a);
1130 break;
1131 case 0x80000001:
1132 entry->edx &= kvm_supported_word1_x86_features;
1133 entry->ecx &= kvm_supported_word6_x86_features;
1134 break;
1135 }
1136 put_cpu();
1137}
1138
674eea0f 1139static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
07716717
DK		 1140 struct kvm_cpuid_entry2 __user *entries)
1141{
1142 struct kvm_cpuid_entry2 *cpuid_entries;
1143 int limit, nent = 0, r = -E2BIG;
1144 u32 func;
1145
1146 if (cpuid->nent < 1)
1147 goto out;
1148 r = -ENOMEM;
1149 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
1150 if (!cpuid_entries)
1151 goto out;
1152
1153 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
1154 limit = cpuid_entries[0].eax;
1155 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
1156 do_cpuid_ent(&cpuid_entries[nent], func, 0,
1157 &nent, cpuid->nent);
1158 r = -E2BIG;
1159 if (nent >= cpuid->nent)
1160 goto out_free;
1161
1162 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
1163 limit = cpuid_entries[nent - 1].eax;
1164 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
1165 do_cpuid_ent(&cpuid_entries[nent], func, 0,
1166 &nent, cpuid->nent);
1167 r = -EFAULT;
1168 if (copy_to_user(entries, cpuid_entries,
1169 nent * sizeof(struct kvm_cpuid_entry2)))
1170 goto out_free;
1171 cpuid->nent = nent;
1172 r = 0;
1173
1174out_free:
1175 vfree(cpuid_entries);
1176out:
1177 return r;
1178}
1179
313a3dc7
CO		 1180static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
1181 struct kvm_lapic_state *s)
1182{
1183 vcpu_load(vcpu);
ad312c7c 1184 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 1185 vcpu_put(vcpu);
1186
1187 return 0;
1188}
1189
1190static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
1191 struct kvm_lapic_state *s)
1192{
1193 vcpu_load(vcpu);
ad312c7c 1194 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7
CO		 1195 kvm_apic_post_state_restore(vcpu);
1196 vcpu_put(vcpu);
1197
1198 return 0;
1199}
1200
f77bc6a4
ZX		 1201static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
1202 struct kvm_interrupt *irq)
1203{
1204 if (irq->irq < 0 || irq->irq >= 256)
1205 return -EINVAL;
1206 if (irqchip_in_kernel(vcpu->kvm))
1207 return -ENXIO;
1208 vcpu_load(vcpu);
1209
ad312c7c
ZX		 1210 set_bit(irq->irq, vcpu->arch.irq_pending);
1211 set_bit(irq->irq / BITS_PER_LONG, &vcpu->arch.irq_summary);
f77bc6a4
ZX		 1212
1213 vcpu_put(vcpu);
1214
1215 return 0;
1216}
1217
b209749f
AK		 1218static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
1219 struct kvm_tpr_access_ctl *tac)
1220{
1221 if (tac->flags)
1222 return -EINVAL;
1223 vcpu->arch.tpr_access_reporting = !!tac->enabled;
1224 return 0;
1225}
1226
313a3dc7
CO		 1227long kvm_arch_vcpu_ioctl(struct file *filp,
1228 unsigned int ioctl, unsigned long arg)
1229{
1230 struct kvm_vcpu *vcpu = filp->private_data;
1231 void __user *argp = (void __user *)arg;
1232 int r;
1233
1234 switch (ioctl) {
1235 case KVM_GET_LAPIC: {
1236 struct kvm_lapic_state lapic;
1237
1238 memset(&lapic, 0, sizeof lapic);
1239 r = kvm_vcpu_ioctl_get_lapic(vcpu, &lapic);
1240 if (r)
1241 goto out;
1242 r = -EFAULT;
1243 if (copy_to_user(argp, &lapic, sizeof lapic))
1244 goto out;
1245 r = 0;
1246 break;
1247 }
1248 case KVM_SET_LAPIC: {
1249 struct kvm_lapic_state lapic;
1250
1251 r = -EFAULT;
1252 if (copy_from_user(&lapic, argp, sizeof lapic))
1253 goto out;
1254 r = kvm_vcpu_ioctl_set_lapic(vcpu, &lapic);;
1255 if (r)
1256 goto out;
1257 r = 0;
1258 break;
1259 }
f77bc6a4
ZX		 1260 case KVM_INTERRUPT: {
1261 struct kvm_interrupt irq;
1262
1263 r = -EFAULT;
1264 if (copy_from_user(&irq, argp, sizeof irq))
1265 goto out;
1266 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
1267 if (r)
1268 goto out;
1269 r = 0;
1270 break;
1271 }
313a3dc7
CO		 1272 case KVM_SET_CPUID: {
1273 struct kvm_cpuid __user *cpuid_arg = argp;
1274 struct kvm_cpuid cpuid;
1275
1276 r = -EFAULT;
1277 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1278 goto out;
1279 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
1280 if (r)
1281 goto out;
1282 break;
1283 }
07716717
DK		 1284 case KVM_SET_CPUID2: {
1285 struct kvm_cpuid2 __user *cpuid_arg = argp;
1286 struct kvm_cpuid2 cpuid;
1287
1288 r = -EFAULT;
1289 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1290 goto out;
1291 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
1292 cpuid_arg->entries);
1293 if (r)
1294 goto out;
1295 break;
1296 }
1297 case KVM_GET_CPUID2: {
1298 struct kvm_cpuid2 __user *cpuid_arg = argp;
1299 struct kvm_cpuid2 cpuid;
1300
1301 r = -EFAULT;
1302 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1303 goto out;
1304 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
1305 cpuid_arg->entries);
1306 if (r)
1307 goto out;
1308 r = -EFAULT;
1309 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1310 goto out;
1311 r = 0;
1312 break;
1313 }
313a3dc7
CO		 1314 case KVM_GET_MSRS:
1315 r = msr_io(vcpu, argp, kvm_get_msr, 1);
1316 break;
1317 case KVM_SET_MSRS:
1318 r = msr_io(vcpu, argp, do_set_msr, 0);
1319 break;
b209749f
AK		 1320 case KVM_TPR_ACCESS_REPORTING: {
1321 struct kvm_tpr_access_ctl tac;
1322
1323 r = -EFAULT;
1324 if (copy_from_user(&tac, argp, sizeof tac))
1325 goto out;
1326 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
1327 if (r)
1328 goto out;
1329 r = -EFAULT;
1330 if (copy_to_user(argp, &tac, sizeof tac))
1331 goto out;
1332 r = 0;
1333 break;
1334 };
b93463aa
AK		 1335 case KVM_SET_VAPIC_ADDR: {
1336 struct kvm_vapic_addr va;
1337
1338 r = -EINVAL;
1339 if (!irqchip_in_kernel(vcpu->kvm))
1340 goto out;
1341 r = -EFAULT;
1342 if (copy_from_user(&va, argp, sizeof va))
1343 goto out;
1344 r = 0;
1345 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
1346 break;
1347 }
313a3dc7
CO		 1348 default:
1349 r = -EINVAL;
1350 }
1351out:
1352 return r;
1353}
1354
1fe779f8
CO		 1355static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
1356{
1357 int ret;
1358
1359 if (addr > (unsigned int)(-3 * PAGE_SIZE))
1360 return -1;
1361 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
1362 return ret;
1363}
1364
1365static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
1366 u32 kvm_nr_mmu_pages)
1367{
1368 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
1369 return -EINVAL;
1370
72dc67a6 1371 down_write(&kvm->slots_lock);
1fe779f8
CO		 1372
1373 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 1374 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 1375
72dc67a6 1376 up_write(&kvm->slots_lock);
1fe779f8
CO		 1377 return 0;
1378}
1379
1380static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
1381{
f05e70ac 1382 return kvm->arch.n_alloc_mmu_pages;
1fe779f8
CO		 1383}
1384
e9f85cde
ZX		 1385gfn_t unalias_gfn(struct kvm *kvm, gfn_t gfn)
1386{
1387 int i;
1388 struct kvm_mem_alias *alias;
1389
d69fb81f
ZX		 1390 for (i = 0; i < kvm->arch.naliases; ++i) {
1391 alias = &kvm->arch.aliases[i];
e9f85cde
ZX		 1392 if (gfn >= alias->base_gfn
1393 && gfn < alias->base_gfn + alias->npages)
1394 return alias->target_gfn + gfn - alias->base_gfn;
1395 }
1396 return gfn;
1397}
1398
1fe779f8
CO		 1399/*
1400 * Set a new alias region. Aliases map a portion of physical memory into
1401 * another portion. This is useful for memory windows, for example the PC
1402 * VGA region.
1403 */
1404static int kvm_vm_ioctl_set_memory_alias(struct kvm *kvm,
1405 struct kvm_memory_alias *alias)
1406{
1407 int r, n;
1408 struct kvm_mem_alias *p;
1409
1410 r = -EINVAL;
1411 /* General sanity checks */
1412 if (alias->memory_size & (PAGE_SIZE - 1))
1413 goto out;
1414 if (alias->guest_phys_addr & (PAGE_SIZE - 1))
1415 goto out;
1416 if (alias->slot >= KVM_ALIAS_SLOTS)
1417 goto out;
1418 if (alias->guest_phys_addr + alias->memory_size
1419 < alias->guest_phys_addr)
1420 goto out;
1421 if (alias->target_phys_addr + alias->memory_size
1422 < alias->target_phys_addr)
1423 goto out;
1424
72dc67a6 1425 down_write(&kvm->slots_lock);
1fe779f8 1426
d69fb81f 1427 p = &kvm->arch.aliases[alias->slot];
1fe779f8
CO		 1428 p->base_gfn = alias->guest_phys_addr >> PAGE_SHIFT;
1429 p->npages = alias->memory_size >> PAGE_SHIFT;
1430 p->target_gfn = alias->target_phys_addr >> PAGE_SHIFT;
1431
1432 for (n = KVM_ALIAS_SLOTS; n > 0; --n)
d69fb81f 1433 if (kvm->arch.aliases[n - 1].npages)
1fe779f8 1434 break;
d69fb81f 1435 kvm->arch.naliases = n;
1fe779f8
CO		 1436
1437 kvm_mmu_zap_all(kvm);
1438
72dc67a6 1439 up_write(&kvm->slots_lock);
1fe779f8
CO		 1440
1441 return 0;
1442
1443out:
1444 return r;
1445}
1446
1447static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
1448{
1449 int r;
1450
1451 r = 0;
1452 switch (chip->chip_id) {
1453 case KVM_IRQCHIP_PIC_MASTER:
1454 memcpy(&chip->chip.pic,
1455 &pic_irqchip(kvm)->pics[0],
1456 sizeof(struct kvm_pic_state));
1457 break;
1458 case KVM_IRQCHIP_PIC_SLAVE:
1459 memcpy(&chip->chip.pic,
1460 &pic_irqchip(kvm)->pics[1],
1461 sizeof(struct kvm_pic_state));
1462 break;
1463 case KVM_IRQCHIP_IOAPIC:
1464 memcpy(&chip->chip.ioapic,
1465 ioapic_irqchip(kvm),
1466 sizeof(struct kvm_ioapic_state));
1467 break;
1468 default:
1469 r = -EINVAL;
1470 break;
1471 }
1472 return r;
1473}
1474
1475static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
1476{
1477 int r;
1478
1479 r = 0;
1480 switch (chip->chip_id) {
1481 case KVM_IRQCHIP_PIC_MASTER:
1482 memcpy(&pic_irqchip(kvm)->pics[0],
1483 &chip->chip.pic,
1484 sizeof(struct kvm_pic_state));
1485 break;
1486 case KVM_IRQCHIP_PIC_SLAVE:
1487 memcpy(&pic_irqchip(kvm)->pics[1],
1488 &chip->chip.pic,
1489 sizeof(struct kvm_pic_state));
1490 break;
1491 case KVM_IRQCHIP_IOAPIC:
1492 memcpy(ioapic_irqchip(kvm),
1493 &chip->chip.ioapic,
1494 sizeof(struct kvm_ioapic_state));
1495 break;
1496 default:
1497 r = -EINVAL;
1498 break;
1499 }
1500 kvm_pic_update_irq(pic_irqchip(kvm));
1501 return r;
1502}
1503
e0f63cb9
SY		 1504static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
1505{
1506 int r = 0;
1507
1508 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
1509 return r;
1510}
1511
1512static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
1513{
1514 int r = 0;
1515
1516 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
1517 kvm_pit_load_count(kvm, 0, ps->channels[0].count);
1518 return r;
1519}
1520
5bb064dc
ZX		 1521/*
1522 * Get (and clear) the dirty memory log for a memory slot.
1523 */
1524int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
1525 struct kvm_dirty_log *log)
1526{
1527 int r;
1528 int n;
1529 struct kvm_memory_slot *memslot;
1530 int is_dirty = 0;
1531
72dc67a6 1532 down_write(&kvm->slots_lock);
5bb064dc
ZX		 1533
1534 r = kvm_get_dirty_log(kvm, log, &is_dirty);
1535 if (r)
1536 goto out;
1537
1538 /* If nothing is dirty, don't bother messing with page tables. */
1539 if (is_dirty) {
1540 kvm_mmu_slot_remove_write_access(kvm, log->slot);
1541 kvm_flush_remote_tlbs(kvm);
1542 memslot = &kvm->memslots[log->slot];
1543 n = ALIGN(memslot->npages, BITS_PER_LONG) / 8;
1544 memset(memslot->dirty_bitmap, 0, n);
1545 }
1546 r = 0;
1547out:
72dc67a6 1548 up_write(&kvm->slots_lock);
5bb064dc
ZX		 1549 return r;
1550}
1551
1fe779f8
CO		 1552long kvm_arch_vm_ioctl(struct file *filp,
1553 unsigned int ioctl, unsigned long arg)
1554{
1555 struct kvm *kvm = filp->private_data;
1556 void __user *argp = (void __user *)arg;
1557 int r = -EINVAL;
1558
1559 switch (ioctl) {
1560 case KVM_SET_TSS_ADDR:
1561 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1562 if (r < 0)
1563 goto out;
1564 break;
1565 case KVM_SET_MEMORY_REGION: {
1566 struct kvm_memory_region kvm_mem;
1567 struct kvm_userspace_memory_region kvm_userspace_mem;
1568
1569 r = -EFAULT;
1570 if (copy_from_user(&kvm_mem, argp, sizeof kvm_mem))
1571 goto out;
1572 kvm_userspace_mem.slot = kvm_mem.slot;
1573 kvm_userspace_mem.flags = kvm_mem.flags;
1574 kvm_userspace_mem.guest_phys_addr = kvm_mem.guest_phys_addr;
1575 kvm_userspace_mem.memory_size = kvm_mem.memory_size;
1576 r = kvm_vm_ioctl_set_memory_region(kvm, &kvm_userspace_mem, 0);
1577 if (r)
1578 goto out;
1579 break;
1580 }
1581 case KVM_SET_NR_MMU_PAGES:
1582 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1583 if (r)
1584 goto out;
1585 break;
1586 case KVM_GET_NR_MMU_PAGES:
1587 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
1588 break;
1589 case KVM_SET_MEMORY_ALIAS: {
1590 struct kvm_memory_alias alias;
1591
1592 r = -EFAULT;
1593 if (copy_from_user(&alias, argp, sizeof alias))
1594 goto out;
1595 r = kvm_vm_ioctl_set_memory_alias(kvm, &alias);
1596 if (r)
1597 goto out;
1598 break;
1599 }
1600 case KVM_CREATE_IRQCHIP:
1601 r = -ENOMEM;
d7deeeb0
ZX		 1602 kvm->arch.vpic = kvm_create_pic(kvm);
1603 if (kvm->arch.vpic) {
1fe779f8
CO		 1604 r = kvm_ioapic_init(kvm);
1605 if (r) {
d7deeeb0
ZX		 1606 kfree(kvm->arch.vpic);
1607 kvm->arch.vpic = NULL;
1fe779f8
CO		 1608 goto out;
1609 }
1610 } else
1611 goto out;
1612 break;
7837699f
SY		 1613 case KVM_CREATE_PIT:
1614 r = -ENOMEM;
1615 kvm->arch.vpit = kvm_create_pit(kvm);
1616 if (kvm->arch.vpit)
1617 r = 0;
1618 break;
1fe779f8
CO		 1619 case KVM_IRQ_LINE: {
1620 struct kvm_irq_level irq_event;
1621
1622 r = -EFAULT;
1623 if (copy_from_user(&irq_event, argp, sizeof irq_event))
1624 goto out;
1625 if (irqchip_in_kernel(kvm)) {
1626 mutex_lock(&kvm->lock);
1627 if (irq_event.irq < 16)
1628 kvm_pic_set_irq(pic_irqchip(kvm),
1629 irq_event.irq,
1630 irq_event.level);
d7deeeb0 1631 kvm_ioapic_set_irq(kvm->arch.vioapic,
1fe779f8
CO		 1632 irq_event.irq,
1633 irq_event.level);
1634 mutex_unlock(&kvm->lock);
1635 r = 0;
1636 }
1637 break;
1638 }
1639 case KVM_GET_IRQCHIP: {
1640 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
1641 struct kvm_irqchip chip;
1642
1643 r = -EFAULT;
1644 if (copy_from_user(&chip, argp, sizeof chip))
1645 goto out;
1646 r = -ENXIO;
1647 if (!irqchip_in_kernel(kvm))
1648 goto out;
1649 r = kvm_vm_ioctl_get_irqchip(kvm, &chip);
1650 if (r)
1651 goto out;
1652 r = -EFAULT;
1653 if (copy_to_user(argp, &chip, sizeof chip))
1654 goto out;
1655 r = 0;
1656 break;
1657 }
1658 case KVM_SET_IRQCHIP: {
1659 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
1660 struct kvm_irqchip chip;
1661
1662 r = -EFAULT;
1663 if (copy_from_user(&chip, argp, sizeof chip))
1664 goto out;
1665 r = -ENXIO;
1666 if (!irqchip_in_kernel(kvm))
1667 goto out;
1668 r = kvm_vm_ioctl_set_irqchip(kvm, &chip);
1669 if (r)
1670 goto out;
1671 r = 0;
1672 break;
1673 }
e0f63cb9
SY		 1674 case KVM_GET_PIT: {
1675 struct kvm_pit_state ps;
1676 r = -EFAULT;
1677 if (copy_from_user(&ps, argp, sizeof ps))
1678 goto out;
1679 r = -ENXIO;
1680 if (!kvm->arch.vpit)
1681 goto out;
1682 r = kvm_vm_ioctl_get_pit(kvm, &ps);
1683 if (r)
1684 goto out;
1685 r = -EFAULT;
1686 if (copy_to_user(argp, &ps, sizeof ps))
1687 goto out;
1688 r = 0;
1689 break;
1690 }
1691 case KVM_SET_PIT: {
1692 struct kvm_pit_state ps;
1693 r = -EFAULT;
1694 if (copy_from_user(&ps, argp, sizeof ps))
1695 goto out;
1696 r = -ENXIO;
1697 if (!kvm->arch.vpit)
1698 goto out;
1699 r = kvm_vm_ioctl_set_pit(kvm, &ps);
1700 if (r)
1701 goto out;
1702 r = 0;
1703 break;
1704 }
1fe779f8
CO		 1705 default:
1706 ;
1707 }
1708out:
1709 return r;
1710}
1711
a16b043c 1712static void kvm_init_msr_list(void)
043405e1
CO		 1713{
1714 u32 dummy[2];
1715 unsigned i, j;
1716
1717 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
1718 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
1719 continue;
1720 if (j < i)
1721 msrs_to_save[j] = msrs_to_save[i];
1722 j++;
1723 }
1724 num_msrs_to_save = j;
1725}
1726
bbd9b64e
CO		 1727/*
1728 * Only apic need an MMIO device hook, so shortcut now..
1729 */
1730static struct kvm_io_device *vcpu_find_pervcpu_dev(struct kvm_vcpu *vcpu,
1731 gpa_t addr)
1732{
1733 struct kvm_io_device *dev;
1734
ad312c7c
ZX		 1735 if (vcpu->arch.apic) {
1736 dev = &vcpu->arch.apic->dev;
bbd9b64e
CO		 1737 if (dev->in_range(dev, addr))
1738 return dev;
1739 }
1740 return NULL;
1741}
1742
1743
1744static struct kvm_io_device *vcpu_find_mmio_dev(struct kvm_vcpu *vcpu,
1745 gpa_t addr)
1746{
1747 struct kvm_io_device *dev;
1748
1749 dev = vcpu_find_pervcpu_dev(vcpu, addr);
1750 if (dev == NULL)
1751 dev = kvm_io_bus_find_dev(&vcpu->kvm->mmio_bus, addr);
1752 return dev;
1753}
1754
1755int emulator_read_std(unsigned long addr,
1756 void *val,
1757 unsigned int bytes,
1758 struct kvm_vcpu *vcpu)
1759{
1760 void *data = val;
10589a46 1761 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 1762
1763 while (bytes) {
ad312c7c 1764 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e
CO		 1765 unsigned offset = addr & (PAGE_SIZE-1);
1766 unsigned tocopy = min(bytes, (unsigned)PAGE_SIZE - offset);
1767 int ret;
1768
10589a46
MT		 1769 if (gpa == UNMAPPED_GVA) {
1770 r = X86EMUL_PROPAGATE_FAULT;
1771 goto out;
1772 }
bbd9b64e 1773 ret = kvm_read_guest(vcpu->kvm, gpa, data, tocopy);
10589a46
MT		 1774 if (ret < 0) {
1775 r = X86EMUL_UNHANDLEABLE;
1776 goto out;
1777 }
bbd9b64e
CO		 1778
1779 bytes -= tocopy;
1780 data += tocopy;
1781 addr += tocopy;
1782 }
10589a46 1783out:
10589a46 1784 return r;
bbd9b64e
CO		 1785}
1786EXPORT_SYMBOL_GPL(emulator_read_std);
1787
bbd9b64e
CO		 1788static int emulator_read_emulated(unsigned long addr,
1789 void *val,
1790 unsigned int bytes,
1791 struct kvm_vcpu *vcpu)
1792{
1793 struct kvm_io_device *mmio_dev;
1794 gpa_t gpa;
1795
1796 if (vcpu->mmio_read_completed) {
1797 memcpy(val, vcpu->mmio_data, bytes);
1798 vcpu->mmio_read_completed = 0;
1799 return X86EMUL_CONTINUE;
1800 }
1801
ad312c7c 1802 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e
CO		 1803
1804 /* For APIC access vmexit */
1805 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
1806 goto mmio;
1807
1808 if (emulator_read_std(addr, val, bytes, vcpu)
1809 == X86EMUL_CONTINUE)
1810 return X86EMUL_CONTINUE;
1811 if (gpa == UNMAPPED_GVA)
1812 return X86EMUL_PROPAGATE_FAULT;
1813
1814mmio:
1815 /*
1816 * Is this MMIO handled locally?
1817 */
10589a46 1818 mutex_lock(&vcpu->kvm->lock);
bbd9b64e
CO		 1819 mmio_dev = vcpu_find_mmio_dev(vcpu, gpa);
1820 if (mmio_dev) {
1821 kvm_iodevice_read(mmio_dev, gpa, bytes, val);
10589a46 1822 mutex_unlock(&vcpu->kvm->lock);
bbd9b64e
CO		 1823 return X86EMUL_CONTINUE;
1824 }
10589a46 1825 mutex_unlock(&vcpu->kvm->lock);
bbd9b64e
CO		 1826
1827 vcpu->mmio_needed = 1;
1828 vcpu->mmio_phys_addr = gpa;
1829 vcpu->mmio_size = bytes;
1830 vcpu->mmio_is_write = 0;
1831
1832 return X86EMUL_UNHANDLEABLE;
1833}
1834
3200f405 1835int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
9f811285 1836 const void *val, int bytes)
bbd9b64e
CO		 1837{
1838 int ret;
1839
1840 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 1841 if (ret < 0)
bbd9b64e
CO		 1842 return 0;
1843 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
1844 return 1;
1845}
1846
1847static int emulator_write_emulated_onepage(unsigned long addr,
1848 const void *val,
1849 unsigned int bytes,
1850 struct kvm_vcpu *vcpu)
1851{
1852 struct kvm_io_device *mmio_dev;
10589a46
MT		 1853 gpa_t gpa;
1854
10589a46 1855 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e
CO		 1856
1857 if (gpa == UNMAPPED_GVA) {
c3c91fee 1858 kvm_inject_page_fault(vcpu, addr, 2);
bbd9b64e
CO		 1859 return X86EMUL_PROPAGATE_FAULT;
1860 }
1861
1862 /* For APIC access vmexit */
1863 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
1864 goto mmio;
1865
1866 if (emulator_write_phys(vcpu, gpa, val, bytes))
1867 return X86EMUL_CONTINUE;
1868
1869mmio:
1870 /*
1871 * Is this MMIO handled locally?
1872 */
10589a46 1873 mutex_lock(&vcpu->kvm->lock);
bbd9b64e
CO		 1874 mmio_dev = vcpu_find_mmio_dev(vcpu, gpa);
1875 if (mmio_dev) {
1876 kvm_iodevice_write(mmio_dev, gpa, bytes, val);
10589a46 1877 mutex_unlock(&vcpu->kvm->lock);
bbd9b64e
CO		 1878 return X86EMUL_CONTINUE;
1879 }
10589a46 1880 mutex_unlock(&vcpu->kvm->lock);
bbd9b64e
CO		 1881
1882 vcpu->mmio_needed = 1;
1883 vcpu->mmio_phys_addr = gpa;
1884 vcpu->mmio_size = bytes;
1885 vcpu->mmio_is_write = 1;
1886 memcpy(vcpu->mmio_data, val, bytes);
1887
1888 return X86EMUL_CONTINUE;
1889}
1890
1891int emulator_write_emulated(unsigned long addr,
1892 const void *val,
1893 unsigned int bytes,
1894 struct kvm_vcpu *vcpu)
1895{
1896 /* Crossing a page boundary? */
1897 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
1898 int rc, now;
1899
1900 now = -addr & ~PAGE_MASK;
1901 rc = emulator_write_emulated_onepage(addr, val, now, vcpu);
1902 if (rc != X86EMUL_CONTINUE)
1903 return rc;
1904 addr += now;
1905 val += now;
1906 bytes -= now;
1907 }
1908 return emulator_write_emulated_onepage(addr, val, bytes, vcpu);
1909}
1910EXPORT_SYMBOL_GPL(emulator_write_emulated);
1911
1912static int emulator_cmpxchg_emulated(unsigned long addr,
1913 const void *old,
1914 const void *new,
1915 unsigned int bytes,
1916 struct kvm_vcpu *vcpu)
1917{
1918 static int reported;
1919
1920 if (!reported) {
1921 reported = 1;
1922 printk(KERN_WARNING "kvm: emulating exchange as write\n");
1923 }
2bacc55c
MT		 1924#ifndef CONFIG_X86_64
1925 /* guests cmpxchg8b have to be emulated atomically */
1926 if (bytes == 8) {
10589a46 1927 gpa_t gpa;
2bacc55c 1928 struct page *page;
c0b49b0d 1929 char *kaddr;
2bacc55c
MT		 1930 u64 val;
1931
10589a46
MT		 1932 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
1933
2bacc55c
MT		 1934 if (gpa == UNMAPPED_GVA ||
1935 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
1936 goto emul_write;
1937
1938 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
1939 goto emul_write;
1940
1941 val = *(u64 *)new;
72dc67a6
IE		 1942
1943 down_read(&current->mm->mmap_sem);
2bacc55c 1944 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
72dc67a6
IE		 1945 up_read(&current->mm->mmap_sem);
1946
c0b49b0d
AM		 1947 kaddr = kmap_atomic(page, KM_USER0);
1948 set_64bit((u64 *)(kaddr + offset_in_page(gpa)), val);
1949 kunmap_atomic(kaddr, KM_USER0);
2bacc55c
MT		 1950 kvm_release_page_dirty(page);
1951 }
3200f405 1952emul_write:
2bacc55c
MT		 1953#endif
1954
bbd9b64e
CO		 1955 return emulator_write_emulated(addr, new, bytes, vcpu);
1956}
1957
1958static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
1959{
1960 return kvm_x86_ops->get_segment_base(vcpu, seg);
1961}
1962
1963int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address)
1964{
1965 return X86EMUL_CONTINUE;
1966}
1967
1968int emulate_clts(struct kvm_vcpu *vcpu)
1969{
ad312c7c 1970 kvm_x86_ops->set_cr0(vcpu, vcpu->arch.cr0 & ~X86_CR0_TS);
bbd9b64e
CO		 1971 return X86EMUL_CONTINUE;
1972}
1973
1974int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
1975{
1976 struct kvm_vcpu *vcpu = ctxt->vcpu;
1977
1978 switch (dr) {
1979 case 0 ... 3:
1980 *dest = kvm_x86_ops->get_dr(vcpu, dr);
1981 return X86EMUL_CONTINUE;
1982 default:
b8688d51 1983 pr_unimpl(vcpu, "%s: unexpected dr %u\n", __func__, dr);
bbd9b64e
CO		 1984 return X86EMUL_UNHANDLEABLE;
1985 }
1986}
1987
1988int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
1989{
1990 unsigned long mask = (ctxt->mode == X86EMUL_MODE_PROT64) ? ~0ULL : ~0U;
1991 int exception;
1992
1993 kvm_x86_ops->set_dr(ctxt->vcpu, dr, value & mask, &exception);
1994 if (exception) {
1995 /* FIXME: better handling */
1996 return X86EMUL_UNHANDLEABLE;
1997 }
1998 return X86EMUL_CONTINUE;
1999}
2000
2001void kvm_report_emulation_failure(struct kvm_vcpu *vcpu, const char *context)
2002{
2003 static int reported;
2004 u8 opcodes[4];
ad312c7c 2005 unsigned long rip = vcpu->arch.rip;
bbd9b64e
CO		 2006 unsigned long rip_linear;
2007
2008 rip_linear = rip + get_segment_base(vcpu, VCPU_SREG_CS);
2009
2010 if (reported)
2011 return;
2012
2013 emulator_read_std(rip_linear, (void *)opcodes, 4, vcpu);
2014
2015 printk(KERN_ERR "emulation failed (%s) rip %lx %02x %02x %02x %02x\n",
2016 context, rip, opcodes[0], opcodes[1], opcodes[2], opcodes[3]);
2017 reported = 1;
2018}
2019EXPORT_SYMBOL_GPL(kvm_report_emulation_failure);
2020
14af3f3c 2021static struct x86_emulate_ops emulate_ops = {
bbd9b64e 2022 .read_std = emulator_read_std,
bbd9b64e
CO		 2023 .read_emulated = emulator_read_emulated,
2024 .write_emulated = emulator_write_emulated,
2025 .cmpxchg_emulated = emulator_cmpxchg_emulated,
2026};
2027
2028int emulate_instruction(struct kvm_vcpu *vcpu,
2029 struct kvm_run *run,
2030 unsigned long cr2,
2031 u16 error_code,
571008da 2032 int emulation_type)
bbd9b64e
CO		 2033{
2034 int r;
571008da 2035 struct decode_cache *c;
bbd9b64e 2036
ad312c7c 2037 vcpu->arch.mmio_fault_cr2 = cr2;
bbd9b64e
CO		 2038 kvm_x86_ops->cache_regs(vcpu);
2039
2040 vcpu->mmio_is_write = 0;
ad312c7c 2041 vcpu->arch.pio.string = 0;
bbd9b64e 2042
571008da 2043 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
bbd9b64e
CO		 2044 int cs_db, cs_l;
2045 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
2046
ad312c7c
ZX		 2047 vcpu->arch.emulate_ctxt.vcpu = vcpu;
2048 vcpu->arch.emulate_ctxt.eflags = kvm_x86_ops->get_rflags(vcpu);
2049 vcpu->arch.emulate_ctxt.mode =
2050 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
bbd9b64e
CO		 2051 ? X86EMUL_MODE_REAL : cs_l
2052 ? X86EMUL_MODE_PROT64 : cs_db
2053 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
2054
ad312c7c
ZX		 2055 if (vcpu->arch.emulate_ctxt.mode == X86EMUL_MODE_PROT64) {
2056 vcpu->arch.emulate_ctxt.cs_base = 0;
2057 vcpu->arch.emulate_ctxt.ds_base = 0;
2058 vcpu->arch.emulate_ctxt.es_base = 0;
2059 vcpu->arch.emulate_ctxt.ss_base = 0;
bbd9b64e 2060 } else {
ad312c7c 2061 vcpu->arch.emulate_ctxt.cs_base =
bbd9b64e 2062 get_segment_base(vcpu, VCPU_SREG_CS);
ad312c7c 2063 vcpu->arch.emulate_ctxt.ds_base =
bbd9b64e 2064 get_segment_base(vcpu, VCPU_SREG_DS);
ad312c7c 2065 vcpu->arch.emulate_ctxt.es_base =
bbd9b64e 2066 get_segment_base(vcpu, VCPU_SREG_ES);
ad312c7c 2067 vcpu->arch.emulate_ctxt.ss_base =
bbd9b64e
CO		 2068 get_segment_base(vcpu, VCPU_SREG_SS);
2069 }
2070
ad312c7c 2071 vcpu->arch.emulate_ctxt.gs_base =
bbd9b64e 2072 get_segment_base(vcpu, VCPU_SREG_GS);
ad312c7c 2073 vcpu->arch.emulate_ctxt.fs_base =
bbd9b64e
CO		 2074 get_segment_base(vcpu, VCPU_SREG_FS);
2075
ad312c7c 2076 r = x86_decode_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
571008da
SY		 2077
2078 /* Reject the instructions other than VMCALL/VMMCALL when
2079 * try to emulate invalid opcode */
2080 c = &vcpu->arch.emulate_ctxt.decode;
2081 if ((emulation_type & EMULTYPE_TRAP_UD) &&
2082 (!(c->twobyte && c->b == 0x01 &&
2083 (c->modrm_reg == 0 || c->modrm_reg == 3) &&
2084 c->modrm_mod == 3 && c->modrm_rm == 1)))
2085 return EMULATE_FAIL;
2086
f2b5756b 2087 ++vcpu->stat.insn_emulation;
bbd9b64e 2088 if (r) {
f2b5756b 2089 ++vcpu->stat.insn_emulation_fail;
bbd9b64e
CO		 2090 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
2091 return EMULATE_DONE;
2092 return EMULATE_FAIL;
2093 }
2094 }
2095
ad312c7c 2096 r = x86_emulate_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
bbd9b64e 2097
ad312c7c 2098 if (vcpu->arch.pio.string)
bbd9b64e
CO		 2099 return EMULATE_DO_MMIO;
2100
2101 if ((r || vcpu->mmio_is_write) && run) {
2102 run->exit_reason = KVM_EXIT_MMIO;
2103 run->mmio.phys_addr = vcpu->mmio_phys_addr;
2104 memcpy(run->mmio.data, vcpu->mmio_data, 8);
2105 run->mmio.len = vcpu->mmio_size;
2106 run->mmio.is_write = vcpu->mmio_is_write;
2107 }
2108
2109 if (r) {
2110 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
2111 return EMULATE_DONE;
2112 if (!vcpu->mmio_needed) {
2113 kvm_report_emulation_failure(vcpu, "mmio");
2114 return EMULATE_FAIL;
2115 }
2116 return EMULATE_DO_MMIO;
2117 }
2118
2119 kvm_x86_ops->decache_regs(vcpu);
ad312c7c 2120 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
bbd9b64e
CO		 2121
2122 if (vcpu->mmio_is_write) {
2123 vcpu->mmio_needed = 0;
2124 return EMULATE_DO_MMIO;
2125 }
2126
2127 return EMULATE_DONE;
2128}
2129EXPORT_SYMBOL_GPL(emulate_instruction);
2130
de7d789a
CO		 2131static void free_pio_guest_pages(struct kvm_vcpu *vcpu)
2132{
2133 int i;
2134
ad312c7c
ZX		 2135 for (i = 0; i < ARRAY_SIZE(vcpu->arch.pio.guest_pages); ++i)
2136 if (vcpu->arch.pio.guest_pages[i]) {
2137 kvm_release_page_dirty(vcpu->arch.pio.guest_pages[i]);
2138 vcpu->arch.pio.guest_pages[i] = NULL;
de7d789a
CO		 2139 }
2140}
2141
2142static int pio_copy_data(struct kvm_vcpu *vcpu)
2143{
ad312c7c 2144 void *p = vcpu->arch.pio_data;
de7d789a
CO		 2145 void *q;
2146 unsigned bytes;
ad312c7c 2147 int nr_pages = vcpu->arch.pio.guest_pages[1] ? 2 : 1;
de7d789a 2148
ad312c7c 2149 q = vmap(vcpu->arch.pio.guest_pages, nr_pages, VM_READ|VM_WRITE,
de7d789a
CO		 2150 PAGE_KERNEL);
2151 if (!q) {
2152 free_pio_guest_pages(vcpu);
2153 return -ENOMEM;
2154 }
ad312c7c
ZX		 2155 q += vcpu->arch.pio.guest_page_offset;
2156 bytes = vcpu->arch.pio.size * vcpu->arch.pio.cur_count;
2157 if (vcpu->arch.pio.in)
de7d789a
CO		 2158 memcpy(q, p, bytes);
2159 else
2160 memcpy(p, q, bytes);
ad312c7c 2161 q -= vcpu->arch.pio.guest_page_offset;
de7d789a
CO		 2162 vunmap(q);
2163 free_pio_guest_pages(vcpu);
2164 return 0;
2165}
2166
2167int complete_pio(struct kvm_vcpu *vcpu)
2168{
ad312c7c 2169 struct kvm_pio_request *io = &vcpu->arch.pio;
de7d789a
CO		 2170 long delta;
2171 int r;
2172
2173 kvm_x86_ops->cache_regs(vcpu);
2174
2175 if (!io->string) {
2176 if (io->in)
ad312c7c 2177 memcpy(&vcpu->arch.regs[VCPU_REGS_RAX], vcpu->arch.pio_data,
de7d789a
CO		 2178 io->size);
2179 } else {
2180 if (io->in) {
2181 r = pio_copy_data(vcpu);
2182 if (r) {
2183 kvm_x86_ops->cache_regs(vcpu);
2184 return r;
2185 }
2186 }
2187
2188 delta = 1;
2189 if (io->rep) {
2190 delta *= io->cur_count;
2191 /*
2192 * The size of the register should really depend on
2193 * current address size.
2194 */
ad312c7c 2195 vcpu->arch.regs[VCPU_REGS_RCX] -= delta;
de7d789a
CO		 2196 }
2197 if (io->down)
2198 delta = -delta;
2199 delta *= io->size;
2200 if (io->in)
ad312c7c 2201 vcpu->arch.regs[VCPU_REGS_RDI] += delta;
de7d789a 2202 else
ad312c7c 2203 vcpu->arch.regs[VCPU_REGS_RSI] += delta;
de7d789a
CO		 2204 }
2205
2206 kvm_x86_ops->decache_regs(vcpu);
2207
2208 io->count -= io->cur_count;
2209 io->cur_count = 0;
2210
2211 return 0;
2212}
2213
2214static void kernel_pio(struct kvm_io_device *pio_dev,
2215 struct kvm_vcpu *vcpu,
2216 void *pd)
2217{
2218 /* TODO: String I/O for in kernel device */
2219
2220 mutex_lock(&vcpu->kvm->lock);
ad312c7c
ZX		 2221 if (vcpu->arch.pio.in)
2222 kvm_iodevice_read(pio_dev, vcpu->arch.pio.port,
2223 vcpu->arch.pio.size,
de7d789a
CO		 2224 pd);
2225 else
ad312c7c
ZX		 2226 kvm_iodevice_write(pio_dev, vcpu->arch.pio.port,
2227 vcpu->arch.pio.size,
de7d789a
CO		 2228 pd);
2229 mutex_unlock(&vcpu->kvm->lock);
2230}
2231
2232static void pio_string_write(struct kvm_io_device *pio_dev,
2233 struct kvm_vcpu *vcpu)
2234{
ad312c7c
ZX		 2235 struct kvm_pio_request *io = &vcpu->arch.pio;
2236 void *pd = vcpu->arch.pio_data;
de7d789a
CO		 2237 int i;
2238
2239 mutex_lock(&vcpu->kvm->lock);
2240 for (i = 0; i < io->cur_count; i++) {
2241 kvm_iodevice_write(pio_dev, io->port,
2242 io->size,
2243 pd);
2244 pd += io->size;
2245 }
2246 mutex_unlock(&vcpu->kvm->lock);
2247}
2248
2249static struct kvm_io_device *vcpu_find_pio_dev(struct kvm_vcpu *vcpu,
2250 gpa_t addr)
2251{
2252 return kvm_io_bus_find_dev(&vcpu->kvm->pio_bus, addr);
2253}
2254
2255int kvm_emulate_pio(struct kvm_vcpu *vcpu, struct kvm_run *run, int in,
2256 int size, unsigned port)
2257{
2258 struct kvm_io_device *pio_dev;
2259
2260 vcpu->run->exit_reason = KVM_EXIT_IO;
2261 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
ad312c7c 2262 vcpu->run->io.size = vcpu->arch.pio.size = size;
de7d789a 2263 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
ad312c7c
ZX		 2264 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = 1;
2265 vcpu->run->io.port = vcpu->arch.pio.port = port;
2266 vcpu->arch.pio.in = in;
2267 vcpu->arch.pio.string = 0;
2268 vcpu->arch.pio.down = 0;
2269 vcpu->arch.pio.guest_page_offset = 0;
2270 vcpu->arch.pio.rep = 0;
de7d789a
CO		 2271
2272 kvm_x86_ops->cache_regs(vcpu);
ad312c7c 2273 memcpy(vcpu->arch.pio_data, &vcpu->arch.regs[VCPU_REGS_RAX], 4);
de7d789a
CO		 2274 kvm_x86_ops->decache_regs(vcpu);
2275
2276 kvm_x86_ops->skip_emulated_instruction(vcpu);
2277
2278 pio_dev = vcpu_find_pio_dev(vcpu, port);
2279 if (pio_dev) {
ad312c7c 2280 kernel_pio(pio_dev, vcpu, vcpu->arch.pio_data);
de7d789a
CO		 2281 complete_pio(vcpu);
2282 return 1;
2283 }
2284 return 0;
2285}
2286EXPORT_SYMBOL_GPL(kvm_emulate_pio);
2287
2288int kvm_emulate_pio_string(struct kvm_vcpu *vcpu, struct kvm_run *run, int in,
2289 int size, unsigned long count, int down,
2290 gva_t address, int rep, unsigned port)
2291{
2292 unsigned now, in_page;
2293 int i, ret = 0;
2294 int nr_pages = 1;
2295 struct page *page;
2296 struct kvm_io_device *pio_dev;
2297
2298 vcpu->run->exit_reason = KVM_EXIT_IO;
2299 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
ad312c7c 2300 vcpu->run->io.size = vcpu->arch.pio.size = size;
de7d789a 2301 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
ad312c7c
ZX		 2302 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = count;
2303 vcpu->run->io.port = vcpu->arch.pio.port = port;
2304 vcpu->arch.pio.in = in;
2305 vcpu->arch.pio.string = 1;
2306 vcpu->arch.pio.down = down;
2307 vcpu->arch.pio.guest_page_offset = offset_in_page(address);
2308 vcpu->arch.pio.rep = rep;
de7d789a
CO		 2309
2310 if (!count) {
2311 kvm_x86_ops->skip_emulated_instruction(vcpu);
2312 return 1;
2313 }
2314
2315 if (!down)
2316 in_page = PAGE_SIZE - offset_in_page(address);
2317 else
2318 in_page = offset_in_page(address) + size;
2319 now = min(count, (unsigned long)in_page / size);
2320 if (!now) {
2321 /*
2322 * String I/O straddles page boundary. Pin two guest pages
2323 * so that we satisfy atomicity constraints. Do just one
2324 * transaction to avoid complexity.
2325 */
2326 nr_pages = 2;
2327 now = 1;
2328 }
2329 if (down) {
2330 /*
2331 * String I/O in reverse. Yuck. Kill the guest, fix later.
2332 */
2333 pr_unimpl(vcpu, "guest string pio down\n");
c1a5d4f9 2334 kvm_inject_gp(vcpu, 0);
de7d789a
CO		 2335 return 1;
2336 }
2337 vcpu->run->io.count = now;
ad312c7c 2338 vcpu->arch.pio.cur_count = now;
de7d789a 2339
ad312c7c 2340 if (vcpu->arch.pio.cur_count == vcpu->arch.pio.count)
de7d789a
CO		 2341 kvm_x86_ops->skip_emulated_instruction(vcpu);
2342
2343 for (i = 0; i < nr_pages; ++i) {
de7d789a 2344 page = gva_to_page(vcpu, address + i * PAGE_SIZE);
ad312c7c 2345 vcpu->arch.pio.guest_pages[i] = page;
de7d789a 2346 if (!page) {
c1a5d4f9 2347 kvm_inject_gp(vcpu, 0);
de7d789a
CO		 2348 free_pio_guest_pages(vcpu);
2349 return 1;
2350 }
2351 }
2352
2353 pio_dev = vcpu_find_pio_dev(vcpu, port);
ad312c7c 2354 if (!vcpu->arch.pio.in) {
de7d789a
CO		 2355 /* string PIO write */
2356 ret = pio_copy_data(vcpu);
2357 if (ret >= 0 && pio_dev) {
2358 pio_string_write(pio_dev, vcpu);
2359 complete_pio(vcpu);
ad312c7c 2360 if (vcpu->arch.pio.count == 0)
de7d789a
CO		 2361 ret = 1;
2362 }
2363 } else if (pio_dev)
2364 pr_unimpl(vcpu, "no string pio read support yet, "
2365 "port %x size %d count %ld\n",
2366 port, size, count);
2367
2368 return ret;
2369}
2370EXPORT_SYMBOL_GPL(kvm_emulate_pio_string);
2371
f8c16bba 2372int kvm_arch_init(void *opaque)
043405e1 2373{
56c6d28a 2374 int r;
f8c16bba
ZX		 2375 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
2376
f8c16bba
ZX		 2377 if (kvm_x86_ops) {
2378 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 2379 r = -EEXIST;
2380 goto out;
f8c16bba
ZX		 2381 }
2382
2383 if (!ops->cpu_has_kvm_support()) {
2384 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 2385 r = -EOPNOTSUPP;
2386 goto out;
f8c16bba
ZX		 2387 }
2388 if (ops->disabled_by_bios()) {
2389 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 2390 r = -EOPNOTSUPP;
2391 goto out;
f8c16bba
ZX		 2392 }
2393
97db56ce
AK		 2394 r = kvm_mmu_module_init();
2395 if (r)
2396 goto out;
2397
2398 kvm_init_msr_list();
2399
f8c16bba 2400 kvm_x86_ops = ops;
56c6d28a 2401 kvm_mmu_set_nonpresent_ptes(0ull, 0ull);
f8c16bba 2402 return 0;
56c6d28a
ZX		 2403
2404out:
56c6d28a 2405 return r;
043405e1 2406}
8776e519 2407
f8c16bba
ZX		 2408void kvm_arch_exit(void)
2409{
2410 kvm_x86_ops = NULL;
56c6d28a
ZX		 2411 kvm_mmu_module_exit();
2412}
f8c16bba 2413
8776e519
HB		 2414int kvm_emulate_halt(struct kvm_vcpu *vcpu)
2415{
2416 ++vcpu->stat.halt_exits;
2417 if (irqchip_in_kernel(vcpu->kvm)) {
ad312c7c 2418 vcpu->arch.mp_state = VCPU_MP_STATE_HALTED;
3200f405 2419 up_read(&vcpu->kvm->slots_lock);
8776e519 2420 kvm_vcpu_block(vcpu);
3200f405 2421 down_read(&vcpu->kvm->slots_lock);
ad312c7c 2422 if (vcpu->arch.mp_state != VCPU_MP_STATE_RUNNABLE)
8776e519
HB		 2423 return -EINTR;
2424 return 1;
2425 } else {
2426 vcpu->run->exit_reason = KVM_EXIT_HLT;
2427 return 0;
2428 }
2429}
2430EXPORT_SYMBOL_GPL(kvm_emulate_halt);
2431
2f333bcb
MT		 2432static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
2433 unsigned long a1)
2434{
2435 if (is_long_mode(vcpu))
2436 return a0;
2437 else
2438 return a0 | ((gpa_t)a1 << 32);
2439}
2440
8776e519
HB		 2441int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
2442{
2443 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 2444 int r = 1;
8776e519
HB		 2445
2446 kvm_x86_ops->cache_regs(vcpu);
2447
ad312c7c
ZX		 2448 nr = vcpu->arch.regs[VCPU_REGS_RAX];
2449 a0 = vcpu->arch.regs[VCPU_REGS_RBX];
2450 a1 = vcpu->arch.regs[VCPU_REGS_RCX];
2451 a2 = vcpu->arch.regs[VCPU_REGS_RDX];
2452 a3 = vcpu->arch.regs[VCPU_REGS_RSI];
8776e519
HB		 2453
2454 if (!is_long_mode(vcpu)) {
2455 nr &= 0xFFFFFFFF;
2456 a0 &= 0xFFFFFFFF;
2457 a1 &= 0xFFFFFFFF;
2458 a2 &= 0xFFFFFFFF;
2459 a3 &= 0xFFFFFFFF;
2460 }
2461
2462 switch (nr) {
b93463aa
AK		 2463 case KVM_HC_VAPIC_POLL_IRQ:
2464 ret = 0;
2465 break;
2f333bcb
MT		 2466 case KVM_HC_MMU_OP:
2467 r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
2468 break;
8776e519
HB		 2469 default:
2470 ret = -KVM_ENOSYS;
2471 break;
2472 }
ad312c7c 2473 vcpu->arch.regs[VCPU_REGS_RAX] = ret;
8776e519 2474 kvm_x86_ops->decache_regs(vcpu);
f11c3a8d 2475 ++vcpu->stat.hypercalls;
2f333bcb 2476 return r;
8776e519
HB		 2477}
2478EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
2479
2480int kvm_fix_hypercall(struct kvm_vcpu *vcpu)
2481{
2482 char instruction[3];
2483 int ret = 0;
2484
8776e519
HB		 2485
2486 /*
2487 * Blow out the MMU to ensure that no other VCPU has an active mapping
2488 * to ensure that the updated hypercall appears atomically across all
2489 * VCPUs.
2490 */
2491 kvm_mmu_zap_all(vcpu->kvm);
2492
2493 kvm_x86_ops->cache_regs(vcpu);
2494 kvm_x86_ops->patch_hypercall(vcpu, instruction);
ad312c7c 2495 if (emulator_write_emulated(vcpu->arch.rip, instruction, 3, vcpu)
8776e519
HB		 2496 != X86EMUL_CONTINUE)
2497 ret = -EFAULT;
2498
8776e519
HB		 2499 return ret;
2500}
2501
2502static u64 mk_cr_64(u64 curr_cr, u32 new_val)
2503{
2504 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
2505}
2506
2507void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
2508{
2509 struct descriptor_table dt = { limit, base };
2510
2511 kvm_x86_ops->set_gdt(vcpu, &dt);
2512}
2513
2514void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
2515{
2516 struct descriptor_table dt = { limit, base };
2517
2518 kvm_x86_ops->set_idt(vcpu, &dt);
2519}
2520
2521void realmode_lmsw(struct kvm_vcpu *vcpu, unsigned long msw,
2522 unsigned long *rflags)
2523{
2d3ad1f4 2524 kvm_lmsw(vcpu, msw);
8776e519
HB		 2525 *rflags = kvm_x86_ops->get_rflags(vcpu);
2526}
2527
2528unsigned long realmode_get_cr(struct kvm_vcpu *vcpu, int cr)
2529{
2530 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
2531 switch (cr) {
2532 case 0:
ad312c7c 2533 return vcpu->arch.cr0;
8776e519 2534 case 2:
ad312c7c 2535 return vcpu->arch.cr2;
8776e519 2536 case 3:
ad312c7c 2537 return vcpu->arch.cr3;
8776e519 2538 case 4:
ad312c7c 2539 return vcpu->arch.cr4;
152ff9be 2540 case 8:
2d3ad1f4 2541 return kvm_get_cr8(vcpu);
8776e519 2542 default:
b8688d51 2543 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
8776e519
HB		 2544 return 0;
2545 }
2546}
2547
2548void realmode_set_cr(struct kvm_vcpu *vcpu, int cr, unsigned long val,
2549 unsigned long *rflags)
2550{
2551 switch (cr) {
2552 case 0:
2d3ad1f4 2553 kvm_set_cr0(vcpu, mk_cr_64(vcpu->arch.cr0, val));
8776e519
HB		 2554 *rflags = kvm_x86_ops->get_rflags(vcpu);
2555 break;
2556 case 2:
ad312c7c 2557 vcpu->arch.cr2 = val;
8776e519
HB		 2558 break;
2559 case 3:
2d3ad1f4 2560 kvm_set_cr3(vcpu, val);
8776e519
HB		 2561 break;
2562 case 4:
2d3ad1f4 2563 kvm_set_cr4(vcpu, mk_cr_64(vcpu->arch.cr4, val));
8776e519 2564 break;
152ff9be 2565 case 8:
2d3ad1f4 2566 kvm_set_cr8(vcpu, val & 0xfUL);
152ff9be 2567 break;
8776e519 2568 default:
b8688d51 2569 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
8776e519
HB		 2570 }
2571}
2572
07716717
DK		 2573static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
2574{
ad312c7c
ZX		 2575 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
2576 int j, nent = vcpu->arch.cpuid_nent;
07716717
DK		 2577
2578 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
2579 /* when no next entry is found, the current entry[i] is reselected */
2580 for (j = i + 1; j == i; j = (j + 1) % nent) {
ad312c7c 2581 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
07716717
DK		 2582 if (ej->function == e->function) {
2583 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
2584 return j;
2585 }
2586 }
2587 return 0; /* silence gcc, even though control never reaches here */
2588}
2589
2590/* find an entry with matching function, matching index (if needed), and that
2591 * should be read next (if it's stateful) */
2592static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
2593 u32 function, u32 index)
2594{
2595 if (e->function != function)
2596 return 0;
2597 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
2598 return 0;
2599 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
2600 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
2601 return 0;
2602 return 1;
2603}
2604
8776e519
HB		 2605void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
2606{
2607 int i;
07716717
DK		 2608 u32 function, index;
2609 struct kvm_cpuid_entry2 *e, *best;
8776e519
HB		 2610
2611 kvm_x86_ops->cache_regs(vcpu);
ad312c7c
ZX		 2612 function = vcpu->arch.regs[VCPU_REGS_RAX];
2613 index = vcpu->arch.regs[VCPU_REGS_RCX];
2614 vcpu->arch.regs[VCPU_REGS_RAX] = 0;
2615 vcpu->arch.regs[VCPU_REGS_RBX] = 0;
2616 vcpu->arch.regs[VCPU_REGS_RCX] = 0;
2617 vcpu->arch.regs[VCPU_REGS_RDX] = 0;
8776e519 2618 best = NULL;
ad312c7c
ZX		 2619 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
2620 e = &vcpu->arch.cpuid_entries[i];
07716717
DK		 2621 if (is_matching_cpuid_entry(e, function, index)) {
2622 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
2623 move_to_next_stateful_cpuid_entry(vcpu, i);
8776e519
HB		 2624 best = e;
2625 break;
2626 }
2627 /*
2628 * Both basic or both extended?
2629 */
2630 if (((e->function ^ function) & 0x80000000) == 0)
2631 if (!best || e->function > best->function)
2632 best = e;
2633 }
2634 if (best) {
ad312c7c
ZX		 2635 vcpu->arch.regs[VCPU_REGS_RAX] = best->eax;
2636 vcpu->arch.regs[VCPU_REGS_RBX] = best->ebx;
2637 vcpu->arch.regs[VCPU_REGS_RCX] = best->ecx;
2638 vcpu->arch.regs[VCPU_REGS_RDX] = best->edx;
8776e519
HB		 2639 }
2640 kvm_x86_ops->decache_regs(vcpu);
2641 kvm_x86_ops->skip_emulated_instruction(vcpu);
2642}
2643EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
d0752060 2644
b6c7a5dc
HB		 2645/*
2646 * Check if userspace requested an interrupt window, and that the
2647 * interrupt window is open.
2648 *
2649 * No need to exit to userspace if we already have an interrupt queued.
2650 */
2651static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu,
2652 struct kvm_run *kvm_run)
2653{
ad312c7c 2654 return (!vcpu->arch.irq_summary &&
b6c7a5dc 2655 kvm_run->request_interrupt_window &&
ad312c7c 2656 vcpu->arch.interrupt_window_open &&
b6c7a5dc
HB		 2657 (kvm_x86_ops->get_rflags(vcpu) & X86_EFLAGS_IF));
2658}
2659
2660static void post_kvm_run_save(struct kvm_vcpu *vcpu,
2661 struct kvm_run *kvm_run)
2662{
2663 kvm_run->if_flag = (kvm_x86_ops->get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 2664 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc
HB		 2665 kvm_run->apic_base = kvm_get_apic_base(vcpu);
2666 if (irqchip_in_kernel(vcpu->kvm))
2667 kvm_run->ready_for_interrupt_injection = 1;
2668 else
2669 kvm_run->ready_for_interrupt_injection =
ad312c7c
ZX		 2670 (vcpu->arch.interrupt_window_open &&
2671 vcpu->arch.irq_summary == 0);
b6c7a5dc
HB		 2672}
2673
b93463aa
AK		 2674static void vapic_enter(struct kvm_vcpu *vcpu)
2675{
2676 struct kvm_lapic *apic = vcpu->arch.apic;
2677 struct page *page;
2678
2679 if (!apic || !apic->vapic_addr)
2680 return;
2681
10589a46 2682 down_read(&current->mm->mmap_sem);
b93463aa 2683 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
10589a46 2684 up_read(&current->mm->mmap_sem);
72dc67a6
IE		 2685
2686 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 2687}
2688
2689static void vapic_exit(struct kvm_vcpu *vcpu)
2690{
2691 struct kvm_lapic *apic = vcpu->arch.apic;
2692
2693 if (!apic || !apic->vapic_addr)
2694 return;
2695
2696 kvm_release_page_dirty(apic->vapic_page);
2697 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
2698}
2699
b6c7a5dc
HB		 2700static int __vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2701{
2702 int r;
2703
ad312c7c 2704 if (unlikely(vcpu->arch.mp_state == VCPU_MP_STATE_SIPI_RECEIVED)) {
b6c7a5dc 2705 pr_debug("vcpu %d received sipi with vector # %x\n",
ad312c7c 2706 vcpu->vcpu_id, vcpu->arch.sipi_vector);
b6c7a5dc
HB		 2707 kvm_lapic_reset(vcpu);
2708 r = kvm_x86_ops->vcpu_reset(vcpu);
2709 if (r)
2710 return r;
ad312c7c 2711 vcpu->arch.mp_state = VCPU_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 2712 }
2713
3200f405 2714 down_read(&vcpu->kvm->slots_lock);
b93463aa
AK		 2715 vapic_enter(vcpu);
2716
b6c7a5dc
HB		 2717preempted:
2718 if (vcpu->guest_debug.enabled)
2719 kvm_x86_ops->guest_debug_pre(vcpu);
2720
2721again:
2e53d63a
MT		 2722 if (vcpu->requests)
2723 if (test_and_clear_bit(KVM_REQ_MMU_RELOAD, &vcpu->requests))
2724 kvm_mmu_unload(vcpu);
2725
b6c7a5dc
HB		 2726 r = kvm_mmu_reload(vcpu);
2727 if (unlikely(r))
2728 goto out;
2729
2f52d58c
AK		 2730 if (vcpu->requests) {
2731 if (test_and_clear_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests))
2732 __kvm_migrate_apic_timer(vcpu);
b93463aa
AK		 2733 if (test_and_clear_bit(KVM_REQ_REPORT_TPR_ACCESS,
2734 &vcpu->requests)) {
2735 kvm_run->exit_reason = KVM_EXIT_TPR_ACCESS;
2736 r = 0;
2737 goto out;
2738 }
71c4dfaf
JR		 2739 if (test_and_clear_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests)) {
2740 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2741 r = 0;
2742 goto out;
2743 }
2f52d58c 2744 }
b93463aa 2745
b6c7a5dc
HB		 2746 kvm_inject_pending_timer_irqs(vcpu);
2747
2748 preempt_disable();
2749
2750 kvm_x86_ops->prepare_guest_switch(vcpu);
2751 kvm_load_guest_fpu(vcpu);
2752
2753 local_irq_disable();
2754
6c142801
AK		 2755 if (need_resched()) {
2756 local_irq_enable();
2757 preempt_enable();
2758 r = 1;
2759 goto out;
2760 }
2761
2e53d63a
MT		 2762 if (vcpu->requests)
2763 if (test_bit(KVM_REQ_MMU_RELOAD, &vcpu->requests)) {
2764 local_irq_enable();
2765 preempt_enable();
2766 r = 1;
2767 goto out;
2768 }
2769
b6c7a5dc
HB		 2770 if (signal_pending(current)) {
2771 local_irq_enable();
2772 preempt_enable();
2773 r = -EINTR;
2774 kvm_run->exit_reason = KVM_EXIT_INTR;
2775 ++vcpu->stat.signal_exits;
2776 goto out;
2777 }
2778
ad312c7c 2779 if (vcpu->arch.exception.pending)
298101da
AK		 2780 __queue_exception(vcpu);
2781 else if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 2782 kvm_x86_ops->inject_pending_irq(vcpu);
eb9774f0 2783 else
b6c7a5dc
HB		 2784 kvm_x86_ops->inject_pending_vectors(vcpu, kvm_run);
2785
b93463aa
AK		 2786 kvm_lapic_sync_to_vapic(vcpu);
2787
3200f405
MT		 2788 up_read(&vcpu->kvm->slots_lock);
2789
b6c7a5dc
HB		 2790 vcpu->guest_mode = 1;
2791 kvm_guest_enter();
2792
2793 if (vcpu->requests)
2794 if (test_and_clear_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests))
2795 kvm_x86_ops->tlb_flush(vcpu);
2796
2797 kvm_x86_ops->run(vcpu, kvm_run);
2798
2799 vcpu->guest_mode = 0;
2800 local_irq_enable();
2801
2802 ++vcpu->stat.exits;
2803
2804 /*
2805 * We must have an instruction between local_irq_enable() and
2806 * kvm_guest_exit(), so the timer interrupt isn't delayed by
2807 * the interrupt shadow. The stat.exits increment will do nicely.
2808 * But we need to prevent reordering, hence this barrier():
2809 */
2810 barrier();
2811
2812 kvm_guest_exit();
2813
2814 preempt_enable();
2815
3200f405
MT		 2816 down_read(&vcpu->kvm->slots_lock);
2817
b6c7a5dc
HB		 2818 /*
2819 * Profile KVM exit RIPs:
2820 */
2821 if (unlikely(prof_on == KVM_PROFILING)) {
2822 kvm_x86_ops->cache_regs(vcpu);
ad312c7c 2823 profile_hit(KVM_PROFILING, (void *)vcpu->arch.rip);
b6c7a5dc
HB		 2824 }
2825
ad312c7c
ZX		 2826 if (vcpu->arch.exception.pending && kvm_x86_ops->exception_injected(vcpu))
2827 vcpu->arch.exception.pending = false;
298101da 2828
b93463aa
AK		 2829 kvm_lapic_sync_from_vapic(vcpu);
2830
b6c7a5dc
HB		 2831 r = kvm_x86_ops->handle_exit(kvm_run, vcpu);
2832
2833 if (r > 0) {
2834 if (dm_request_for_irq_injection(vcpu, kvm_run)) {
2835 r = -EINTR;
2836 kvm_run->exit_reason = KVM_EXIT_INTR;
2837 ++vcpu->stat.request_irq_exits;
2838 goto out;
2839 }
e1beb1d3 2840 if (!need_resched())
b6c7a5dc 2841 goto again;
b6c7a5dc
HB		 2842 }
2843
2844out:
3200f405 2845 up_read(&vcpu->kvm->slots_lock);
b6c7a5dc
HB		 2846 if (r > 0) {
2847 kvm_resched(vcpu);
3200f405 2848 down_read(&vcpu->kvm->slots_lock);
b6c7a5dc
HB		 2849 goto preempted;
2850 }
2851
2852 post_kvm_run_save(vcpu, kvm_run);
2853
3200f405 2854 down_read(&vcpu->kvm->slots_lock);
b93463aa 2855 vapic_exit(vcpu);
3200f405 2856 up_read(&vcpu->kvm->slots_lock);
b93463aa 2857
b6c7a5dc
HB		 2858 return r;
2859}
2860
2861int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2862{
2863 int r;
2864 sigset_t sigsaved;
2865
2866 vcpu_load(vcpu);
2867
ad312c7c 2868 if (unlikely(vcpu->arch.mp_state == VCPU_MP_STATE_UNINITIALIZED)) {
b6c7a5dc
HB		 2869 kvm_vcpu_block(vcpu);
2870 vcpu_put(vcpu);
2871 return -EAGAIN;
2872 }
2873
2874 if (vcpu->sigset_active)
2875 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
2876
2877 /* re-sync apic's tpr */
2878 if (!irqchip_in_kernel(vcpu->kvm))
2d3ad1f4 2879 kvm_set_cr8(vcpu, kvm_run->cr8);
b6c7a5dc 2880
ad312c7c 2881 if (vcpu->arch.pio.cur_count) {
b6c7a5dc
HB		 2882 r = complete_pio(vcpu);
2883 if (r)
2884 goto out;
2885 }
2886#if CONFIG_HAS_IOMEM
2887 if (vcpu->mmio_needed) {
2888 memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8);
2889 vcpu->mmio_read_completed = 1;
2890 vcpu->mmio_needed = 0;
3200f405
MT		 2891
2892 down_read(&vcpu->kvm->slots_lock);
b6c7a5dc 2893 r = emulate_instruction(vcpu, kvm_run,
571008da
SY		 2894 vcpu->arch.mmio_fault_cr2, 0,
2895 EMULTYPE_NO_DECODE);
3200f405 2896 up_read(&vcpu->kvm->slots_lock);
b6c7a5dc
HB		 2897 if (r == EMULATE_DO_MMIO) {
2898 /*
2899 * Read-modify-write. Back to userspace.
2900 */
2901 r = 0;
2902 goto out;
2903 }
2904 }
2905#endif
2906 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL) {
2907 kvm_x86_ops->cache_regs(vcpu);
ad312c7c 2908 vcpu->arch.regs[VCPU_REGS_RAX] = kvm_run->hypercall.ret;
b6c7a5dc
HB		 2909 kvm_x86_ops->decache_regs(vcpu);
2910 }
2911
2912 r = __vcpu_run(vcpu, kvm_run);
2913
2914out:
2915 if (vcpu->sigset_active)
2916 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
2917
2918 vcpu_put(vcpu);
2919 return r;
2920}
2921
2922int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
2923{
2924 vcpu_load(vcpu);
2925
2926 kvm_x86_ops->cache_regs(vcpu);
2927
ad312c7c
ZX		 2928 regs->rax = vcpu->arch.regs[VCPU_REGS_RAX];
2929 regs->rbx = vcpu->arch.regs[VCPU_REGS_RBX];
2930 regs->rcx = vcpu->arch.regs[VCPU_REGS_RCX];
2931 regs->rdx = vcpu->arch.regs[VCPU_REGS_RDX];
2932 regs->rsi = vcpu->arch.regs[VCPU_REGS_RSI];
2933 regs->rdi = vcpu->arch.regs[VCPU_REGS_RDI];
2934 regs->rsp = vcpu->arch.regs[VCPU_REGS_RSP];
2935 regs->rbp = vcpu->arch.regs[VCPU_REGS_RBP];
b6c7a5dc 2936#ifdef CONFIG_X86_64
ad312c7c
ZX		 2937 regs->r8 = vcpu->arch.regs[VCPU_REGS_R8];
2938 regs->r9 = vcpu->arch.regs[VCPU_REGS_R9];
2939 regs->r10 = vcpu->arch.regs[VCPU_REGS_R10];
2940 regs->r11 = vcpu->arch.regs[VCPU_REGS_R11];
2941 regs->r12 = vcpu->arch.regs[VCPU_REGS_R12];
2942 regs->r13 = vcpu->arch.regs[VCPU_REGS_R13];
2943 regs->r14 = vcpu->arch.regs[VCPU_REGS_R14];
2944 regs->r15 = vcpu->arch.regs[VCPU_REGS_R15];
b6c7a5dc
HB		 2945#endif
2946
ad312c7c 2947 regs->rip = vcpu->arch.rip;
b6c7a5dc
HB		 2948 regs->rflags = kvm_x86_ops->get_rflags(vcpu);
2949
2950 /*
2951 * Don't leak debug flags in case they were set for guest debugging
2952 */
2953 if (vcpu->guest_debug.enabled && vcpu->guest_debug.singlestep)
2954 regs->rflags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
2955
2956 vcpu_put(vcpu);
2957
2958 return 0;
2959}
2960
2961int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
2962{
2963 vcpu_load(vcpu);
2964
ad312c7c
ZX		 2965 vcpu->arch.regs[VCPU_REGS_RAX] = regs->rax;
2966 vcpu->arch.regs[VCPU_REGS_RBX] = regs->rbx;
2967 vcpu->arch.regs[VCPU_REGS_RCX] = regs->rcx;
2968 vcpu->arch.regs[VCPU_REGS_RDX] = regs->rdx;
2969 vcpu->arch.regs[VCPU_REGS_RSI] = regs->rsi;
2970 vcpu->arch.regs[VCPU_REGS_RDI] = regs->rdi;
2971 vcpu->arch.regs[VCPU_REGS_RSP] = regs->rsp;
2972 vcpu->arch.regs[VCPU_REGS_RBP] = regs->rbp;
b6c7a5dc 2973#ifdef CONFIG_X86_64
ad312c7c
ZX		 2974 vcpu->arch.regs[VCPU_REGS_R8] = regs->r8;
2975 vcpu->arch.regs[VCPU_REGS_R9] = regs->r9;
2976 vcpu->arch.regs[VCPU_REGS_R10] = regs->r10;
2977 vcpu->arch.regs[VCPU_REGS_R11] = regs->r11;
2978 vcpu->arch.regs[VCPU_REGS_R12] = regs->r12;
2979 vcpu->arch.regs[VCPU_REGS_R13] = regs->r13;
2980 vcpu->arch.regs[VCPU_REGS_R14] = regs->r14;
2981 vcpu->arch.regs[VCPU_REGS_R15] = regs->r15;
b6c7a5dc
HB		 2982#endif
2983
ad312c7c 2984 vcpu->arch.rip = regs->rip;
b6c7a5dc
HB		 2985 kvm_x86_ops->set_rflags(vcpu, regs->rflags);
2986
2987 kvm_x86_ops->decache_regs(vcpu);
2988
2989 vcpu_put(vcpu);
2990
2991 return 0;
2992}
2993
2994static void get_segment(struct kvm_vcpu *vcpu,
2995 struct kvm_segment *var, int seg)
2996{
14af3f3c 2997 kvm_x86_ops->get_segment(vcpu, var, seg);
b6c7a5dc
HB		 2998}
2999
3000void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3001{
3002 struct kvm_segment cs;
3003
3004 get_segment(vcpu, &cs, VCPU_SREG_CS);
3005 *db = cs.db;
3006 *l = cs.l;
3007}
3008EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
3009
3010int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
3011 struct kvm_sregs *sregs)
3012{
3013 struct descriptor_table dt;
3014 int pending_vec;
3015
3016 vcpu_load(vcpu);
3017
3018 get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
3019 get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
3020 get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
3021 get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
3022 get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
3023 get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
3024
3025 get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
3026 get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
3027
3028 kvm_x86_ops->get_idt(vcpu, &dt);
3029 sregs->idt.limit = dt.limit;
3030 sregs->idt.base = dt.base;
3031 kvm_x86_ops->get_gdt(vcpu, &dt);
3032 sregs->gdt.limit = dt.limit;
3033 sregs->gdt.base = dt.base;
3034
3035 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
ad312c7c
ZX		 3036 sregs->cr0 = vcpu->arch.cr0;
3037 sregs->cr2 = vcpu->arch.cr2;
3038 sregs->cr3 = vcpu->arch.cr3;
3039 sregs->cr4 = vcpu->arch.cr4;
2d3ad1f4 3040 sregs->cr8 = kvm_get_cr8(vcpu);
ad312c7c 3041 sregs->efer = vcpu->arch.shadow_efer;
b6c7a5dc
HB		 3042 sregs->apic_base = kvm_get_apic_base(vcpu);
3043
3044 if (irqchip_in_kernel(vcpu->kvm)) {
3045 memset(sregs->interrupt_bitmap, 0,
3046 sizeof sregs->interrupt_bitmap);
3047 pending_vec = kvm_x86_ops->get_irq(vcpu);
3048 if (pending_vec >= 0)
3049 set_bit(pending_vec,
3050 (unsigned long *)sregs->interrupt_bitmap);
3051 } else
ad312c7c 3052 memcpy(sregs->interrupt_bitmap, vcpu->arch.irq_pending,
b6c7a5dc
HB		 3053 sizeof sregs->interrupt_bitmap);
3054
3055 vcpu_put(vcpu);
3056
3057 return 0;
3058}
3059
3060static void set_segment(struct kvm_vcpu *vcpu,
3061 struct kvm_segment *var, int seg)
3062{
14af3f3c 3063 kvm_x86_ops->set_segment(vcpu, var, seg);
b6c7a5dc
HB		 3064}
3065
37817f29
IE		 3066static void seg_desct_to_kvm_desct(struct desc_struct *seg_desc, u16 selector,
3067 struct kvm_segment *kvm_desct)
3068{
3069 kvm_desct->base = seg_desc->base0;
3070 kvm_desct->base |= seg_desc->base1 << 16;
3071 kvm_desct->base |= seg_desc->base2 << 24;
3072 kvm_desct->limit = seg_desc->limit0;
3073 kvm_desct->limit |= seg_desc->limit << 16;
3074 kvm_desct->selector = selector;
3075 kvm_desct->type = seg_desc->type;
3076 kvm_desct->present = seg_desc->p;
3077 kvm_desct->dpl = seg_desc->dpl;
3078 kvm_desct->db = seg_desc->d;
3079 kvm_desct->s = seg_desc->s;
3080 kvm_desct->l = seg_desc->l;
3081 kvm_desct->g = seg_desc->g;
3082 kvm_desct->avl = seg_desc->avl;
3083 if (!selector)
3084 kvm_desct->unusable = 1;
3085 else
3086 kvm_desct->unusable = 0;
3087 kvm_desct->padding = 0;
3088}
3089
3090static void get_segment_descritptor_dtable(struct kvm_vcpu *vcpu,
3091 u16 selector,
3092 struct descriptor_table *dtable)
3093{
3094 if (selector & 1 << 2) {
3095 struct kvm_segment kvm_seg;
3096
3097 get_segment(vcpu, &kvm_seg, VCPU_SREG_LDTR);
3098
3099 if (kvm_seg.unusable)
3100 dtable->limit = 0;
3101 else
3102 dtable->limit = kvm_seg.limit;
3103 dtable->base = kvm_seg.base;
3104 }
3105 else
3106 kvm_x86_ops->get_gdt(vcpu, dtable);
3107}
3108
3109/* allowed just for 8 bytes segments */
3110static int load_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
3111 struct desc_struct *seg_desc)
3112{
3113 struct descriptor_table dtable;
3114 u16 index = selector >> 3;
3115
3116 get_segment_descritptor_dtable(vcpu, selector, &dtable);
3117
3118 if (dtable.limit < index * 8 + 7) {
3119 kvm_queue_exception_e(vcpu, GP_VECTOR, selector & 0xfffc);
3120 return 1;
3121 }
3122 return kvm_read_guest(vcpu->kvm, dtable.base + index * 8, seg_desc, 8);
3123}
3124
3125/* allowed just for 8 bytes segments */
3126static int save_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
3127 struct desc_struct *seg_desc)
3128{
3129 struct descriptor_table dtable;
3130 u16 index = selector >> 3;
3131
3132 get_segment_descritptor_dtable(vcpu, selector, &dtable);
3133
3134 if (dtable.limit < index * 8 + 7)
3135 return 1;
3136 return kvm_write_guest(vcpu->kvm, dtable.base + index * 8, seg_desc, 8);
3137}
3138
3139static u32 get_tss_base_addr(struct kvm_vcpu *vcpu,
3140 struct desc_struct *seg_desc)
3141{
3142 u32 base_addr;
3143
3144 base_addr = seg_desc->base0;
3145 base_addr |= (seg_desc->base1 << 16);
3146 base_addr |= (seg_desc->base2 << 24);
3147
3148 return base_addr;
3149}
3150
3151static int load_tss_segment32(struct kvm_vcpu *vcpu,
3152 struct desc_struct *seg_desc,
3153 struct tss_segment_32 *tss)
3154{
3155 u32 base_addr;
3156
3157 base_addr = get_tss_base_addr(vcpu, seg_desc);
3158
3159 return kvm_read_guest(vcpu->kvm, base_addr, tss,
3160 sizeof(struct tss_segment_32));
3161}
3162
3163static int save_tss_segment32(struct kvm_vcpu *vcpu,
3164 struct desc_struct *seg_desc,
3165 struct tss_segment_32 *tss)
3166{
3167 u32 base_addr;
3168
3169 base_addr = get_tss_base_addr(vcpu, seg_desc);
3170
3171 return kvm_write_guest(vcpu->kvm, base_addr, tss,
3172 sizeof(struct tss_segment_32));
3173}
3174
3175static int load_tss_segment16(struct kvm_vcpu *vcpu,
3176 struct desc_struct *seg_desc,
3177 struct tss_segment_16 *tss)
3178{
3179 u32 base_addr;
3180
3181 base_addr = get_tss_base_addr(vcpu, seg_desc);
3182
3183 return kvm_read_guest(vcpu->kvm, base_addr, tss,
3184 sizeof(struct tss_segment_16));
3185}
3186
3187static int save_tss_segment16(struct kvm_vcpu *vcpu,
3188 struct desc_struct *seg_desc,
3189 struct tss_segment_16 *tss)
3190{
3191 u32 base_addr;
3192
3193 base_addr = get_tss_base_addr(vcpu, seg_desc);
3194
3195 return kvm_write_guest(vcpu->kvm, base_addr, tss,
3196 sizeof(struct tss_segment_16));
3197}
3198
3199static u16 get_segment_selector(struct kvm_vcpu *vcpu, int seg)
3200{
3201 struct kvm_segment kvm_seg;
3202
3203 get_segment(vcpu, &kvm_seg, seg);
3204 return kvm_seg.selector;
3205}
3206
3207static int load_segment_descriptor_to_kvm_desct(struct kvm_vcpu *vcpu,
3208 u16 selector,
3209 struct kvm_segment *kvm_seg)
3210{
3211 struct desc_struct seg_desc;
3212
3213 if (load_guest_segment_descriptor(vcpu, selector, &seg_desc))
3214 return 1;
3215 seg_desct_to_kvm_desct(&seg_desc, selector, kvm_seg);
3216 return 0;
3217}
3218
3219static int load_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
3220 int type_bits, int seg)
3221{
3222 struct kvm_segment kvm_seg;
3223
3224 if (load_segment_descriptor_to_kvm_desct(vcpu, selector, &kvm_seg))
3225 return 1;
3226 kvm_seg.type |= type_bits;
3227
3228 if (seg != VCPU_SREG_SS && seg != VCPU_SREG_CS &&
3229 seg != VCPU_SREG_LDTR)
3230 if (!kvm_seg.s)
3231 kvm_seg.unusable = 1;
3232
3233 set_segment(vcpu, &kvm_seg, seg);
3234 return 0;
3235}
3236
3237static void save_state_to_tss32(struct kvm_vcpu *vcpu,
3238 struct tss_segment_32 *tss)
3239{
3240 tss->cr3 = vcpu->arch.cr3;
3241 tss->eip = vcpu->arch.rip;
3242 tss->eflags = kvm_x86_ops->get_rflags(vcpu);
3243 tss->eax = vcpu->arch.regs[VCPU_REGS_RAX];
3244 tss->ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3245 tss->edx = vcpu->arch.regs[VCPU_REGS_RDX];
3246 tss->ebx = vcpu->arch.regs[VCPU_REGS_RBX];
3247 tss->esp = vcpu->arch.regs[VCPU_REGS_RSP];
3248 tss->ebp = vcpu->arch.regs[VCPU_REGS_RBP];
3249 tss->esi = vcpu->arch.regs[VCPU_REGS_RSI];
3250 tss->edi = vcpu->arch.regs[VCPU_REGS_RDI];
3251
3252 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
3253 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
3254 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
3255 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
3256 tss->fs = get_segment_selector(vcpu, VCPU_SREG_FS);
3257 tss->gs = get_segment_selector(vcpu, VCPU_SREG_GS);
3258 tss->ldt_selector = get_segment_selector(vcpu, VCPU_SREG_LDTR);
3259 tss->prev_task_link = get_segment_selector(vcpu, VCPU_SREG_TR);
3260}
3261
3262static int load_state_from_tss32(struct kvm_vcpu *vcpu,
3263 struct tss_segment_32 *tss)
3264{
3265 kvm_set_cr3(vcpu, tss->cr3);
3266
3267 vcpu->arch.rip = tss->eip;
3268 kvm_x86_ops->set_rflags(vcpu, tss->eflags | 2);
3269
3270 vcpu->arch.regs[VCPU_REGS_RAX] = tss->eax;
3271 vcpu->arch.regs[VCPU_REGS_RCX] = tss->ecx;
3272 vcpu->arch.regs[VCPU_REGS_RDX] = tss->edx;
3273 vcpu->arch.regs[VCPU_REGS_RBX] = tss->ebx;
3274 vcpu->arch.regs[VCPU_REGS_RSP] = tss->esp;
3275 vcpu->arch.regs[VCPU_REGS_RBP] = tss->ebp;
3276 vcpu->arch.regs[VCPU_REGS_RSI] = tss->esi;
3277 vcpu->arch.regs[VCPU_REGS_RDI] = tss->edi;
3278
3279 if (load_segment_descriptor(vcpu, tss->ldt_selector, 0, VCPU_SREG_LDTR))
3280 return 1;
3281
3282 if (load_segment_descriptor(vcpu, tss->es, 1, VCPU_SREG_ES))
3283 return 1;
3284
3285 if (load_segment_descriptor(vcpu, tss->cs, 9, VCPU_SREG_CS))
3286 return 1;
3287
3288 if (load_segment_descriptor(vcpu, tss->ss, 1, VCPU_SREG_SS))
3289 return 1;
3290
3291 if (load_segment_descriptor(vcpu, tss->ds, 1, VCPU_SREG_DS))
3292 return 1;
3293
3294 if (load_segment_descriptor(vcpu, tss->fs, 1, VCPU_SREG_FS))
3295 return 1;
3296
3297 if (load_segment_descriptor(vcpu, tss->gs, 1, VCPU_SREG_GS))
3298 return 1;
3299 return 0;
3300}
3301
3302static void save_state_to_tss16(struct kvm_vcpu *vcpu,
3303 struct tss_segment_16 *tss)
3304{
3305 tss->ip = vcpu->arch.rip;
3306 tss->flag = kvm_x86_ops->get_rflags(vcpu);
3307 tss->ax = vcpu->arch.regs[VCPU_REGS_RAX];
3308 tss->cx = vcpu->arch.regs[VCPU_REGS_RCX];
3309 tss->dx = vcpu->arch.regs[VCPU_REGS_RDX];
3310 tss->bx = vcpu->arch.regs[VCPU_REGS_RBX];
3311 tss->sp = vcpu->arch.regs[VCPU_REGS_RSP];
3312 tss->bp = vcpu->arch.regs[VCPU_REGS_RBP];
3313 tss->si = vcpu->arch.regs[VCPU_REGS_RSI];
3314 tss->di = vcpu->arch.regs[VCPU_REGS_RDI];
3315
3316 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
3317 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
3318 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
3319 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
3320 tss->ldt = get_segment_selector(vcpu, VCPU_SREG_LDTR);
3321 tss->prev_task_link = get_segment_selector(vcpu, VCPU_SREG_TR);
3322}
3323
3324static int load_state_from_tss16(struct kvm_vcpu *vcpu,
3325 struct tss_segment_16 *tss)
3326{
3327 vcpu->arch.rip = tss->ip;
3328 kvm_x86_ops->set_rflags(vcpu, tss->flag | 2);
3329 vcpu->arch.regs[VCPU_REGS_RAX] = tss->ax;
3330 vcpu->arch.regs[VCPU_REGS_RCX] = tss->cx;
3331 vcpu->arch.regs[VCPU_REGS_RDX] = tss->dx;
3332 vcpu->arch.regs[VCPU_REGS_RBX] = tss->bx;
3333 vcpu->arch.regs[VCPU_REGS_RSP] = tss->sp;
3334 vcpu->arch.regs[VCPU_REGS_RBP] = tss->bp;
3335 vcpu->arch.regs[VCPU_REGS_RSI] = tss->si;
3336 vcpu->arch.regs[VCPU_REGS_RDI] = tss->di;
3337
3338 if (load_segment_descriptor(vcpu, tss->ldt, 0, VCPU_SREG_LDTR))
3339 return 1;
3340
3341 if (load_segment_descriptor(vcpu, tss->es, 1, VCPU_SREG_ES))
3342 return 1;
3343
3344 if (load_segment_descriptor(vcpu, tss->cs, 9, VCPU_SREG_CS))
3345 return 1;
3346
3347 if (load_segment_descriptor(vcpu, tss->ss, 1, VCPU_SREG_SS))
3348 return 1;
3349
3350 if (load_segment_descriptor(vcpu, tss->ds, 1, VCPU_SREG_DS))
3351 return 1;
3352 return 0;
3353}
3354
3355int kvm_task_switch_16(struct kvm_vcpu *vcpu, u16 tss_selector,
3356 struct desc_struct *cseg_desc,
3357 struct desc_struct *nseg_desc)
3358{
3359 struct tss_segment_16 tss_segment_16;
3360 int ret = 0;
3361
3362 if (load_tss_segment16(vcpu, cseg_desc, &tss_segment_16))
3363 goto out;
3364
3365 save_state_to_tss16(vcpu, &tss_segment_16);
3366 save_tss_segment16(vcpu, cseg_desc, &tss_segment_16);
3367
3368 if (load_tss_segment16(vcpu, nseg_desc, &tss_segment_16))
3369 goto out;
3370 if (load_state_from_tss16(vcpu, &tss_segment_16))
3371 goto out;
3372
3373 ret = 1;
3374out:
3375 return ret;
3376}
3377
3378int kvm_task_switch_32(struct kvm_vcpu *vcpu, u16 tss_selector,
3379 struct desc_struct *cseg_desc,
3380 struct desc_struct *nseg_desc)
3381{
3382 struct tss_segment_32 tss_segment_32;
3383 int ret = 0;
3384
3385 if (load_tss_segment32(vcpu, cseg_desc, &tss_segment_32))
3386 goto out;
3387
3388 save_state_to_tss32(vcpu, &tss_segment_32);
3389 save_tss_segment32(vcpu, cseg_desc, &tss_segment_32);
3390
3391 if (load_tss_segment32(vcpu, nseg_desc, &tss_segment_32))
3392 goto out;
3393 if (load_state_from_tss32(vcpu, &tss_segment_32))
3394 goto out;
3395
3396 ret = 1;
3397out:
3398 return ret;
3399}
3400
3401int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason)
3402{
3403 struct kvm_segment tr_seg;
3404 struct desc_struct cseg_desc;
3405 struct desc_struct nseg_desc;
3406 int ret = 0;
3407
3408 get_segment(vcpu, &tr_seg, VCPU_SREG_TR);
3409
3410 if (load_guest_segment_descriptor(vcpu, tss_selector, &nseg_desc))
3411 goto out;
3412
3413 if (load_guest_segment_descriptor(vcpu, tr_seg.selector, &cseg_desc))
3414 goto out;
3415
3416
3417 if (reason != TASK_SWITCH_IRET) {
3418 int cpl;
3419
3420 cpl = kvm_x86_ops->get_cpl(vcpu);
3421 if ((tss_selector & 3) > nseg_desc.dpl || cpl > nseg_desc.dpl) {
3422 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
3423 return 1;
3424 }
3425 }
3426
3427 if (!nseg_desc.p || (nseg_desc.limit0 | nseg_desc.limit << 16) < 0x67) {
3428 kvm_queue_exception_e(vcpu, TS_VECTOR, tss_selector & 0xfffc);
3429 return 1;
3430 }
3431
3432 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
3433 cseg_desc.type &= ~(1 << 8); //clear the B flag
3434 save_guest_segment_descriptor(vcpu, tr_seg.selector,
3435 &cseg_desc);
3436 }
3437
3438 if (reason == TASK_SWITCH_IRET) {
3439 u32 eflags = kvm_x86_ops->get_rflags(vcpu);
3440 kvm_x86_ops->set_rflags(vcpu, eflags & ~X86_EFLAGS_NT);
3441 }
3442
3443 kvm_x86_ops->skip_emulated_instruction(vcpu);
3444 kvm_x86_ops->cache_regs(vcpu);
3445
3446 if (nseg_desc.type & 8)
3447 ret = kvm_task_switch_32(vcpu, tss_selector, &cseg_desc,
3448 &nseg_desc);
3449 else
3450 ret = kvm_task_switch_16(vcpu, tss_selector, &cseg_desc,
3451 &nseg_desc);
3452
3453 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE) {
3454 u32 eflags = kvm_x86_ops->get_rflags(vcpu);
3455 kvm_x86_ops->set_rflags(vcpu, eflags | X86_EFLAGS_NT);
3456 }
3457
3458 if (reason != TASK_SWITCH_IRET) {
3459 nseg_desc.type |= (1 << 8);
3460 save_guest_segment_descriptor(vcpu, tss_selector,
3461 &nseg_desc);
3462 }
3463
3464 kvm_x86_ops->set_cr0(vcpu, vcpu->arch.cr0 | X86_CR0_TS);
3465 seg_desct_to_kvm_desct(&nseg_desc, tss_selector, &tr_seg);
3466 tr_seg.type = 11;
3467 set_segment(vcpu, &tr_seg, VCPU_SREG_TR);
3468out:
3469 kvm_x86_ops->decache_regs(vcpu);
3470 return ret;
3471}
3472EXPORT_SYMBOL_GPL(kvm_task_switch);
3473
b6c7a5dc
HB		 3474int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
3475 struct kvm_sregs *sregs)
3476{
3477 int mmu_reset_needed = 0;
3478 int i, pending_vec, max_bits;
3479 struct descriptor_table dt;
3480
3481 vcpu_load(vcpu);
3482
3483 dt.limit = sregs->idt.limit;
3484 dt.base = sregs->idt.base;
3485 kvm_x86_ops->set_idt(vcpu, &dt);
3486 dt.limit = sregs->gdt.limit;
3487 dt.base = sregs->gdt.base;
3488 kvm_x86_ops->set_gdt(vcpu, &dt);
3489
ad312c7c
ZX		 3490 vcpu->arch.cr2 = sregs->cr2;
3491 mmu_reset_needed |= vcpu->arch.cr3 != sregs->cr3;
3492 vcpu->arch.cr3 = sregs->cr3;
b6c7a5dc 3493
2d3ad1f4 3494 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 3495
ad312c7c 3496 mmu_reset_needed |= vcpu->arch.shadow_efer != sregs->efer;
b6c7a5dc 3497 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 3498 kvm_set_apic_base(vcpu, sregs->apic_base);
3499
3500 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
3501
ad312c7c 3502 mmu_reset_needed |= vcpu->arch.cr0 != sregs->cr0;
b6c7a5dc 3503 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 3504 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 3505
ad312c7c 3506 mmu_reset_needed |= vcpu->arch.cr4 != sregs->cr4;
b6c7a5dc
HB		 3507 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3508 if (!is_long_mode(vcpu) && is_pae(vcpu))
ad312c7c 3509 load_pdptrs(vcpu, vcpu->arch.cr3);
b6c7a5dc
HB		 3510
3511 if (mmu_reset_needed)
3512 kvm_mmu_reset_context(vcpu);
3513
3514 if (!irqchip_in_kernel(vcpu->kvm)) {
ad312c7c
ZX		 3515 memcpy(vcpu->arch.irq_pending, sregs->interrupt_bitmap,
3516 sizeof vcpu->arch.irq_pending);
3517 vcpu->arch.irq_summary = 0;
3518 for (i = 0; i < ARRAY_SIZE(vcpu->arch.irq_pending); ++i)
3519 if (vcpu->arch.irq_pending[i])
3520 __set_bit(i, &vcpu->arch.irq_summary);
b6c7a5dc
HB		 3521 } else {
3522 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
3523 pending_vec = find_first_bit(
3524 (const unsigned long *)sregs->interrupt_bitmap,
3525 max_bits);
3526 /* Only pending external irq is handled here */
3527 if (pending_vec < max_bits) {
3528 kvm_x86_ops->set_irq(vcpu, pending_vec);
3529 pr_debug("Set back pending irq %d\n",
3530 pending_vec);
3531 }
3532 }
3533
3534 set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
3535 set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
3536 set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
3537 set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
3538 set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
3539 set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
3540
3541 set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
3542 set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
3543
3544 vcpu_put(vcpu);
3545
3546 return 0;
3547}
3548
3549int kvm_arch_vcpu_ioctl_debug_guest(struct kvm_vcpu *vcpu,
3550 struct kvm_debug_guest *dbg)
3551{
3552 int r;
3553
3554 vcpu_load(vcpu);
3555
3556 r = kvm_x86_ops->set_guest_debug(vcpu, dbg);
3557
3558 vcpu_put(vcpu);
3559
3560 return r;
3561}
3562
d0752060
HB		 3563/*
3564 * fxsave fpu state. Taken from x86_64/processor.h. To be killed when
3565 * we have asm/x86/processor.h
3566 */
3567struct fxsave {
3568 u16 cwd;
3569 u16 swd;
3570 u16 twd;
3571 u16 fop;
3572 u64 rip;
3573 u64 rdp;
3574 u32 mxcsr;
3575 u32 mxcsr_mask;
3576 u32 st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
3577#ifdef CONFIG_X86_64
3578 u32 xmm_space[64]; /* 16*16 bytes for each XMM-reg = 256 bytes */
3579#else
3580 u32 xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */
3581#endif
3582};
3583
8b006791
ZX		 3584/*
3585 * Translate a guest virtual address to a guest physical address.
3586 */
3587int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
3588 struct kvm_translation *tr)
3589{
3590 unsigned long vaddr = tr->linear_address;
3591 gpa_t gpa;
3592
3593 vcpu_load(vcpu);
72dc67a6 3594 down_read(&vcpu->kvm->slots_lock);
ad312c7c 3595 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, vaddr);
72dc67a6 3596 up_read(&vcpu->kvm->slots_lock);
8b006791
ZX		 3597 tr->physical_address = gpa;
3598 tr->valid = gpa != UNMAPPED_GVA;
3599 tr->writeable = 1;
3600 tr->usermode = 0;
8b006791
ZX		 3601 vcpu_put(vcpu);
3602
3603 return 0;
3604}
3605
d0752060
HB		 3606int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
3607{
ad312c7c 3608 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 3609
3610 vcpu_load(vcpu);
3611
3612 memcpy(fpu->fpr, fxsave->st_space, 128);
3613 fpu->fcw = fxsave->cwd;
3614 fpu->fsw = fxsave->swd;
3615 fpu->ftwx = fxsave->twd;
3616 fpu->last_opcode = fxsave->fop;
3617 fpu->last_ip = fxsave->rip;
3618 fpu->last_dp = fxsave->rdp;
3619 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
3620
3621 vcpu_put(vcpu);
3622
3623 return 0;
3624}
3625
3626int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
3627{
ad312c7c 3628 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 3629
3630 vcpu_load(vcpu);
3631
3632 memcpy(fxsave->st_space, fpu->fpr, 128);
3633 fxsave->cwd = fpu->fcw;
3634 fxsave->swd = fpu->fsw;
3635 fxsave->twd = fpu->ftwx;
3636 fxsave->fop = fpu->last_opcode;
3637 fxsave->rip = fpu->last_ip;
3638 fxsave->rdp = fpu->last_dp;
3639 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
3640
3641 vcpu_put(vcpu);
3642
3643 return 0;
3644}
3645
3646void fx_init(struct kvm_vcpu *vcpu)
3647{
3648 unsigned after_mxcsr_mask;
3649
3650 /* Initialize guest FPU by resetting ours and saving into guest's */
3651 preempt_disable();
ad312c7c 3652 fx_save(&vcpu->arch.host_fx_image);
d0752060 3653 fpu_init();
ad312c7c
ZX		 3654 fx_save(&vcpu->arch.guest_fx_image);
3655 fx_restore(&vcpu->arch.host_fx_image);
d0752060
HB		 3656 preempt_enable();
3657
ad312c7c 3658 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 3659 after_mxcsr_mask = offsetof(struct i387_fxsave_struct, st_space);
ad312c7c
ZX		 3660 vcpu->arch.guest_fx_image.mxcsr = 0x1f80;
3661 memset((void *)&vcpu->arch.guest_fx_image + after_mxcsr_mask,
d0752060
HB		 3662 0, sizeof(struct i387_fxsave_struct) - after_mxcsr_mask);
3663}
3664EXPORT_SYMBOL_GPL(fx_init);
3665
3666void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
3667{
3668 if (!vcpu->fpu_active || vcpu->guest_fpu_loaded)
3669 return;
3670
3671 vcpu->guest_fpu_loaded = 1;
ad312c7c
ZX		 3672 fx_save(&vcpu->arch.host_fx_image);
3673 fx_restore(&vcpu->arch.guest_fx_image);
d0752060
HB		 3674}
3675EXPORT_SYMBOL_GPL(kvm_load_guest_fpu);
3676
3677void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
3678{
3679 if (!vcpu->guest_fpu_loaded)
3680 return;
3681
3682 vcpu->guest_fpu_loaded = 0;
ad312c7c
ZX		 3683 fx_save(&vcpu->arch.guest_fx_image);
3684 fx_restore(&vcpu->arch.host_fx_image);
f096ed85 3685 ++vcpu->stat.fpu_reload;
d0752060
HB		 3686}
3687EXPORT_SYMBOL_GPL(kvm_put_guest_fpu);
e9b11c17
ZX		 3688
3689void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
3690{
3691 kvm_x86_ops->vcpu_free(vcpu);
3692}
3693
3694struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
3695 unsigned int id)
3696{
26e5215f
AK		 3697 return kvm_x86_ops->vcpu_create(kvm, id);
3698}
e9b11c17 3699
26e5215f
AK		 3700int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
3701{
3702 int r;
e9b11c17
ZX		 3703
3704 /* We do fxsave: this must be aligned. */
ad312c7c 3705 BUG_ON((unsigned long)&vcpu->arch.host_fx_image & 0xF);
e9b11c17
ZX		 3706
3707 vcpu_load(vcpu);
3708 r = kvm_arch_vcpu_reset(vcpu);
3709 if (r == 0)
3710 r = kvm_mmu_setup(vcpu);
3711 vcpu_put(vcpu);
3712 if (r < 0)
3713 goto free_vcpu;
3714
26e5215f 3715 return 0;
e9b11c17
ZX		 3716free_vcpu:
3717 kvm_x86_ops->vcpu_free(vcpu);
26e5215f 3718 return r;
e9b11c17
ZX		 3719}
3720
d40ccc62 3721void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17
ZX		 3722{
3723 vcpu_load(vcpu);
3724 kvm_mmu_unload(vcpu);
3725 vcpu_put(vcpu);
3726
3727 kvm_x86_ops->vcpu_free(vcpu);
3728}
3729
3730int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
3731{
3732 return kvm_x86_ops->vcpu_reset(vcpu);
3733}
3734
3735void kvm_arch_hardware_enable(void *garbage)
3736{
3737 kvm_x86_ops->hardware_enable(garbage);
3738}
3739
3740void kvm_arch_hardware_disable(void *garbage)
3741{
3742 kvm_x86_ops->hardware_disable(garbage);
3743}
3744
3745int kvm_arch_hardware_setup(void)
3746{
3747 return kvm_x86_ops->hardware_setup();
3748}
3749
3750void kvm_arch_hardware_unsetup(void)
3751{
3752 kvm_x86_ops->hardware_unsetup();
3753}
3754
3755void kvm_arch_check_processor_compat(void *rtn)
3756{
3757 kvm_x86_ops->check_processor_compatibility(rtn);
3758}
3759
3760int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
3761{
3762 struct page *page;
3763 struct kvm *kvm;
3764 int r;
3765
3766 BUG_ON(vcpu->kvm == NULL);
3767 kvm = vcpu->kvm;
3768
ad312c7c 3769 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
e9b11c17 3770 if (!irqchip_in_kernel(kvm) || vcpu->vcpu_id == 0)
ad312c7c 3771 vcpu->arch.mp_state = VCPU_MP_STATE_RUNNABLE;
e9b11c17 3772 else
ad312c7c 3773 vcpu->arch.mp_state = VCPU_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 3774
3775 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
3776 if (!page) {
3777 r = -ENOMEM;
3778 goto fail;
3779 }
ad312c7c 3780 vcpu->arch.pio_data = page_address(page);
e9b11c17
ZX		 3781
3782 r = kvm_mmu_create(vcpu);
3783 if (r < 0)
3784 goto fail_free_pio_data;
3785
3786 if (irqchip_in_kernel(kvm)) {
3787 r = kvm_create_lapic(vcpu);
3788 if (r < 0)
3789 goto fail_mmu_destroy;
3790 }
3791
3792 return 0;
3793
3794fail_mmu_destroy:
3795 kvm_mmu_destroy(vcpu);
3796fail_free_pio_data:
ad312c7c 3797 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 3798fail:
3799 return r;
3800}
3801
3802void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
3803{
3804 kvm_free_lapic(vcpu);
3200f405 3805 down_read(&vcpu->kvm->slots_lock);
e9b11c17 3806 kvm_mmu_destroy(vcpu);
3200f405 3807 up_read(&vcpu->kvm->slots_lock);
ad312c7c 3808 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 3809}
d19a9cd2
ZX		 3810
3811struct kvm *kvm_arch_create_vm(void)
3812{
3813 struct kvm *kvm = kzalloc(sizeof(struct kvm), GFP_KERNEL);
3814
3815 if (!kvm)
3816 return ERR_PTR(-ENOMEM);
3817
f05e70ac 3818 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
d19a9cd2
ZX		 3819
3820 return kvm;
3821}
3822
3823static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
3824{
3825 vcpu_load(vcpu);
3826 kvm_mmu_unload(vcpu);
3827 vcpu_put(vcpu);
3828}
3829
3830static void kvm_free_vcpus(struct kvm *kvm)
3831{
3832 unsigned int i;
3833
3834 /*
3835 * Unpin any mmu pages first.
3836 */
3837 for (i = 0; i < KVM_MAX_VCPUS; ++i)
3838 if (kvm->vcpus[i])
3839 kvm_unload_vcpu_mmu(kvm->vcpus[i]);
3840 for (i = 0; i < KVM_MAX_VCPUS; ++i) {
3841 if (kvm->vcpus[i]) {
3842 kvm_arch_vcpu_free(kvm->vcpus[i]);
3843 kvm->vcpus[i] = NULL;
3844 }
3845 }
3846
3847}
3848
3849void kvm_arch_destroy_vm(struct kvm *kvm)
3850{
7837699f 3851 kvm_free_pit(kvm);
d7deeeb0
ZX		 3852 kfree(kvm->arch.vpic);
3853 kfree(kvm->arch.vioapic);
d19a9cd2
ZX		 3854 kvm_free_vcpus(kvm);
3855 kvm_free_physmem(kvm);
3856 kfree(kvm);
3857}
0de10343
ZX		 3858
3859int kvm_arch_set_memory_region(struct kvm *kvm,
3860 struct kvm_userspace_memory_region *mem,
3861 struct kvm_memory_slot old,
3862 int user_alloc)
3863{
3864 int npages = mem->memory_size >> PAGE_SHIFT;
3865 struct kvm_memory_slot *memslot = &kvm->memslots[mem->slot];
3866
3867 /*To keep backward compatibility with older userspace,
3868 *x86 needs to hanlde !user_alloc case.
3869 */
3870 if (!user_alloc) {
3871 if (npages && !old.rmap) {
72dc67a6 3872 down_write(&current->mm->mmap_sem);
0de10343
ZX		 3873 memslot->userspace_addr = do_mmap(NULL, 0,
3874 npages * PAGE_SIZE,
3875 PROT_READ | PROT_WRITE,
3876 MAP_SHARED | MAP_ANONYMOUS,
3877 0);
72dc67a6 3878 up_write(&current->mm->mmap_sem);
0de10343
ZX		 3879
3880 if (IS_ERR((void *)memslot->userspace_addr))
3881 return PTR_ERR((void *)memslot->userspace_addr);
3882 } else {
3883 if (!old.user_alloc && old.rmap) {
3884 int ret;
3885
72dc67a6 3886 down_write(&current->mm->mmap_sem);
0de10343
ZX		 3887 ret = do_munmap(current->mm, old.userspace_addr,
3888 old.npages * PAGE_SIZE);
72dc67a6 3889 up_write(&current->mm->mmap_sem);
0de10343
ZX		 3890 if (ret < 0)
3891 printk(KERN_WARNING
3892 "kvm_vm_ioctl_set_memory_region: "
3893 "failed to munmap memory\n");
3894 }
3895 }
3896 }
3897
f05e70ac 3898 if (!kvm->arch.n_requested_mmu_pages) {
0de10343
ZX		 3899 unsigned int nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
3900 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
3901 }
3902
3903 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
3904 kvm_flush_remote_tlbs(kvm);
3905
3906 return 0;
3907}
1d737c8a
ZX		 3908
3909int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
3910{
3911 return vcpu->arch.mp_state == VCPU_MP_STATE_RUNNABLE
3912 || vcpu->arch.mp_state == VCPU_MP_STATE_SIPI_RECEIVED;
3913}
5736199a
ZX		 3914
3915static void vcpu_kick_intr(void *info)
3916{
3917#ifdef DEBUG
3918 struct kvm_vcpu *vcpu = (struct kvm_vcpu *)info;
3919 printk(KERN_DEBUG "vcpu_kick_intr %p \n", vcpu);
3920#endif
3921}
3922
3923void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
3924{
3925 int ipi_pcpu = vcpu->cpu;
3926
3927 if (waitqueue_active(&vcpu->wq)) {
3928 wake_up_interruptible(&vcpu->wq);
3929 ++vcpu->stat.halt_wakeup;
3930 }
3931 if (vcpu->guest_mode)
3932 smp_call_function_single(ipi_pcpu, vcpu_kick_intr, vcpu, 0, 0);
3933}
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