[linux.git] / drivers / reset / Kconfig

# SPDX-License-Identifier: GPL-2.0-only
config ARCH_HAS_RESET_CONTROLLER
	bool

menuconfig RESET_CONTROLLER
	bool "Reset Controller Support"
	default y if ARCH_HAS_RESET_CONTROLLER
	help
	  Generic Reset Controller support.

	  This framework is designed to abstract reset handling of devices
	  via GPIOs or SoC-internal reset controller modules.

	  If unsure, say no.

if RESET_CONTROLLER

config RESET_A10SR
	tristate "Altera Arria10 System Resource Reset"
	depends on MFD_ALTERA_A10SR || COMPILE_TEST
	help
	  This option enables support for the external reset functions for
	  peripheral PHYs on the Altera Arria10 System Resource Chip.

config RESET_ATH79
	bool "AR71xx Reset Driver" if COMPILE_TEST
	default ATH79
	help
	  This enables the ATH79 reset controller driver that supports the
	  AR71xx SoC reset controller.

config RESET_AXS10X
	bool "AXS10x Reset Driver" if COMPILE_TEST
	default ARC_PLAT_AXS10X
	help
	  This enables the reset controller driver for AXS10x.

config RESET_BCM6345
	bool "BCM6345 Reset Controller"
	depends on BMIPS_GENERIC || COMPILE_TEST
	default BMIPS_GENERIC
	help
	  This enables the reset controller driver for BCM6345 SoCs.

config RESET_BERLIN
	tristate "Berlin Reset Driver"
	depends on ARCH_BERLIN || COMPILE_TEST
	default m if ARCH_BERLIN
	help
	  This enables the reset controller driver for Marvell Berlin SoCs.

config RESET_BRCMSTB
	tristate "Broadcom STB reset controller"
	depends on ARCH_BRCMSTB || COMPILE_TEST
	default ARCH_BRCMSTB
	help
	  This enables the reset controller driver for Broadcom STB SoCs using
	  a SUN_TOP_CTRL_SW_INIT style controller.

config RESET_BRCMSTB_RESCAL
	tristate "Broadcom STB RESCAL reset controller"
	depends on HAS_IOMEM
	depends on ARCH_BRCMSTB || COMPILE_TEST
	default ARCH_BRCMSTB
	help
	  This enables the RESCAL reset controller for SATA, PCIe0, or PCIe1 on
	  BCM7216.

config RESET_HSDK
	bool "Synopsys HSDK Reset Driver"
	depends on HAS_IOMEM
	depends on ARC_SOC_HSDK || COMPILE_TEST
	help
	  This enables the reset controller driver for HSDK board.

config RESET_IMX7
	tristate "i.MX7/8 Reset Driver"
	depends on HAS_IOMEM
	depends on SOC_IMX7D || (ARM64 && ARCH_MXC) || COMPILE_TEST
	default y if SOC_IMX7D
	select MFD_SYSCON
	help
	  This enables the reset controller driver for i.MX7 SoCs.

config RESET_INTEL_GW
	bool "Intel Reset Controller Driver"
	depends on X86 || COMPILE_TEST
	depends on OF && HAS_IOMEM
	select REGMAP_MMIO
	help
	  This enables the reset controller driver for Intel Gateway SoCs.
	  Say Y to control the reset signals provided by reset controller.
	  Otherwise, say N.

config RESET_K210
	bool "Reset controller driver for Canaan Kendryte K210 SoC"
	depends on (SOC_CANAAN || COMPILE_TEST) && OF
	select MFD_SYSCON
	default SOC_CANAAN
	help
	  Support for the Canaan Kendryte K210 RISC-V SoC reset controller.
	  Say Y if you want to control reset signals provided by this
	  controller.

config RESET_LANTIQ
	bool "Lantiq XWAY Reset Driver" if COMPILE_TEST
	default SOC_TYPE_XWAY
	help
	  This enables the reset controller driver for Lantiq / Intel XWAY SoCs.

config RESET_LPC18XX
	bool "LPC18xx/43xx Reset Driver" if COMPILE_TEST
	default ARCH_LPC18XX
	help
	  This enables the reset controller driver for NXP LPC18xx/43xx SoCs.

config RESET_MCHP_SPARX5
	bool "Microchip Sparx5 reset driver"
	depends on ARCH_SPARX5 || SOC_LAN966 || COMPILE_TEST
	default y if SPARX5_SWITCH
	select MFD_SYSCON
	help
	  This driver supports switch core reset for the Microchip Sparx5 SoC.

config RESET_MESON
	tristate "Meson Reset Driver"
	depends on ARCH_MESON || COMPILE_TEST
	default ARCH_MESON
	help
	  This enables the reset driver for Amlogic Meson SoCs.

config RESET_MESON_AUDIO_ARB
	tristate "Meson Audio Memory Arbiter Reset Driver"
	depends on ARCH_MESON || COMPILE_TEST
	help
	  This enables the reset driver for Audio Memory Arbiter of
	  Amlogic's A113 based SoCs

config RESET_NPCM
	bool "NPCM BMC Reset Driver" if COMPILE_TEST
	default ARCH_NPCM
	help
	  This enables the reset controller driver for Nuvoton NPCM
	  BMC SoCs.

config RESET_NUVOTON_MA35D1
	bool "Nuvoton MA35D1 Reset Driver"
	depends on ARCH_MA35 || COMPILE_TEST
	default ARCH_MA35
	help
	  This enables the reset controller driver for Nuvoton MA35D1 SoC.

config RESET_PISTACHIO
	bool "Pistachio Reset Driver"
	depends on MIPS || COMPILE_TEST
	help
	  This enables the reset driver for ImgTec Pistachio SoCs.

config RESET_POLARFIRE_SOC
	bool "Microchip PolarFire SoC (MPFS) Reset Driver"
	depends on MCHP_CLK_MPFS
	select AUXILIARY_BUS
	default MCHP_CLK_MPFS
	help
	  This driver supports peripheral reset for the Microchip PolarFire SoC

config RESET_QCOM_AOSS
	tristate "Qcom AOSS Reset Driver"
	depends on ARCH_QCOM || COMPILE_TEST
	help
	  This enables the AOSS (always on subsystem) reset driver
	  for Qualcomm SDM845 SoCs. Say Y if you want to control
	  reset signals provided by AOSS for Modem, Venus, ADSP,
	  GPU, Camera, Wireless, Display subsystem. Otherwise, say N.

config RESET_QCOM_PDC
	tristate "Qualcomm PDC Reset Driver"
	depends on ARCH_QCOM || COMPILE_TEST
	help
	  This enables the PDC (Power Domain Controller) reset driver
	  for Qualcomm Technologies Inc SDM845 SoCs. Say Y if you want
	  to control reset signals provided by PDC for Modem, Compute,
	  Display, GPU, Debug, AOP, Sensors, Audio, SP and APPS.

config RESET_RASPBERRYPI
	tristate "Raspberry Pi 4 Firmware Reset Driver"
	depends on RASPBERRYPI_FIRMWARE || (RASPBERRYPI_FIRMWARE=n && COMPILE_TEST)
	default USB_XHCI_PCI
	help
	  Raspberry Pi 4's co-processor controls some of the board's HW
	  initialization process, but it's up to Linux to trigger it when
	  relevant. This driver provides a reset controller capable of
	  interfacing with RPi4's co-processor and model these firmware
	  initialization routines as reset lines.

config RESET_RZG2L_USBPHY_CTRL
	tristate "Renesas RZ/G2L USBPHY control driver"
	depends on ARCH_RZG2L || COMPILE_TEST
	help
	  Support for USBPHY Control found on RZ/G2L family. It mainly
	  controls reset and power down of the USB/PHY.

config RESET_SCMI
	tristate "Reset driver controlled via ARM SCMI interface"
	depends on ARM_SCMI_PROTOCOL || COMPILE_TEST
	default ARM_SCMI_PROTOCOL
	help
	  This driver provides support for reset signal/domains that are
	  controlled by firmware that implements the SCMI interface.

	  This driver uses SCMI Message Protocol to interact with the
	  firmware controlling all the reset signals.

config RESET_SIMPLE
	bool "Simple Reset Controller Driver" if COMPILE_TEST || EXPERT
	default ARCH_ASPEED || ARCH_BCMBCA || ARCH_BITMAIN || ARCH_REALTEK || ARCH_STM32 || (ARCH_INTEL_SOCFPGA && ARM64) || ARCH_SUNXI || ARC
	depends on HAS_IOMEM
	help
	  This enables a simple reset controller driver for reset lines that
	  that can be asserted and deasserted by toggling bits in a contiguous,
	  exclusive register space.

	  Currently this driver supports:
	   - Altera SoCFPGAs
	   - ASPEED BMC SoCs
	   - Bitmain BM1880 SoC
	   - Realtek SoCs
	   - RCC reset controller in STM32 MCUs
	   - Allwinner SoCs
	   - SiFive FU740 SoCs

config RESET_SOCFPGA
	bool "SoCFPGA Reset Driver" if COMPILE_TEST && (!ARM || !ARCH_INTEL_SOCFPGA)
	default ARM && ARCH_INTEL_SOCFPGA
	select RESET_SIMPLE
	help
	  This enables the reset driver for the SoCFPGA ARMv7 platforms. This
	  driver gets initialized early during platform init calls.

config RESET_SUNPLUS
	bool "Sunplus SoCs Reset Driver" if COMPILE_TEST
	default ARCH_SUNPLUS
	help
	  This enables the reset driver support for Sunplus SoCs.
	  The reset lines that can be asserted and deasserted by toggling bits
	  in a contiguous, exclusive register space. The register is HIWORD_MASKED,
	  which means each register holds 16 reset lines.

config RESET_SUNXI
	bool "Allwinner SoCs Reset Driver" if COMPILE_TEST && !ARCH_SUNXI
	default ARCH_SUNXI
	select RESET_SIMPLE
	help
	  This enables the reset driver for Allwinner SoCs.

config RESET_TI_SCI
	tristate "TI System Control Interface (TI-SCI) reset driver"
	depends on TI_SCI_PROTOCOL || (COMPILE_TEST && TI_SCI_PROTOCOL=n)
	help
	  This enables the reset driver support over TI System Control Interface
	  available on some new TI's SoCs. If you wish to use reset resources
	  managed by the TI System Controller, say Y here. Otherwise, say N.

config RESET_TI_SYSCON
	tristate "TI SYSCON Reset Driver"
	depends on HAS_IOMEM
	select MFD_SYSCON
	help
	  This enables the reset driver support for TI devices with
	  memory-mapped reset registers as part of a syscon device node. If
	  you wish to use the reset framework for such memory-mapped devices,
	  say Y here. Otherwise, say N.

config RESET_TI_TPS380X
	tristate "TI TPS380x Reset Driver"
	select GPIOLIB
	help
	  This enables the reset driver support for TI TPS380x devices. If
	  you wish to use the reset framework for such devices, say Y here.
	  Otherwise, say N.

config RESET_TN48M_CPLD
	tristate "Delta Networks TN48M switch CPLD reset controller"
	depends on MFD_TN48M_CPLD || COMPILE_TEST
	default MFD_TN48M_CPLD
	help
	  This enables the reset controller driver for the Delta TN48M CPLD.
	  It provides reset signals for Armada 7040 and 385 SoC-s, Alleycat 3X
	  switch MAC-s, Alaska OOB ethernet PHY, Quad Alaska ethernet PHY-s and
	  Microchip PD69200 PoE PSE controller.

	  This driver can also be built as a module. If so, the module will be
	  called reset-tn48m.

config RESET_UNIPHIER
	tristate "Reset controller driver for UniPhier SoCs"
	depends on ARCH_UNIPHIER || COMPILE_TEST
	depends on OF && MFD_SYSCON
	default ARCH_UNIPHIER
	help
	  Support for reset controllers on UniPhier SoCs.
	  Say Y if you want to control reset signals provided by System Control
	  block, Media I/O block, Peripheral Block.

config RESET_UNIPHIER_GLUE
	tristate "Reset driver in glue layer for UniPhier SoCs"
	depends on (ARCH_UNIPHIER || COMPILE_TEST) && OF
	default ARCH_UNIPHIER
	select RESET_SIMPLE
	help
	  Support for peripheral core reset included in its own glue layer
	  on UniPhier SoCs. Say Y if you want to control reset signals
	  provided by the glue layer.

config RESET_ZYNQ
	bool "ZYNQ Reset Driver" if COMPILE_TEST
	default ARCH_ZYNQ
	help
	  This enables the reset controller driver for Xilinx Zynq SoCs.

source "drivers/reset/starfive/Kconfig"
source "drivers/reset/sti/Kconfig"
source "drivers/reset/hisilicon/Kconfig"
source "drivers/reset/tegra/Kconfig"

endif
Commit	Line	Data
ec8f24b7	1	# SPDX-License-Identifier: GPL-2.0-only
61fc4131 PZ	2	config ARCH_HAS_RESET_CONTROLLER
	3	bool
	4
	5	menuconfig RESET_CONTROLLER
	6	bool "Reset Controller Support"
	7	default y if ARCH_HAS_RESET_CONTROLLER
	8	help
	9	Generic Reset Controller support.
	10
	11	This framework is designed to abstract reset handling of devices
	12	via GPIOs or SoC-internal reset controller modules.
	13
	14	If unsure, say no.
e5d76075	15
998cd463 MY	16	if RESET_CONTROLLER
998cd463 MY	17
62700682 TT	18	config RESET_A10SR
62700682 TT	19	tristate "Altera Arria10 System Resource Reset"
af19f193	20	depends on MFD_ALTERA_A10SR \|\| COMPILE_TEST
62700682 TT	21	help
	22	This option enables support for the external reset functions for
	23	peripheral PHYs on the Altera Arria10 System Resource Chip.
	24
e27b4a6e PZ	25	config RESET_ATH79
	26	bool "AR71xx Reset Driver" if COMPILE_TEST
	27	default ATH79
	28	help
	29	This enables the ATH79 reset controller driver that supports the
	30	AR71xx SoC reset controller.
	31
37634923 EP	32	config RESET_AXS10X
	33	bool "AXS10x Reset Driver" if COMPILE_TEST
	34	default ARC_PLAT_AXS10X
	35	help
	36	This enables the reset controller driver for AXS10x.
	37
aac02543 ÁFR	38	config RESET_BCM6345
	39	bool "BCM6345 Reset Controller"
	40	depends on BMIPS_GENERIC \|\| COMPILE_TEST
	41	default BMIPS_GENERIC
	42	help
	43	This enables the reset controller driver for BCM6345 SoCs.
	44
70d467ea	45	config RESET_BERLIN
5e787cdf JZ	46	tristate "Berlin Reset Driver"
	47	depends on ARCH_BERLIN \|\| COMPILE_TEST
	48	default m if ARCH_BERLIN
70d467ea PZ	49	help
	50	This enables the reset controller driver for Marvell Berlin SoCs.
	51
77750bc0 FF	52	config RESET_BRCMSTB
	53	tristate "Broadcom STB reset controller"
	54	depends on ARCH_BRCMSTB \|\| COMPILE_TEST
	55	default ARCH_BRCMSTB
	56	help
	57	This enables the reset controller driver for Broadcom STB SoCs using
	58	a SUN_TOP_CTRL_SW_INIT style controller.
	59
4cf176e5	60	config RESET_BRCMSTB_RESCAL
5694ca29	61	tristate "Broadcom STB RESCAL reset controller"
7fbcc535	62	depends on HAS_IOMEM
42f6a76f GU	63	depends on ARCH_BRCMSTB \|\| COMPILE_TEST
42f6a76f GU	64	default ARCH_BRCMSTB
4cf176e5 JQ	65	help
	66	This enables the RESCAL reset controller for SATA, PCIe0, or PCIe1 on
	67	BCM7216.
	68
13541226 VG	69	config RESET_HSDK
13541226 VG	70	bool "Synopsys HSDK Reset Driver"
2d48a237	71	depends on HAS_IOMEM
544e3bf4	72	depends on ARC_SOC_HSDK \|\| COMPILE_TEST
e0be864f	73	help
13541226	74	This enables the reset controller driver for HSDK board.
e0be864f	75
abf97755	76	config RESET_IMX7
a442abbb	77	tristate "i.MX7/8 Reset Driver"
8fa56620	78	depends on HAS_IOMEM
a442abbb AH	79	depends on SOC_IMX7D \|\| (ARM64 && ARCH_MXC) \|\| COMPILE_TEST
a442abbb AH	80	default y if SOC_IMX7D
abf97755 AS	81	select MFD_SYSCON
	82	help
	83	This enables the reset controller driver for i.MX7 SoCs.
	84
c9aef213 DK	85	config RESET_INTEL_GW
c9aef213 DK	86	bool "Intel Reset Controller Driver"
6ab9d621	87	depends on X86 \|\| COMPILE_TEST
b460e0a9	88	depends on OF && HAS_IOMEM
c9aef213 DK	89	select REGMAP_MMIO
	90	help
	91	This enables the reset controller driver for Intel Gateway SoCs.
	92	Say Y to control the reset signals provided by reset controller.
	93	Otherwise, say N.
	94
5a2308da DLM	95	config RESET_K210
	96	bool "Reset controller driver for Canaan Kendryte K210 SoC"
	97	depends on (SOC_CANAAN \|\| COMPILE_TEST) && OF
	98	select MFD_SYSCON
	99	default SOC_CANAAN
	100	help
	101	Support for the Canaan Kendryte K210 RISC-V SoC reset controller.
	102	Say Y if you want to control reset signals provided by this
	103	controller.
	104
79797b6f MB	105	config RESET_LANTIQ
	106	bool "Lantiq XWAY Reset Driver" if COMPILE_TEST
	107	default SOC_TYPE_XWAY
	108	help
	109	This enables the reset controller driver for Lantiq / Intel XWAY SoCs.
	110
cd7f4b81 PZ	111	config RESET_LPC18XX
	112	bool "LPC18xx/43xx Reset Driver" if COMPILE_TEST
	113	default ARCH_LPC18XX
	114	help
	115	This enables the reset controller driver for NXP LPC18xx/43xx SoCs.
	116
453ed428 SH	117	config RESET_MCHP_SPARX5
453ed428 SH	118	bool "Microchip Sparx5 reset driver"
8c81620a	119	depends on ARCH_SPARX5 \|\| SOC_LAN966 \|\| COMPILE_TEST
453ed428 SH	120	default y if SPARX5_SWITCH
	121	select MFD_SYSCON
	122	help
	123	This driver supports switch core reset for the Microchip Sparx5 SoC.
	124
44336c24	125	config RESET_MESON
3bfe8933 NA	126	tristate "Meson Reset Driver"
3bfe8933 NA	127	depends on ARCH_MESON \|\| COMPILE_TEST
44336c24 PZ	128	default ARCH_MESON
	129	help
	130	This enables the reset driver for Amlogic Meson SoCs.
	131
d903779b JB	132	config RESET_MESON_AUDIO_ARB
	133	tristate "Meson Audio Memory Arbiter Reset Driver"
	134	depends on ARCH_MESON \|\| COMPILE_TEST
	135	help
	136	This enables the reset driver for Audio Memory Arbiter of
	137	Amlogic's A113 based SoCs
	138
9c81b2cc TM	139	config RESET_NPCM
	140	bool "NPCM BMC Reset Driver" if COMPILE_TEST
	141	default ARCH_NPCM
	142	help
	143	This enables the reset controller driver for Nuvoton NPCM
	144	BMC SoCs.
	145
e4bb55d6	146	config RESET_NUVOTON_MA35D1
aead1076 GU	147	bool "Nuvoton MA35D1 Reset Driver"
	148	depends on ARCH_MA35 \|\| COMPILE_TEST
	149	default ARCH_MA35
e4bb55d6 JH	150	help
	151	This enables the reset controller driver for Nuvoton MA35D1 SoC.
	152
fab3f730	153	config RESET_PISTACHIO
4af16070 GU	154	bool "Pistachio Reset Driver"
4af16070 GU	155	depends on MIPS \|\| COMPILE_TEST
fab3f730 PZ	156	help
	157	This enables the reset driver for ImgTec Pistachio SoCs.
	158
05f9e363 CD	159	config RESET_POLARFIRE_SOC
05f9e363 CD	160	bool "Microchip PolarFire SoC (MPFS) Reset Driver"
afb39e2b PZ	161	depends on MCHP_CLK_MPFS
afb39e2b PZ	162	select AUXILIARY_BUS
05f9e363 CD	163	default MCHP_CLK_MPFS
	164	help
	165	This driver supports peripheral reset for the Microchip PolarFire SoC
	166
5ecb0651	167	config RESET_QCOM_AOSS
e2d5e833	168	tristate "Qcom AOSS Reset Driver"
5ecb0651 SS	169	depends on ARCH_QCOM \|\| COMPILE_TEST
	170	help
	171	This enables the AOSS (always on subsystem) reset driver
	172	for Qualcomm SDM845 SoCs. Say Y if you want to control
	173	reset signals provided by AOSS for Modem, Venus, ADSP,
	174	GPU, Camera, Wireless, Display subsystem. Otherwise, say N.
	175
eea2926b SS	176	config RESET_QCOM_PDC
	177	tristate "Qualcomm PDC Reset Driver"
	178	depends on ARCH_QCOM \|\| COMPILE_TEST
	179	help
	180	This enables the PDC (Power Domain Controller) reset driver
	181	for Qualcomm Technologies Inc SDM845 SoCs. Say Y if you want
	182	to control reset signals provided by PDC for Modem, Compute,
	183	Display, GPU, Debug, AOP, Sensors, Audio, SP and APPS.
	184
abffc82a NSJ	185	config RESET_RASPBERRYPI
	186	tristate "Raspberry Pi 4 Firmware Reset Driver"
	187	depends on RASPBERRYPI_FIRMWARE \|\| (RASPBERRYPI_FIRMWARE=n && COMPILE_TEST)
	188	default USB_XHCI_PCI
	189	help
	190	Raspberry Pi 4's co-processor controls some of the board's HW
	191	initialization process, but it's up to Linux to trigger it when
	192	relevant. This driver provides a reset controller capable of
	193	interfacing with RPi4's co-processor and model these firmware
	194	initialization routines as reset lines.
	195
bee08559 BD	196	config RESET_RZG2L_USBPHY_CTRL
bee08559 BD	197	tristate "Renesas RZ/G2L USBPHY control driver"
9fe7dd4e	198	depends on ARCH_RZG2L \|\| COMPILE_TEST
bee08559 BD	199	help
	200	Support for USBPHY Control found on RZ/G2L family. It mainly
	201	controls reset and power down of the USB/PHY.
	202
c8ae9c2d SH	203	config RESET_SCMI
	204	tristate "Reset driver controlled via ARM SCMI interface"
	205	depends on ARM_SCMI_PROTOCOL \|\| COMPILE_TEST
	206	default ARM_SCMI_PROTOCOL
	207	help
	208	This driver provides support for reset signal/domains that are
	209	controlled by firmware that implements the SCMI interface.
	210
	211	This driver uses SCMI Message Protocol to interact with the
	212	firmware controlling all the reset signals.
	213
81c22ad0	214	config RESET_SIMPLE
18d1909b	215	bool "Simple Reset Controller Driver" if COMPILE_TEST \|\| EXPERT
7bb49d77	216	default ARCH_ASPEED \|\| ARCH_BCMBCA \|\| ARCH_BITMAIN \|\| ARCH_REALTEK \|\| ARCH_STM32 \|\| (ARCH_INTEL_SOCFPGA && ARM64) \|\| ARCH_SUNXI \|\| ARC
c4ada3ca	217	depends on HAS_IOMEM
81c22ad0 PZ	218	help
	219	This enables a simple reset controller driver for reset lines that
	220	that can be asserted and deasserted by toggling bits in a contiguous,
	221	exclusive register space.
	222
1d7592f8 JS	223	Currently this driver supports:
	224	- Altera SoCFPGAs
	225	- ASPEED BMC SoCs
5ac33eeb	226	- Bitmain BM1880 SoC
3ab831e5	227	- Realtek SoCs
1d7592f8 JS	228	- RCC reset controller in STM32 MCUs
1d7592f8 JS	229	- Allwinner SoCs
e4d368e0	230	- SiFive FU740 SoCs
7e0e901d	231
b3ca9888	232	config RESET_SOCFPGA
225c13f0 KK	233	bool "SoCFPGA Reset Driver" if COMPILE_TEST && (!ARM \|\| !ARCH_INTEL_SOCFPGA)
225c13f0 KK	234	default ARM && ARCH_INTEL_SOCFPGA
b3ca9888 DN	235	select RESET_SIMPLE
	236	help
	237	This enables the reset driver for the SoCFPGA ARMv7 platforms. This
	238	driver gets initialized early during platform init calls.
	239
dbf018be QJ	240	config RESET_SUNPLUS
	241	bool "Sunplus SoCs Reset Driver" if COMPILE_TEST
	242	default ARCH_SUNPLUS
	243	help
	244	This enables the reset driver support for Sunplus SoCs.
	245	The reset lines that can be asserted and deasserted by toggling bits
	246	in a contiguous, exclusive register space. The register is HIWORD_MASKED,
	247	which means each register holds 16 reset lines.
	248
0ae08419 PZ	249	config RESET_SUNXI
	250	bool "Allwinner SoCs Reset Driver" if COMPILE_TEST && !ARCH_SUNXI
	251	default ARCH_SUNXI
e13c205a	252	select RESET_SIMPLE
0ae08419 PZ	253	help
	254	This enables the reset driver for Allwinner SoCs.
	255
28df169b AD	256	config RESET_TI_SCI
28df169b AD	257	tristate "TI System Control Interface (TI-SCI) reset driver"
13678f3f	258	depends on TI_SCI_PROTOCOL \|\| (COMPILE_TEST && TI_SCI_PROTOCOL=n)
28df169b AD	259	help
	260	This enables the reset driver support over TI System Control Interface
	261	available on some new TI's SoCs. If you wish to use reset resources
	262	managed by the TI System Controller, say Y here. Otherwise, say N.
	263
dd9bf863	264	config RESET_TI_SYSCON
cc7c2bb1 AD	265	tristate "TI SYSCON Reset Driver"
	266	depends on HAS_IOMEM
	267	select MFD_SYSCON
	268	help
	269	This enables the reset driver support for TI devices with
	270	memory-mapped reset registers as part of a syscon device node. If
	271	you wish to use the reset framework for such memory-mapped devices,
	272	say Y here. Otherwise, say N.
	273
8a4e6154 MF	274	config RESET_TI_TPS380X
	275	tristate "TI TPS380x Reset Driver"
	276	select GPIOLIB
	277	help
	278	This enables the reset driver support for TI TPS380x devices. If
	279	you wish to use the reset framework for such devices, say Y here.
	280	Otherwise, say N.
	281
5cd3921d RM	282	config RESET_TN48M_CPLD
	283	tristate "Delta Networks TN48M switch CPLD reset controller"
	284	depends on MFD_TN48M_CPLD \|\| COMPILE_TEST
	285	default MFD_TN48M_CPLD
	286	help
	287	This enables the reset controller driver for the Delta TN48M CPLD.
	288	It provides reset signals for Armada 7040 and 385 SoC-s, Alleycat 3X
	289	switch MAC-s, Alaska OOB ethernet PHY, Quad Alaska ethernet PHY-s and
	290	Microchip PD69200 PoE PSE controller.
	291
	292	This driver can also be built as a module. If so, the module will be
	293	called reset-tn48m.
	294
54e991b5 MY	295	config RESET_UNIPHIER
	296	tristate "Reset controller driver for UniPhier SoCs"
	297	depends on ARCH_UNIPHIER \|\| COMPILE_TEST
	298	depends on OF && MFD_SYSCON
	299	default ARCH_UNIPHIER
	300	help
	301	Support for reset controllers on UniPhier SoCs.
	302	Say Y if you want to control reset signals provided by System Control
	303	block, Media I/O block, Peripheral Block.
	304
3eb8f765 KH	305	config RESET_UNIPHIER_GLUE
3eb8f765 KH	306	tristate "Reset driver in glue layer for UniPhier SoCs"
499fef09 KH	307	depends on (ARCH_UNIPHIER \|\| COMPILE_TEST) && OF
	308	default ARCH_UNIPHIER
	309	select RESET_SIMPLE
	310	help
3eb8f765 KH	311	Support for peripheral core reset included in its own glue layer
	312	on UniPhier SoCs. Say Y if you want to control reset signals
	313	provided by the glue layer.
499fef09	314
6f51b860 PZ	315	config RESET_ZYNQ
	316	bool "ZYNQ Reset Driver" if COMPILE_TEST
	317	default ARCH_ZYNQ
	318	help
	319	This enables the reset controller driver for Xilinx Zynq SoCs.
	320
69bfec75	321	source "drivers/reset/starfive/Kconfig"
e5d76075	322	source "drivers/reset/sti/Kconfig"
f59d23c2	323	source "drivers/reset/hisilicon/Kconfig"
dc606c52	324	source "drivers/reset/tegra/Kconfig"
998cd463 MY	325
998cd463 MY	326	endif