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99c513f6 1/* Renesas RL78 specific support for 32-bit ELF.
219d1afa 2 Copyright (C) 2011-2018 Free Software Foundation, Inc.
99c513f6
DD		 3
4 This file is part of BFD, the Binary File Descriptor library.
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3 of the License, or
9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
863f7a5f
NC		 18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
99c513f6
DD		 20
21#include "sysdep.h"
22#include "bfd.h"
23#include "bfd_stdint.h"
24#include "libbfd.h"
25#include "elf-bfd.h"
26#include "elf/rl78.h"
27#include "libiberty.h"
28
29#define valid_16bit_address(v) ((v) <= 0x0ffff || (v) >= 0xf0000)
30
31#define RL78REL(n,sz,bit,shift,complain,pcrel) \
32 HOWTO (R_RL78_##n, shift, sz, bit, pcrel, 0, complain_overflow_ ## complain, \
33 bfd_elf_generic_reloc, "R_RL78_" #n, FALSE, 0, ~0, FALSE)
34
6ff71e76
NC		 35static bfd_reloc_status_type rl78_special_reloc (bfd *, arelent *, asymbol *, void *,
36 asection *, bfd *, char **);
37
38/* FIXME: We could omit the SHIFT parameter, it is always zero. */
39#define RL78_OP_REL(n,sz,bit,shift,complain,pcrel) \
40 HOWTO (R_RL78_##n, shift, sz, bit, pcrel, 0, complain_overflow_ ## complain, \
41 rl78_special_reloc, "R_RL78_" #n, FALSE, 0, ~0, FALSE)
42
99c513f6
DD		 43/* Note that the relocations around 0x7f are internal to this file;
44 feel free to move them as needed to avoid conflicts with published
45 relocation numbers. */
46
47static reloc_howto_type rl78_elf_howto_table [] =
48{
07d6d2b8
AM		 49 RL78REL (NONE, 3, 0, 0, dont, FALSE),
50 RL78REL (DIR32, 2, 32, 0, signed, FALSE),
51 RL78REL (DIR24S, 2, 24, 0, signed, FALSE),
52 RL78REL (DIR16, 1, 16, 0, dont, FALSE),
53 RL78REL (DIR16U, 1, 16, 0, unsigned, FALSE),
54 RL78REL (DIR16S, 1, 16, 0, signed, FALSE),
55 RL78REL (DIR8, 0, 8, 0, dont, FALSE),
56 RL78REL (DIR8U, 0, 8, 0, unsigned, FALSE),
57 RL78REL (DIR8S, 0, 8, 0, signed, FALSE),
99c513f6
DD		 58 RL78REL (DIR24S_PCREL, 2, 24, 0, signed, TRUE),
59 RL78REL (DIR16S_PCREL, 1, 16, 0, signed, TRUE),
07d6d2b8
AM		 60 RL78REL (DIR8S_PCREL, 0, 8, 0, signed, TRUE),
61 RL78REL (DIR16UL, 1, 16, 2, unsigned, FALSE),
62 RL78REL (DIR16UW, 1, 16, 1, unsigned, FALSE),
63 RL78REL (DIR8UL, 0, 8, 2, unsigned, FALSE),
64 RL78REL (DIR8UW, 0, 8, 1, unsigned, FALSE),
65 RL78REL (DIR32_REV, 1, 16, 0, dont, FALSE),
66 RL78REL (DIR16_REV, 1, 16, 0, dont, FALSE),
67 RL78REL (DIR3U_PCREL, 0, 3, 0, dont, TRUE),
99c513f6
DD		 68
69 EMPTY_HOWTO (0x13),
70 EMPTY_HOWTO (0x14),
71 EMPTY_HOWTO (0x15),
72 EMPTY_HOWTO (0x16),
73 EMPTY_HOWTO (0x17),
74 EMPTY_HOWTO (0x18),
75 EMPTY_HOWTO (0x19),
76 EMPTY_HOWTO (0x1a),
77 EMPTY_HOWTO (0x1b),
78 EMPTY_HOWTO (0x1c),
79 EMPTY_HOWTO (0x1d),
80 EMPTY_HOWTO (0x1e),
81 EMPTY_HOWTO (0x1f),
82
83 EMPTY_HOWTO (0x20),
84 EMPTY_HOWTO (0x21),
85 EMPTY_HOWTO (0x22),
86 EMPTY_HOWTO (0x23),
87 EMPTY_HOWTO (0x24),
88 EMPTY_HOWTO (0x25),
89 EMPTY_HOWTO (0x26),
90 EMPTY_HOWTO (0x27),
91 EMPTY_HOWTO (0x28),
92 EMPTY_HOWTO (0x29),
93 EMPTY_HOWTO (0x2a),
94 EMPTY_HOWTO (0x2b),
95 EMPTY_HOWTO (0x2c),
07d6d2b8 96 RL78REL (RH_RELAX, 0, 0, 0, dont, FALSE),
99c513f6
DD		 97
98 EMPTY_HOWTO (0x2e),
07d6d2b8 99 RL78REL (RH_SADDR, 0, 0, 0, dont, FALSE),
99c513f6
DD		 100 EMPTY_HOWTO (0x30),
101 EMPTY_HOWTO (0x31),
102 EMPTY_HOWTO (0x32),
103 EMPTY_HOWTO (0x33),
104 EMPTY_HOWTO (0x34),
105 EMPTY_HOWTO (0x35),
106 EMPTY_HOWTO (0x36),
107 EMPTY_HOWTO (0x37),
108 EMPTY_HOWTO (0x38),
109 EMPTY_HOWTO (0x39),
110 EMPTY_HOWTO (0x3a),
111 EMPTY_HOWTO (0x3b),
112 EMPTY_HOWTO (0x3c),
113 EMPTY_HOWTO (0x3d),
114 EMPTY_HOWTO (0x3e),
115 EMPTY_HOWTO (0x3f),
116 EMPTY_HOWTO (0x40),
117
07d6d2b8
AM		 118 RL78_OP_REL (ABS32, 2, 32, 0, dont, FALSE),
119 RL78_OP_REL (ABS24S, 2, 24, 0, signed, FALSE),
120 RL78_OP_REL (ABS16, 1, 16, 0, dont, FALSE),
121 RL78_OP_REL (ABS16U, 1, 16, 0, unsigned, FALSE),
122 RL78_OP_REL (ABS16S, 1, 16, 0, signed, FALSE),
123 RL78_OP_REL (ABS8, 0, 8, 0, dont, FALSE),
124 RL78_OP_REL (ABS8U, 0, 8, 0, unsigned, FALSE),
125 RL78_OP_REL (ABS8S, 0, 8, 0, signed, FALSE),
126 RL78_OP_REL (ABS24S_PCREL, 2, 24, 0, signed, TRUE),
127 RL78_OP_REL (ABS16S_PCREL, 1, 16, 0, signed, TRUE),
128 RL78_OP_REL (ABS8S_PCREL, 0, 8, 0, signed, TRUE),
129 RL78_OP_REL (ABS16UL, 1, 16, 0, unsigned, FALSE),
130 RL78_OP_REL (ABS16UW, 1, 16, 0, unsigned, FALSE),
131 RL78_OP_REL (ABS8UL, 0, 8, 0, unsigned, FALSE),
132 RL78_OP_REL (ABS8UW, 0, 8, 0, unsigned, FALSE),
133 RL78_OP_REL (ABS32_REV, 2, 32, 0, dont, FALSE),
134 RL78_OP_REL (ABS16_REV, 1, 16, 0, dont, FALSE),
99c513f6
DD		 135
136#define STACK_REL_P(x) ((x) <= R_RL78_ABS16_REV && (x) >= R_RL78_ABS32)
137
138 EMPTY_HOWTO (0x52),
139 EMPTY_HOWTO (0x53),
140 EMPTY_HOWTO (0x54),
141 EMPTY_HOWTO (0x55),
142 EMPTY_HOWTO (0x56),
143 EMPTY_HOWTO (0x57),
144 EMPTY_HOWTO (0x58),
145 EMPTY_HOWTO (0x59),
146 EMPTY_HOWTO (0x5a),
147 EMPTY_HOWTO (0x5b),
148 EMPTY_HOWTO (0x5c),
149 EMPTY_HOWTO (0x5d),
150 EMPTY_HOWTO (0x5e),
151 EMPTY_HOWTO (0x5f),
152 EMPTY_HOWTO (0x60),
153 EMPTY_HOWTO (0x61),
154 EMPTY_HOWTO (0x62),
155 EMPTY_HOWTO (0x63),
156 EMPTY_HOWTO (0x64),
157 EMPTY_HOWTO (0x65),
158 EMPTY_HOWTO (0x66),
159 EMPTY_HOWTO (0x67),
160 EMPTY_HOWTO (0x68),
161 EMPTY_HOWTO (0x69),
162 EMPTY_HOWTO (0x6a),
163 EMPTY_HOWTO (0x6b),
164 EMPTY_HOWTO (0x6c),
165 EMPTY_HOWTO (0x6d),
166 EMPTY_HOWTO (0x6e),
167 EMPTY_HOWTO (0x6f),
168 EMPTY_HOWTO (0x70),
169 EMPTY_HOWTO (0x71),
170 EMPTY_HOWTO (0x72),
171 EMPTY_HOWTO (0x73),
172 EMPTY_HOWTO (0x74),
173 EMPTY_HOWTO (0x75),
174 EMPTY_HOWTO (0x76),
175 EMPTY_HOWTO (0x77),
176
177 EMPTY_HOWTO (0x78),
178 EMPTY_HOWTO (0x79),
179 EMPTY_HOWTO (0x7a),
180 EMPTY_HOWTO (0x7b),
181 EMPTY_HOWTO (0x7c),
182 EMPTY_HOWTO (0x7d),
183 EMPTY_HOWTO (0x7e),
184 EMPTY_HOWTO (0x7f),
185
07d6d2b8
AM		 186 RL78_OP_REL (SYM, 2, 32, 0, dont, FALSE),
187 RL78_OP_REL (OPneg, 2, 32, 0, dont, FALSE),
188 RL78_OP_REL (OPadd, 2, 32, 0, dont, FALSE),
189 RL78_OP_REL (OPsub, 2, 32, 0, dont, FALSE),
190 RL78_OP_REL (OPmul, 2, 32, 0, dont, FALSE),
191 RL78_OP_REL (OPdiv, 2, 32, 0, dont, FALSE),
192 RL78_OP_REL (OPshla, 2, 32, 0, dont, FALSE),
193 RL78_OP_REL (OPshra, 2, 32, 0, dont, FALSE),
6ff71e76 194 RL78_OP_REL (OPsctsize, 2, 32, 0, dont, FALSE),
99c513f6
DD		 195 EMPTY_HOWTO (0x89),
196 EMPTY_HOWTO (0x8a),
197 EMPTY_HOWTO (0x8b),
198 EMPTY_HOWTO (0x8c),
6ff71e76 199 RL78_OP_REL (OPscttop, 2, 32, 0, dont, FALSE),
99c513f6
DD		 200 EMPTY_HOWTO (0x8e),
201 EMPTY_HOWTO (0x8f),
07d6d2b8
AM		 202 RL78_OP_REL (OPand, 2, 32, 0, dont, FALSE),
203 RL78_OP_REL (OPor, 2, 32, 0, dont, FALSE),
204 RL78_OP_REL (OPxor, 2, 32, 0, dont, FALSE),
205 RL78_OP_REL (OPnot, 2, 32, 0, dont, FALSE),
206 RL78_OP_REL (OPmod, 2, 32, 0, dont, FALSE),
6ff71e76
NC		 207 RL78_OP_REL (OPromtop, 2, 32, 0, dont, FALSE),
208 RL78_OP_REL (OPramtop, 2, 32, 0, dont, FALSE)
99c513f6
DD		 209};
210\f
211/* Map BFD reloc types to RL78 ELF reloc types. */
212
213struct rl78_reloc_map
214{
215 bfd_reloc_code_real_type bfd_reloc_val;
07d6d2b8 216 unsigned int rl78_reloc_val;
99c513f6
DD		 217};
218
219static const struct rl78_reloc_map rl78_reloc_map [] =
220{
221 { BFD_RELOC_NONE, R_RL78_NONE },
222 { BFD_RELOC_8, R_RL78_DIR8S },
223 { BFD_RELOC_16, R_RL78_DIR16S },
224 { BFD_RELOC_24, R_RL78_DIR24S },
225 { BFD_RELOC_32, R_RL78_DIR32 },
226 { BFD_RELOC_RL78_16_OP, R_RL78_DIR16 },
227 { BFD_RELOC_RL78_DIR3U_PCREL, R_RL78_DIR3U_PCREL },
228 { BFD_RELOC_8_PCREL, R_RL78_DIR8S_PCREL },
229 { BFD_RELOC_16_PCREL, R_RL78_DIR16S_PCREL },
230 { BFD_RELOC_24_PCREL, R_RL78_DIR24S_PCREL },
231 { BFD_RELOC_RL78_8U, R_RL78_DIR8U },
232 { BFD_RELOC_RL78_16U, R_RL78_DIR16U },
233 { BFD_RELOC_RL78_SYM, R_RL78_SYM },
234 { BFD_RELOC_RL78_OP_SUBTRACT, R_RL78_OPsub },
235 { BFD_RELOC_RL78_OP_NEG, R_RL78_OPneg },
236 { BFD_RELOC_RL78_OP_AND, R_RL78_OPand },
237 { BFD_RELOC_RL78_OP_SHRA, R_RL78_OPshra },
238 { BFD_RELOC_RL78_ABS8, R_RL78_ABS8 },
239 { BFD_RELOC_RL78_ABS16, R_RL78_ABS16 },
240 { BFD_RELOC_RL78_ABS16_REV, R_RL78_ABS16_REV },
241 { BFD_RELOC_RL78_ABS32, R_RL78_ABS32 },
242 { BFD_RELOC_RL78_ABS32_REV, R_RL78_ABS32_REV },
243 { BFD_RELOC_RL78_ABS16UL, R_RL78_ABS16UL },
244 { BFD_RELOC_RL78_ABS16UW, R_RL78_ABS16UW },
9cea966c 245 { BFD_RELOC_RL78_ABS16U, R_RL78_ABS16U },
54f66250 246 { BFD_RELOC_RL78_SADDR, R_RL78_RH_SADDR },
9cea966c 247 { BFD_RELOC_RL78_RELAX, R_RL78_RH_RELAX }
99c513f6
DD		 248};
249
250static reloc_howto_type *
251rl78_reloc_type_lookup (bfd * abfd ATTRIBUTE_UNUSED,
252 bfd_reloc_code_real_type code)
253{
254 unsigned int i;
255
256 if (code == BFD_RELOC_RL78_32_OP)
257 return rl78_elf_howto_table + R_RL78_DIR32;
258
0ba38529 259 for (i = ARRAY_SIZE (rl78_reloc_map); i--;)
99c513f6
DD		 260 if (rl78_reloc_map [i].bfd_reloc_val == code)
261 return rl78_elf_howto_table + rl78_reloc_map[i].rl78_reloc_val;
262
263 return NULL;
264}
265
266static reloc_howto_type *
267rl78_reloc_name_lookup (bfd * abfd ATTRIBUTE_UNUSED, const char * r_name)
268{
269 unsigned int i;
270
271 for (i = 0; i < ARRAY_SIZE (rl78_elf_howto_table); i++)
272 if (rl78_elf_howto_table[i].name != NULL
273 && strcasecmp (rl78_elf_howto_table[i].name, r_name) == 0)
274 return rl78_elf_howto_table + i;
275
276 return NULL;
277}
278
279/* Set the howto pointer for an RL78 ELF reloc. */
280
281static void
07d6d2b8
AM		 282rl78_info_to_howto_rela (bfd * abfd ATTRIBUTE_UNUSED,
283 arelent * cache_ptr,
99c513f6
DD		 284 Elf_Internal_Rela * dst)
285{
286 unsigned int r_type;
287
288 r_type = ELF32_R_TYPE (dst->r_info);
5860e3f8
NC		 289 if (r_type >= (unsigned int) R_RL78_max)
290 {
695344c0 291 /* xgettext:c-format */
0aa13fee
AM		 292 _bfd_error_handler (_("%pB: unsupported relocation type %#x"),
293 abfd, r_type);
5860e3f8
NC		 294 r_type = 0;
295 }
99c513f6
DD		 296 cache_ptr->howto = rl78_elf_howto_table + r_type;
297}
298\f
299static bfd_vma
07d6d2b8 300get_symbol_value (const char * name,
99c513f6 301 struct bfd_link_info * info,
07d6d2b8
AM		 302 bfd * input_bfd,
303 asection * input_section,
99c513f6
DD		 304 int offset)
305{
99c513f6
DD		 306 struct bfd_link_hash_entry * h;
307
6ff71e76
NC		 308 if (info == NULL)
309 return 0;
310
99c513f6
DD		 311 h = bfd_link_hash_lookup (info->hash, name, FALSE, FALSE, TRUE);
312
313 if (h == NULL
314 || (h->type != bfd_link_hash_defined
315 && h->type != bfd_link_hash_defweak))
6ff71e76 316 {
1a72702b 317 (*info->callbacks->undefined_symbol)
6ff71e76 318 (info, name, input_bfd, input_section, offset, TRUE);
6ff71e76
NC		 319 return 0;
320 }
99c513f6 321
6ff71e76
NC		 322 return (h->u.def.value
323 + h->u.def.section->output_section->vma
324 + h->u.def.section->output_offset);
99c513f6
DD		 325}
326
327static bfd_vma
1a72702b 328get_romstart (struct bfd_link_info * info,
07d6d2b8
AM		 329 bfd * abfd,
330 asection * sec,
99c513f6
DD		 331 int offset)
332{
333 static bfd_boolean cached = FALSE;
334 static bfd_vma cached_value = 0;
335
336 if (!cached)
337 {
1a72702b 338 cached_value = get_symbol_value ("_start", info, abfd, sec, offset);
99c513f6
DD		 339 cached = TRUE;
340 }
341 return cached_value;
342}
343
344static bfd_vma
1a72702b 345get_ramstart (struct bfd_link_info * info,
07d6d2b8
AM		 346 bfd * abfd,
347 asection * sec,
99c513f6
DD		 348 int offset)
349{
350 static bfd_boolean cached = FALSE;
351 static bfd_vma cached_value = 0;
352
353 if (!cached)
354 {
1a72702b 355 cached_value = get_symbol_value ("__datastart", info, abfd, sec, offset);
99c513f6
DD		 356 cached = TRUE;
357 }
358 return cached_value;
359}
360
361#define NUM_STACK_ENTRIES 16
362static int32_t rl78_stack [ NUM_STACK_ENTRIES ];
363static unsigned int rl78_stack_top;
364
365#define RL78_STACK_PUSH(val) \
366 do \
367 { \
368 if (rl78_stack_top < NUM_STACK_ENTRIES) \
07d6d2b8 369 rl78_stack [rl78_stack_top ++] = (val); \
99c513f6 370 else \
38f14ab8 371 _bfd_error_handler (_("internal error: RL78 reloc stack overflow")); \
99c513f6
DD		 372 } \
373 while (0)
374
375#define RL78_STACK_POP(dest) \
376 do \
377 { \
378 if (rl78_stack_top > 0) \
07d6d2b8 379 (dest) = rl78_stack [-- rl78_stack_top];\
99c513f6 380 else \
6ff71e76 381 { \
38f14ab8 382 _bfd_error_handler (_("internal error: RL78 reloc stack underflow")); \
07d6d2b8
AM		 383 (dest) = 0; \
384 } \
99c513f6
DD		 385 } \
386 while (0)
387
6ff71e76
NC		 388/* Special handling for RL78 complex relocs. Returns the
389 value of the reloc, or 0 for relocs which do not generate
390 a result. SYMVAL is the value of the symbol for relocs
391 which use a symbolic argument. */
392
393static bfd_vma
394rl78_compute_complex_reloc (unsigned long r_type,
07d6d2b8
AM		 395 bfd_vma symval,
396 asection * input_section)
6ff71e76
NC		 397{
398 int32_t tmp1, tmp2;
399 bfd_vma relocation;
400
401 switch (r_type)
402 {
403 default:
404 return 0;
405
406 case R_RL78_ABS24S_PCREL:
407 case R_RL78_ABS16S_PCREL:
408 case R_RL78_ABS8S_PCREL:
409 RL78_STACK_POP (relocation);
410 relocation -= input_section->output_section->vma + input_section->output_offset;
411 return relocation;
412
413 case R_RL78_ABS32:
414 case R_RL78_ABS32_REV:
415 case R_RL78_ABS16:
416 case R_RL78_ABS16_REV:
417 case R_RL78_ABS16S:
418 case R_RL78_ABS16U:
419 case R_RL78_ABS8:
420 case R_RL78_ABS8U:
421 case R_RL78_ABS8S:
422 RL78_STACK_POP (relocation);
423 return relocation;
424
425 case R_RL78_ABS16UL:
426 case R_RL78_ABS8UL:
427 RL78_STACK_POP (relocation);
428 return relocation >> 2;
429
430 case R_RL78_ABS16UW:
431 case R_RL78_ABS8UW:
432 RL78_STACK_POP (relocation);
433 return relocation >> 1;
434
435 /* The rest of the relocs compute values and then push them onto the stack. */
436 case R_RL78_OPramtop:
437 case R_RL78_OPromtop:
438 case R_RL78_SYM:
439 RL78_STACK_PUSH (symval);
440 return 0;
1b786873 441
6ff71e76
NC		 442 case R_RL78_OPneg:
443 RL78_STACK_POP (tmp1);
444 tmp1 = - tmp1;
445 RL78_STACK_PUSH (tmp1);
446 return 0;
447
448 case R_RL78_OPadd:
449 RL78_STACK_POP (tmp2);
450 RL78_STACK_POP (tmp1);
451 tmp1 += tmp2;
452 RL78_STACK_PUSH (tmp1);
453 return 0;
454
455 case R_RL78_OPsub:
456 /* For the expression "A - B", the assembler pushes A,
457 then B, then OPSUB. So the first op we pop is B, not A. */
458 RL78_STACK_POP (tmp2); /* B */
459 RL78_STACK_POP (tmp1); /* A */
460 tmp1 -= tmp2; /* A - B */
461 RL78_STACK_PUSH (tmp1);
462 return 0;
463
464 case R_RL78_OPmul:
465 RL78_STACK_POP (tmp2);
466 RL78_STACK_POP (tmp1);
467 tmp1 *= tmp2;
468 RL78_STACK_PUSH (tmp1);
469 return 0;
470
471 case R_RL78_OPdiv:
472 RL78_STACK_POP (tmp2);
473 RL78_STACK_POP (tmp1);
474 tmp1 /= tmp2;
475 RL78_STACK_PUSH (tmp1);
476 return 0;
477
478 case R_RL78_OPshla:
479 RL78_STACK_POP (tmp2);
480 RL78_STACK_POP (tmp1);
481 tmp1 <<= tmp2;
482 RL78_STACK_PUSH (tmp1);
483 return 0;
484
485 case R_RL78_OPshra:
486 RL78_STACK_POP (tmp2);
487 RL78_STACK_POP (tmp1);
488 tmp1 >>= tmp2;
489 RL78_STACK_PUSH (tmp1);
490 return 0;
491
492 case R_RL78_OPsctsize:
493 RL78_STACK_PUSH (input_section->size);
494 return 0;
495
496 case R_RL78_OPscttop:
497 RL78_STACK_PUSH (input_section->output_section->vma);
498 return 0;
499
500 case R_RL78_OPand:
501 RL78_STACK_POP (tmp2);
502 RL78_STACK_POP (tmp1);
503 tmp1 &= tmp2;
504 RL78_STACK_PUSH (tmp1);
505 return 0;
506
507 case R_RL78_OPor:
508 RL78_STACK_POP (tmp2);
509 RL78_STACK_POP (tmp1);
510 tmp1 |= tmp2;
511 RL78_STACK_PUSH (tmp1);
512 return 0;
513
514 case R_RL78_OPxor:
515 RL78_STACK_POP (tmp2);
516 RL78_STACK_POP (tmp1);
517 tmp1 ^= tmp2;
518 RL78_STACK_PUSH (tmp1);
519 return 0;
520
521 case R_RL78_OPnot:
522 RL78_STACK_POP (tmp1);
523 tmp1 = ~ tmp1;
524 RL78_STACK_PUSH (tmp1);
525 return 0;
526
527 case R_RL78_OPmod:
528 RL78_STACK_POP (tmp2);
529 RL78_STACK_POP (tmp1);
530 tmp1 %= tmp2;
531 RL78_STACK_PUSH (tmp1);
532 return 0;
533 }
534}
535
536#undef RL78_STACK_PUSH
537#undef RL78_STACK_POP
538
539#define OP(i) (contents[reloc->address + (i)])
540
541static bfd_reloc_status_type
542rl78_special_reloc (bfd * input_bfd,
543 arelent * reloc,
544 asymbol * symbol,
545 void * data,
546 asection * input_section,
547 bfd * output_bfd ATTRIBUTE_UNUSED,
548 char ** error_message ATTRIBUTE_UNUSED)
549{
07d6d2b8
AM		 550 bfd_reloc_status_type r = bfd_reloc_ok;
551 bfd_vma relocation = 0;
552 unsigned long r_type = reloc->howto->type;
553 bfd_byte * contents = data;
6ff71e76
NC		 554
555 /* If necessary, compute the symbolic value of the relocation. */
556 switch (r_type)
557 {
558 case R_RL78_SYM:
559 relocation = (symbol->value
560 + symbol->section->output_section->vma
561 + symbol->section->output_offset
562 + reloc->addend);
563 break;
564
565 case R_RL78_OPromtop:
1a72702b 566 relocation = get_romstart (NULL, input_bfd, input_section,
6ff71e76
NC		 567 reloc->address);
568 break;
569
570 case R_RL78_OPramtop:
1a72702b 571 relocation = get_ramstart (NULL, input_bfd, input_section,
6ff71e76
NC		 572 reloc->address);
573 break;
574 }
575
576 /* Get the value of the relocation. */
577 relocation = rl78_compute_complex_reloc (r_type, relocation, input_section);
578
579 /* If the relocation alters the contents of the section then apply it now.
580 Note - since this function is called from
581 bfd_generic_get_relocated_section_contents via bfd_perform_relocation,
582 and not from the linker, we do not perform any range checking. The
583 clients who are calling us are only interested in some relocated section
584 contents, and not any linkage problems that might occur later. */
585 switch (r_type)
586 {
587 case R_RL78_ABS32:
588 OP (0) = relocation;
589 OP (1) = relocation >> 8;
590 OP (2) = relocation >> 16;
591 OP (3) = relocation >> 24;
592 break;
593
594 case R_RL78_ABS32_REV:
595 OP (3) = relocation;
596 OP (2) = relocation >> 8;
597 OP (1) = relocation >> 16;
598 OP (0) = relocation >> 24;
599 break;
600
601 case R_RL78_ABS24S_PCREL:
602 case R_RL78_ABS24S:
603 OP (0) = relocation;
604 OP (1) = relocation >> 8;
605 OP (2) = relocation >> 16;
606 break;
607
608 case R_RL78_ABS16_REV:
609 OP (1) = relocation;
610 OP (0) = relocation >> 8;
611 break;
612
613 case R_RL78_ABS16S_PCREL:
614 case R_RL78_ABS16:
615 case R_RL78_ABS16S:
616 case R_RL78_ABS16U:
617 case R_RL78_ABS16UL:
618 case R_RL78_ABS16UW:
619 OP (0) = relocation;
620 OP (1) = relocation >> 8;
621 break;
622
623 case R_RL78_ABS8S_PCREL:
624 case R_RL78_ABS8:
625 case R_RL78_ABS8U:
626 case R_RL78_ABS8UL:
627 case R_RL78_ABS8UW:
628 case R_RL78_ABS8S:
629 OP (0) = relocation;
630 break;
631
632 default:
633 break;
634 }
635
636 return r;
637}
638
639#undef OP
640#define OP(i) (contents[rel->r_offset + (i)])
641
99c513f6
DD		 642/* Relocate an RL78 ELF section.
643 There is some attempt to make this function usable for many architectures,
644 both USE_REL and USE_RELA ['twould be nice if such a critter existed],
645 if only to serve as a learning tool.
646
647 The RELOCATE_SECTION function is called by the new ELF backend linker
648 to handle the relocations for a section.
649
650 The relocs are always passed as Rela structures; if the section
651 actually uses Rel structures, the r_addend field will always be
652 zero.
653
654 This function is responsible for adjusting the section contents as
655 necessary, and (if using Rela relocs and generating a relocatable
656 output file) adjusting the reloc addend as necessary.
657
658 This function does not have to worry about setting the reloc
659 address or the reloc symbol index.
660
661 LOCAL_SYMS is a pointer to the swapped in local symbols.
662
663 LOCAL_SECTIONS is an array giving the section in the input file
664 corresponding to the st_shndx field of each local symbol.
665
666 The global hash table entry for the global symbols can be found
667 via elf_sym_hashes (input_bfd).
668
669 When generating relocatable output, this function must handle
670 STB_LOCAL/STT_SECTION symbols specially. The output symbol is
671 going to be the section symbol corresponding to the output
672 section, which means that the addend must be adjusted
673 accordingly. */
674
675static bfd_boolean
676rl78_elf_relocate_section
07d6d2b8 677 (bfd * output_bfd,
99c513f6 678 struct bfd_link_info * info,
07d6d2b8
AM		 679 bfd * input_bfd,
680 asection * input_section,
681 bfd_byte * contents,
99c513f6 682 Elf_Internal_Rela * relocs,
07d6d2b8
AM		 683 Elf_Internal_Sym * local_syms,
684 asection ** local_sections)
99c513f6 685{
07d6d2b8 686 Elf_Internal_Shdr * symtab_hdr;
99c513f6 687 struct elf_link_hash_entry ** sym_hashes;
07d6d2b8
AM		 688 Elf_Internal_Rela * rel;
689 Elf_Internal_Rela * relend;
99c513f6
DD		 690 asection *splt;
691
692 symtab_hdr = & elf_tdata (input_bfd)->symtab_hdr;
693 sym_hashes = elf_sym_hashes (input_bfd);
694 relend = relocs + input_section->reloc_count;
695
ce558b89 696 splt = elf_hash_table (info)->splt;
99c513f6
DD		 697
698 for (rel = relocs; rel < relend; rel ++)
699 {
07d6d2b8
AM		 700 reloc_howto_type * howto;
701 unsigned long r_symndx;
702 Elf_Internal_Sym * sym;
703 asection * sec;
99c513f6 704 struct elf_link_hash_entry * h;
07d6d2b8
AM		 705 bfd_vma relocation;
706 bfd_reloc_status_type r;
707 const char * name = NULL;
708 bfd_boolean unresolved_reloc = TRUE;
709 int r_type;
99c513f6
DD		 710
711 r_type = ELF32_R_TYPE (rel->r_info);
712 r_symndx = ELF32_R_SYM (rel->r_info);
713
714 howto = rl78_elf_howto_table + ELF32_R_TYPE (rel->r_info);
07d6d2b8 715 h = NULL;
99c513f6
DD		 716 sym = NULL;
717 sec = NULL;
718 relocation = 0;
719
720 if (r_symndx < symtab_hdr->sh_info)
721 {
722 sym = local_syms + r_symndx;
723 sec = local_sections [r_symndx];
724 relocation = _bfd_elf_rela_local_sym (output_bfd, sym, & sec, rel);
725
726 name = bfd_elf_string_from_elf_section
727 (input_bfd, symtab_hdr->sh_link, sym->st_name);
728 name = (sym->st_name == 0) ? bfd_section_name (input_bfd, sec) : name;
729 }
730 else
731 {
62d887d4
L		 732 bfd_boolean warned ATTRIBUTE_UNUSED;
733 bfd_boolean ignored ATTRIBUTE_UNUSED;
99c513f6
DD		 734
735 RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel,
736 r_symndx, symtab_hdr, sym_hashes, h,
737 sec, relocation, unresolved_reloc,
62d887d4 738 warned, ignored);
99c513f6
DD		 739
740 name = h->root.root.string;
741 }
742
95b57ade 743 if (sec != NULL && discarded_section (sec))
99c513f6 744 RELOC_AGAINST_DISCARDED_SECTION (info, input_bfd, input_section,
545fd46b 745 rel, 1, relend, howto, 0, contents);
99c513f6 746
0e1862bb 747 if (bfd_link_relocatable (info))
99c513f6
DD		 748 {
749 /* This is a relocatable link. We don't have to change
07d6d2b8
AM		 750 anything, unless the reloc is against a section symbol,
751 in which case we have to adjust according to where the
752 section symbol winds up in the output section. */
99c513f6
DD		 753 if (sym != NULL && ELF_ST_TYPE (sym->st_info) == STT_SECTION)
754 rel->r_addend += sec->output_offset;
755 continue;
756 }
757
758 switch (ELF32_R_TYPE (rel->r_info))
759 {
760 case R_RL78_DIR16S:
761 {
762 bfd_vma *plt_offset;
763
764 if (h != NULL)
765 plt_offset = &h->plt.offset;
766 else
767 plt_offset = elf_local_got_offsets (input_bfd) + r_symndx;
768
9cea966c 769 if (! valid_16bit_address (relocation))
99c513f6 770 {
99c513f6
DD		 771 /* If this is the first time we've processed this symbol,
772 fill in the plt entry with the correct symbol address. */
773 if ((*plt_offset & 1) == 0)
774 {
775 unsigned int x;
776
777 x = 0x000000ec; /* br !!abs24 */
778 x |= (relocation << 8) & 0xffffff00;
779 bfd_put_32 (input_bfd, x, splt->contents + *plt_offset);
780 *plt_offset |= 1;
781 }
782
783 relocation = (splt->output_section->vma
784 + splt->output_offset
785 + (*plt_offset & -2));
786 if (name)
787 {
788 char *newname = bfd_malloc (strlen(name)+5);
789 strcpy (newname, name);
790 strcat(newname, ".plt");
791 _bfd_generic_link_add_one_symbol (info,
792 input_bfd,
793 newname,
794 BSF_FUNCTION | BSF_WEAK,
795 splt,
796 (*plt_offset & -2),
797 0,
798 1,
799 0,
800 0);
801 }
802 }
803 }
804 break;
805 }
806
807 if (h != NULL && h->root.type == bfd_link_hash_undefweak)
808 /* If the symbol is undefined and weak
809 then the relocation resolves to zero. */
810 relocation = 0;
811 else
812 {
813 if (howto->pc_relative)
814 {
815 relocation -= (input_section->output_section->vma
816 + input_section->output_offset
817 + rel->r_offset);
818 relocation -= bfd_get_reloc_size (howto);
819 }
820
821 relocation += rel->r_addend;
822 }
823
824 r = bfd_reloc_ok;
825
826#define RANGE(a,b) if (a > (long) relocation || (long) relocation > b) r = bfd_reloc_overflow
99c513f6
DD		 827
828 /* Opcode relocs are always big endian. Data relocs are bi-endian. */
829 switch (r_type)
830 {
831 case R_RL78_NONE:
832 break;
833
9cea966c
DD		 834 case R_RL78_RH_RELAX:
835 break;
836
99c513f6
DD		 837 case R_RL78_DIR8S_PCREL:
838 RANGE (-128, 127);
839 OP (0) = relocation;
840 break;
841
842 case R_RL78_DIR8S:
843 RANGE (-128, 255);
844 OP (0) = relocation;
845 break;
846
847 case R_RL78_DIR8U:
848 RANGE (0, 255);
849 OP (0) = relocation;
850 break;
851
852 case R_RL78_DIR16S_PCREL:
853 RANGE (-32768, 32767);
854 OP (0) = relocation;
855 OP (1) = relocation >> 8;
856 break;
857
858 case R_RL78_DIR16S:
859 if ((relocation & 0xf0000) == 0xf0000)
860 relocation &= 0xffff;
861 RANGE (-32768, 65535);
862 OP (0) = relocation;
863 OP (1) = relocation >> 8;
864 break;
865
866 case R_RL78_DIR16U:
867 RANGE (0, 65536);
868 OP (0) = relocation;
869 OP (1) = relocation >> 8;
870 break;
871
872 case R_RL78_DIR16:
873 RANGE (-32768, 65536);
874 OP (0) = relocation;
875 OP (1) = relocation >> 8;
876 break;
877
878 case R_RL78_DIR16_REV:
879 RANGE (-32768, 65536);
880 OP (1) = relocation;
881 OP (0) = relocation >> 8;
882 break;
883
884 case R_RL78_DIR3U_PCREL:
885 RANGE (3, 10);
886 OP (0) &= 0xf8;
887 OP (0) |= relocation & 0x07;
888 break;
889
890 case R_RL78_DIR24S_PCREL:
891 RANGE (-0x800000, 0x7fffff);
892 OP (0) = relocation;
893 OP (1) = relocation >> 8;
894 OP (2) = relocation >> 16;
895 break;
896
897 case R_RL78_DIR24S:
898 RANGE (-0x800000, 0x7fffff);
899 OP (0) = relocation;
900 OP (1) = relocation >> 8;
901 OP (2) = relocation >> 16;
902 break;
903
904 case R_RL78_DIR32:
905 OP (0) = relocation;
906 OP (1) = relocation >> 8;
907 OP (2) = relocation >> 16;
908 OP (3) = relocation >> 24;
909 break;
910
911 case R_RL78_DIR32_REV:
912 OP (3) = relocation;
913 OP (2) = relocation >> 8;
914 OP (1) = relocation >> 16;
915 OP (0) = relocation >> 24;
916 break;
917
9cea966c 918 case R_RL78_RH_SFR:
9cea966c
DD		 919 RANGE (0xfff00, 0xfffff);
920 OP (0) = relocation & 0xff;
921 break;
922
923 case R_RL78_RH_SADDR:
9cea966c
DD		 924 RANGE (0xffe20, 0xfff1f);
925 OP (0) = relocation & 0xff;
9cea966c
DD		 926 break;
927
99c513f6 928 /* Complex reloc handling: */
99c513f6 929 case R_RL78_ABS32:
99c513f6 930 case R_RL78_ABS32_REV:
99c513f6
DD		 931 case R_RL78_ABS24S_PCREL:
932 case R_RL78_ABS24S:
99c513f6 933 case R_RL78_ABS16:
99c513f6 934 case R_RL78_ABS16_REV:
99c513f6
DD		 935 case R_RL78_ABS16S_PCREL:
936 case R_RL78_ABS16S:
99c513f6 937 case R_RL78_ABS16U:
99c513f6 938 case R_RL78_ABS16UL:
99c513f6 939 case R_RL78_ABS16UW:
99c513f6 940 case R_RL78_ABS8:
99c513f6 941 case R_RL78_ABS8U:
99c513f6 942 case R_RL78_ABS8UL:
99c513f6 943 case R_RL78_ABS8UW:
99c513f6
DD		 944 case R_RL78_ABS8S_PCREL:
945 case R_RL78_ABS8S:
99c513f6 946 case R_RL78_OPneg:
99c513f6 947 case R_RL78_OPadd:
99c513f6 948 case R_RL78_OPsub:
99c513f6 949 case R_RL78_OPmul:
99c513f6 950 case R_RL78_OPdiv:
99c513f6 951 case R_RL78_OPshla:
99c513f6 952 case R_RL78_OPshra:
99c513f6 953 case R_RL78_OPsctsize:
99c513f6 954 case R_RL78_OPscttop:
99c513f6 955 case R_RL78_OPand:
6ff71e76
NC		 956 case R_RL78_OPor:
957 case R_RL78_OPxor:
958 case R_RL78_OPnot:
959 case R_RL78_OPmod:
960 relocation = rl78_compute_complex_reloc (r_type, 0, input_section);
99c513f6 961
6ff71e76
NC		 962 switch (r_type)
963 {
964 case R_RL78_ABS32:
965 OP (0) = relocation;
966 OP (1) = relocation >> 8;
967 OP (2) = relocation >> 16;
968 OP (3) = relocation >> 24;
969 break;
99c513f6 970
6ff71e76
NC		 971 case R_RL78_ABS32_REV:
972 OP (3) = relocation;
973 OP (2) = relocation >> 8;
974 OP (1) = relocation >> 16;
975 OP (0) = relocation >> 24;
976 break;
99c513f6 977
6ff71e76
NC		 978 case R_RL78_ABS24S_PCREL:
979 case R_RL78_ABS24S:
980 RANGE (-0x800000, 0x7fffff);
981 OP (0) = relocation;
982 OP (1) = relocation >> 8;
983 OP (2) = relocation >> 16;
984 break;
99c513f6 985
6ff71e76
NC		 986 case R_RL78_ABS16:
987 RANGE (-32768, 65535);
988 OP (0) = relocation;
989 OP (1) = relocation >> 8;
990 break;
99c513f6 991
6ff71e76
NC		 992 case R_RL78_ABS16_REV:
993 RANGE (-32768, 65535);
994 OP (1) = relocation;
995 OP (0) = relocation >> 8;
996 break;
99c513f6 997
6ff71e76
NC		 998 case R_RL78_ABS16S_PCREL:
999 case R_RL78_ABS16S:
1000 RANGE (-32768, 32767);
1001 OP (0) = relocation;
1002 OP (1) = relocation >> 8;
1003 break;
99c513f6 1004
6ff71e76
NC		 1005 case R_RL78_ABS16U:
1006 case R_RL78_ABS16UL:
1007 case R_RL78_ABS16UW:
1008 RANGE (0, 65536);
1009 OP (0) = relocation;
1010 OP (1) = relocation >> 8;
1011 break;
99c513f6 1012
6ff71e76
NC		 1013 case R_RL78_ABS8:
1014 RANGE (-128, 255);
1015 OP (0) = relocation;
1016 break;
99c513f6 1017
6ff71e76
NC		 1018 case R_RL78_ABS8U:
1019 case R_RL78_ABS8UL:
1020 case R_RL78_ABS8UW:
1021 RANGE (0, 255);
1022 OP (0) = relocation;
1023 break;
1024
1025 case R_RL78_ABS8S_PCREL:
1026 case R_RL78_ABS8S:
1027 RANGE (-128, 127);
1028 OP (0) = relocation;
1029 break;
1030
1031 default:
1032 break;
1033 }
1034 break;
1b786873 1035
6ff71e76
NC		 1036 case R_RL78_SYM:
1037 if (r_symndx < symtab_hdr->sh_info)
1038 relocation = sec->output_section->vma + sec->output_offset
1039 + sym->st_value + rel->r_addend;
1040 else if (h != NULL
1041 && (h->root.type == bfd_link_hash_defined
1042 || h->root.type == bfd_link_hash_defweak))
1043 relocation = h->root.u.def.value
1044 + sec->output_section->vma
1045 + sec->output_offset
1046 + rel->r_addend;
1047 else
1048 {
1049 relocation = 0;
1050 if (h->root.type != bfd_link_hash_undefweak)
38f14ab8
AM		 1051 _bfd_error_handler
1052 (_("warning: RL78_SYM reloc with an unknown symbol"));
6ff71e76
NC		 1053 }
1054 (void) rl78_compute_complex_reloc (r_type, relocation, input_section);
99c513f6
DD		 1055 break;
1056
1057 case R_RL78_OPromtop:
1a72702b 1058 relocation = get_romstart (info, input_bfd, input_section, rel->r_offset);
6ff71e76 1059 (void) rl78_compute_complex_reloc (r_type, relocation, input_section);
99c513f6
DD		 1060 break;
1061
1062 case R_RL78_OPramtop:
1a72702b 1063 relocation = get_ramstart (info, input_bfd, input_section, rel->r_offset);
6ff71e76 1064 (void) rl78_compute_complex_reloc (r_type, relocation, input_section);
99c513f6
DD		 1065 break;
1066
1067 default:
1068 r = bfd_reloc_notsupported;
1069 break;
1070 }
1071
1072 if (r != bfd_reloc_ok)
1073 {
1074 const char * msg = NULL;
1075
1076 switch (r)
1077 {
1078 case bfd_reloc_overflow:
1079 /* Catch the case of a missing function declaration
1080 and emit a more helpful error message. */
1081 if (r_type == R_RL78_DIR24S_PCREL)
695344c0 1082 /* xgettext:c-format */
871b3ab2 1083 msg = _("%pB(%pA): error: call to undefined function '%s'");
99c513f6 1084 else
1a72702b 1085 (*info->callbacks->reloc_overflow)
99c513f6
DD		 1086 (info, (h ? &h->root : NULL), name, howto->name, (bfd_vma) 0,
1087 input_bfd, input_section, rel->r_offset);
1088 break;
1089
1090 case bfd_reloc_undefined:
1a72702b
AM		 1091 (*info->callbacks->undefined_symbol)
1092 (info, name, input_bfd, input_section, rel->r_offset, TRUE);
99c513f6
DD		 1093 break;
1094
1095 case bfd_reloc_other:
695344c0 1096 /* xgettext:c-format */
871b3ab2 1097 msg = _("%pB(%pA): warning: unaligned access to symbol '%s' in the small data area");
99c513f6
DD		 1098 break;
1099
1100 case bfd_reloc_outofrange:
695344c0 1101 /* xgettext:c-format */
871b3ab2 1102 msg = _("%pB(%pA): internal error: out of range error");
99c513f6
DD		 1103 break;
1104
1105 case bfd_reloc_notsupported:
695344c0 1106 /* xgettext:c-format */
871b3ab2 1107 msg = _("%pB(%pA): internal error: unsupported relocation error");
99c513f6
DD		 1108 break;
1109
1110 case bfd_reloc_dangerous:
695344c0 1111 /* xgettext:c-format */
871b3ab2 1112 msg = _("%pB(%pA): internal error: dangerous relocation");
99c513f6
DD		 1113 break;
1114
1115 default:
695344c0 1116 /* xgettext:c-format */
871b3ab2 1117 msg = _("%pB(%pA): internal error: unknown error");
99c513f6
DD		 1118 break;
1119 }
1120
1121 if (msg)
1122 _bfd_error_handler (msg, input_bfd, input_section, name);
99c513f6
DD		 1123 }
1124 }
1125
1126 return TRUE;
1127}
1128\f
1129/* Function to set the ELF flag bits. */
1130
1131static bfd_boolean
1132rl78_elf_set_private_flags (bfd * abfd, flagword flags)
1133{
1134 elf_elfheader (abfd)->e_flags = flags;
1135 elf_flags_init (abfd) = TRUE;
1136 return TRUE;
1137}
1138
1139static bfd_boolean no_warn_mismatch = FALSE;
1140
1141void bfd_elf32_rl78_set_target_flags (bfd_boolean);
1142
1143void
1144bfd_elf32_rl78_set_target_flags (bfd_boolean user_no_warn_mismatch)
1145{
1146 no_warn_mismatch = user_no_warn_mismatch;
1147}
1148
1740ba0c
NC		 1149static const char *
1150rl78_cpu_name (flagword flags)
1151{
1152 switch (flags & E_FLAG_RL78_CPU_MASK)
1153 {
1154 default: return "";
1155 case E_FLAG_RL78_G10: return "G10";
1156 case E_FLAG_RL78_G13: return "G13";
1157 case E_FLAG_RL78_G14: return "G14";
1158 }
1159}
1160
99c513f6
DD		 1161/* Merge backend specific data from an object file to the output
1162 object file when linking. */
1163
1164static bfd_boolean
50e03d47 1165rl78_elf_merge_private_bfd_data (bfd *ibfd, struct bfd_link_info *info)
99c513f6 1166{
50e03d47 1167 bfd *obfd = info->output_bfd;
99c513f6 1168 flagword new_flags;
4046d87a 1169 flagword old_flags;
99c513f6
DD		 1170 bfd_boolean error = FALSE;
1171
1172 new_flags = elf_elfheader (ibfd)->e_flags;
4046d87a 1173 old_flags = elf_elfheader (obfd)->e_flags;
99c513f6
DD		 1174
1175 if (!elf_flags_init (obfd))
1176 {
1177 /* First call, no flags set. */
1178 elf_flags_init (obfd) = TRUE;
1179 elf_elfheader (obfd)->e_flags = new_flags;
1180 }
4046d87a
NC		 1181 else if (old_flags != new_flags)
1182 {
1183 flagword changed_flags = old_flags ^ new_flags;
1184
1740ba0c 1185 if (changed_flags & E_FLAG_RL78_CPU_MASK)
4046d87a 1186 {
1740ba0c
NC		 1187 flagword out_cpu = old_flags & E_FLAG_RL78_CPU_MASK;
1188 flagword in_cpu = new_flags & E_FLAG_RL78_CPU_MASK;
4046d87a 1189
1740ba0c
NC		 1190 if (in_cpu == E_FLAG_RL78_ANY_CPU || in_cpu == out_cpu)
1191 /* It does not matter what new_cpu may have. */;
1192 else if (out_cpu == E_FLAG_RL78_ANY_CPU)
1193 {
1194 if (in_cpu == E_FLAG_RL78_G10)
1195 {
1196 /* G10 files can only be linked with other G10 files.
1197 If the output is set to "any" this means that it is
1198 a G14 file that does not use hardware multiply/divide,
1199 but that is still incompatible with the G10 ABI. */
1200 error = TRUE;
1201
4eca0228 1202 _bfd_error_handler
695344c0 1203 /* xgettext:c-format */
871b3ab2
AM		 1204 (_("RL78 ABI conflict: G10 file %pB cannot be linked"
1205 " with %s file %pB"),
dae82561 1206 ibfd, rl78_cpu_name (out_cpu), obfd);
1740ba0c
NC		 1207 }
1208 else
1209 {
1210 old_flags &= ~ E_FLAG_RL78_CPU_MASK;
1211 old_flags |= in_cpu;
1212 elf_elfheader (obfd)->e_flags = old_flags;
1213 }
1214 }
4046d87a 1215 else
1740ba0c
NC		 1216 {
1217 error = TRUE;
1218
4eca0228 1219 _bfd_error_handler
695344c0 1220 /* xgettext:c-format */
871b3ab2 1221 (_("RL78 ABI conflict: cannot link %s file %pB with %s file %pB"),
dae82561
AM		 1222 rl78_cpu_name (in_cpu), ibfd,
1223 rl78_cpu_name (out_cpu), obfd);
1740ba0c 1224 }
4046d87a 1225 }
856ea05c
KP		 1226
1227 if (changed_flags & E_FLAG_RL78_64BIT_DOUBLES)
1228 {
4eca0228 1229 _bfd_error_handler
856ea05c
KP		 1230 (_("RL78 merge conflict: cannot link 32-bit and 64-bit objects together"));
1231
1232 if (old_flags & E_FLAG_RL78_64BIT_DOUBLES)
695344c0 1233 /* xgettext:c-format */
871b3ab2 1234 _bfd_error_handler (_("- %pB is 64-bit, %pB is not"),
dae82561 1235 obfd, ibfd);
856ea05c 1236 else
695344c0 1237 /* xgettext:c-format */
871b3ab2 1238 _bfd_error_handler (_("- %pB is 64-bit, %pB is not"),
dae82561 1239 ibfd, obfd);
1740ba0c 1240 error = TRUE;
1b786873 1241 }
4046d87a 1242 }
99c513f6
DD		 1243
1244 return !error;
1245}
1246\f
1247static bfd_boolean
1248rl78_elf_print_private_bfd_data (bfd * abfd, void * ptr)
1249{
1250 FILE * file = (FILE *) ptr;
1251 flagword flags;
1252
1253 BFD_ASSERT (abfd != NULL && ptr != NULL);
1254
1255 /* Print normal ELF private data. */
1256 _bfd_elf_print_private_bfd_data (abfd, ptr);
1257
1258 flags = elf_elfheader (abfd)->e_flags;
1259 fprintf (file, _("private flags = 0x%lx:"), (long) flags);
1260
1740ba0c
NC		 1261 if (flags & E_FLAG_RL78_CPU_MASK)
1262 fprintf (file, " [%s]", rl78_cpu_name (flags));
4046d87a 1263
856ea05c
KP		 1264 if (flags & E_FLAG_RL78_64BIT_DOUBLES)
1265 fprintf (file, _(" [64-bit doubles]"));
1266
99c513f6
DD		 1267 fputc ('\n', file);
1268 return TRUE;
1269}
1270
1271/* Return the MACH for an e_flags value. */
1272
1273static int
1740ba0c 1274elf32_rl78_machine (bfd * abfd ATTRIBUTE_UNUSED)
99c513f6 1275{
1740ba0c 1276 return bfd_mach_rl78;
99c513f6
DD		 1277}
1278
1279static bfd_boolean
1280rl78_elf_object_p (bfd * abfd)
1281{
1282 bfd_default_set_arch_mach (abfd, bfd_arch_rl78,
1283 elf32_rl78_machine (abfd));
1284 return TRUE;
1285}
99c513f6
DD		 1286\f
1287/* support PLT for 16-bit references to 24-bit functions. */
1288
1289/* We support 16-bit pointers to code above 64k by generating a thunk
1290 below 64k containing a JMP instruction to the final address. */
68ffbac6 1291
99c513f6
DD		 1292static bfd_boolean
1293rl78_elf_check_relocs
07d6d2b8 1294 (bfd * abfd,
99c513f6 1295 struct bfd_link_info * info,
07d6d2b8 1296 asection * sec,
99c513f6
DD		 1297 const Elf_Internal_Rela * relocs)
1298{
07d6d2b8 1299 Elf_Internal_Shdr * symtab_hdr;
99c513f6 1300 struct elf_link_hash_entry ** sym_hashes;
07d6d2b8
AM		 1301 const Elf_Internal_Rela * rel;
1302 const Elf_Internal_Rela * rel_end;
99c513f6
DD		 1303 bfd_vma *local_plt_offsets;
1304 asection *splt;
1305 bfd *dynobj;
1306
0e1862bb 1307 if (bfd_link_relocatable (info))
99c513f6 1308 return TRUE;
68ffbac6 1309
99c513f6
DD		 1310 symtab_hdr = &elf_tdata (abfd)->symtab_hdr;
1311 sym_hashes = elf_sym_hashes (abfd);
1312 local_plt_offsets = elf_local_got_offsets (abfd);
99c513f6
DD		 1313 dynobj = elf_hash_table(info)->dynobj;
1314
1315 rel_end = relocs + sec->reloc_count;
1316 for (rel = relocs; rel < rel_end; rel++)
1317 {
1318 struct elf_link_hash_entry *h;
1319 unsigned long r_symndx;
1320 bfd_vma *offset;
68ffbac6 1321
99c513f6
DD		 1322 r_symndx = ELF32_R_SYM (rel->r_info);
1323 if (r_symndx < symtab_hdr->sh_info)
07d6d2b8 1324 h = NULL;
99c513f6
DD		 1325 else
1326 {
1327 h = sym_hashes[r_symndx - symtab_hdr->sh_info];
1328 while (h->root.type == bfd_link_hash_indirect
1329 || h->root.type == bfd_link_hash_warning)
1330 h = (struct elf_link_hash_entry *) h->root.u.i.link;
1331 }
68ffbac6 1332
99c513f6 1333 switch (ELF32_R_TYPE (rel->r_info))
07d6d2b8 1334 {
99c513f6
DD		 1335 /* This relocation describes a 16-bit pointer to a function.
1336 We may need to allocate a thunk in low memory; reserve memory
1337 for it now. */
1338 case R_RL78_DIR16S:
1339 if (dynobj == NULL)
1340 elf_hash_table (info)->dynobj = dynobj = abfd;
ce558b89 1341 splt = elf_hash_table (info)->splt;
99c513f6
DD		 1342 if (splt == NULL)
1343 {
ce558b89
AM		 1344 flagword flags = (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS
1345 | SEC_IN_MEMORY | SEC_LINKER_CREATED
1346 | SEC_READONLY | SEC_CODE);
1347 splt = bfd_make_section_anyway_with_flags (dynobj, ".plt",
1348 flags);
1349 elf_hash_table (info)->splt = splt;
1350 if (splt == NULL
1351 || ! bfd_set_section_alignment (dynobj, splt, 1))
1352 return FALSE;
99c513f6
DD		 1353 }
1354
1355 if (h != NULL)
1356 offset = &h->plt.offset;
1357 else
1358 {
1359 if (local_plt_offsets == NULL)
1360 {
1361 size_t size;
1362 unsigned int i;
1363
1364 size = symtab_hdr->sh_info * sizeof (bfd_vma);
1365 local_plt_offsets = (bfd_vma *) bfd_alloc (abfd, size);
1366 if (local_plt_offsets == NULL)
1367 return FALSE;
1368 elf_local_got_offsets (abfd) = local_plt_offsets;
1369
1370 for (i = 0; i < symtab_hdr->sh_info; i++)
1371 local_plt_offsets[i] = (bfd_vma) -1;
1372 }
1373 offset = &local_plt_offsets[r_symndx];
1374 }
1375
1376 if (*offset == (bfd_vma) -1)
1377 {
1378 *offset = splt->size;
1379 splt->size += 4;
1380 }
1381 break;
07d6d2b8 1382 }
99c513f6 1383 }
68ffbac6 1384
99c513f6
DD		 1385 return TRUE;
1386}
1387
1388/* This must exist if dynobj is ever set. */
1389
1390static bfd_boolean
1391rl78_elf_finish_dynamic_sections (bfd *abfd ATTRIBUTE_UNUSED,
07d6d2b8 1392 struct bfd_link_info *info)
99c513f6
DD		 1393{
1394 bfd *dynobj;
1395 asection *splt;
1396
47fc0f1f
NC		 1397 if (!elf_hash_table (info)->dynamic_sections_created)
1398 return TRUE;
1399
9cea966c
DD		 1400 /* As an extra sanity check, verify that all plt entries have been
1401 filled in. However, relaxing might have changed the relocs so
1402 that some plt entries don't get filled in, so we have to skip
1403 this check if we're relaxing. Unfortunately, check_relocs is
1404 called before relaxation. */
99c513f6 1405
1740ba0c 1406 if (info->relax_trip > 0)
47fc0f1f
NC		 1407 return TRUE;
1408
ce558b89
AM		 1409 dynobj = elf_hash_table (info)->dynobj;
1410 splt = elf_hash_table (info)->splt;
1411 if (dynobj != NULL && splt != NULL)
99c513f6 1412 {
47fc0f1f
NC		 1413 bfd_byte *contents = splt->contents;
1414 unsigned int i, size = splt->size;
1415
1416 for (i = 0; i < size; i += 4)
99c513f6 1417 {
47fc0f1f
NC		 1418 unsigned int x = bfd_get_32 (dynobj, contents + i);
1419 BFD_ASSERT (x != 0);
99c513f6
DD		 1420 }
1421 }
1422
1423 return TRUE;
1424}
1425
1426static bfd_boolean
1427rl78_elf_always_size_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
07d6d2b8 1428 struct bfd_link_info *info)
99c513f6
DD		 1429{
1430 bfd *dynobj;
1431 asection *splt;
1432
0e1862bb 1433 if (bfd_link_relocatable (info))
99c513f6
DD		 1434 return TRUE;
1435
1436 dynobj = elf_hash_table (info)->dynobj;
1437 if (dynobj == NULL)
1438 return TRUE;
1439
ce558b89 1440 splt = elf_hash_table (info)->splt;
99c513f6
DD		 1441 BFD_ASSERT (splt != NULL);
1442
1443 splt->contents = (bfd_byte *) bfd_zalloc (dynobj, splt->size);
1444 if (splt->contents == NULL)
1445 return FALSE;
1446
1447 return TRUE;
1448}
1449
1450\f
1451
1452/* Handle relaxing. */
1453
1454/* A subroutine of rl78_elf_relax_section. If the global symbol H
1455 is within the low 64k, remove any entry for it in the plt. */
1456
1457struct relax_plt_data
1458{
1459 asection *splt;
1460 bfd_boolean *again;
1461};
1462
1463static bfd_boolean
2c3fc389 1464rl78_relax_plt_check (struct elf_link_hash_entry *h, void * xdata)
99c513f6
DD		 1465{
1466 struct relax_plt_data *data = (struct relax_plt_data *) xdata;
1467
1468 if (h->plt.offset != (bfd_vma) -1)
1469 {
1470 bfd_vma address;
1471
1472 if (h->root.type == bfd_link_hash_undefined
1473 || h->root.type == bfd_link_hash_undefweak)
1474 address = 0;
1475 else
1476 address = (h->root.u.def.section->output_section->vma
1477 + h->root.u.def.section->output_offset
1478 + h->root.u.def.value);
1479
1480 if (valid_16bit_address (address))
1481 {
1482 h->plt.offset = -1;
1483 data->splt->size -= 4;
1484 *data->again = TRUE;
1485 }
1486 }
1487
1488 return TRUE;
1489}
1490
1491/* A subroutine of rl78_elf_relax_section. If the global symbol H
1492 previously had a plt entry, give it a new entry offset. */
1493
1494static bfd_boolean
2c3fc389 1495rl78_relax_plt_realloc (struct elf_link_hash_entry *h, void * xdata)
99c513f6
DD		 1496{
1497 bfd_vma *entry = (bfd_vma *) xdata;
1498
1499 if (h->plt.offset != (bfd_vma) -1)
1500 {
1501 h->plt.offset = *entry;
1502 *entry += 4;
1503 }
1504
1505 return TRUE;
1506}
1507
1508static bfd_boolean
1509rl78_elf_relax_plt_section (bfd *dynobj,
07d6d2b8
AM		 1510 asection *splt,
1511 struct bfd_link_info *info,
1512 bfd_boolean *again)
99c513f6
DD		 1513{
1514 struct relax_plt_data relax_plt_data;
1515 bfd *ibfd;
1516
1517 /* Assume nothing changes. */
1518 *again = FALSE;
1519
0e1862bb 1520 if (bfd_link_relocatable (info))
99c513f6
DD		 1521 return TRUE;
1522
1523 /* We only relax the .plt section at the moment. */
1524 if (dynobj != elf_hash_table (info)->dynobj
1525 || strcmp (splt->name, ".plt") != 0)
1526 return TRUE;
1527
1528 /* Quick check for an empty plt. */
1529 if (splt->size == 0)
1530 return TRUE;
1531
1532 /* Map across all global symbols; see which ones happen to
1533 fall in the low 64k. */
1534 relax_plt_data.splt = splt;
1535 relax_plt_data.again = again;
1536 elf_link_hash_traverse (elf_hash_table (info), rl78_relax_plt_check,
1537 &relax_plt_data);
1538
1539 /* Likewise for local symbols, though that's somewhat less convenient
1540 as we have to walk the list of input bfds and swap in symbol data. */
c72f2fb2 1541 for (ibfd = info->input_bfds; ibfd ; ibfd = ibfd->link.next)
99c513f6
DD		 1542 {
1543 bfd_vma *local_plt_offsets = elf_local_got_offsets (ibfd);
1544 Elf_Internal_Shdr *symtab_hdr;
1545 Elf_Internal_Sym *isymbuf = NULL;
1546 unsigned int idx;
1547
1548 if (! local_plt_offsets)
1549 continue;
1550
1551 symtab_hdr = &elf_tdata (ibfd)->symtab_hdr;
1552 if (symtab_hdr->sh_info != 0)
1553 {
1554 isymbuf = (Elf_Internal_Sym *) symtab_hdr->contents;
1555 if (isymbuf == NULL)
1556 isymbuf = bfd_elf_get_elf_syms (ibfd, symtab_hdr,
1557 symtab_hdr->sh_info, 0,
1558 NULL, NULL, NULL);
1559 if (isymbuf == NULL)
1560 return FALSE;
1561 }
1562
1563 for (idx = 0; idx < symtab_hdr->sh_info; ++idx)
1564 {
1565 Elf_Internal_Sym *isym;
1566 asection *tsec;
1567 bfd_vma address;
1568
1569 if (local_plt_offsets[idx] == (bfd_vma) -1)
1570 continue;
1571
1572 isym = &isymbuf[idx];
1573 if (isym->st_shndx == SHN_UNDEF)
1574 continue;
1575 else if (isym->st_shndx == SHN_ABS)
1576 tsec = bfd_abs_section_ptr;
1577 else if (isym->st_shndx == SHN_COMMON)
1578 tsec = bfd_com_section_ptr;
1579 else
1580 tsec = bfd_section_from_elf_index (ibfd, isym->st_shndx);
1581
1582 address = (tsec->output_section->vma
1583 + tsec->output_offset
1584 + isym->st_value);
1585 if (valid_16bit_address (address))
1586 {
1587 local_plt_offsets[idx] = -1;
1588 splt->size -= 4;
1589 *again = TRUE;
1590 }
1591 }
1592
1593 if (isymbuf != NULL
1594 && symtab_hdr->contents != (unsigned char *) isymbuf)
1595 {
1596 if (! info->keep_memory)
1597 free (isymbuf);
1598 else
1599 {
1600 /* Cache the symbols for elf_link_input_bfd. */
1601 symtab_hdr->contents = (unsigned char *) isymbuf;
1602 }
1603 }
1604 }
1605
1606 /* If we changed anything, walk the symbols again to reallocate
1607 .plt entry addresses. */
1608 if (*again && splt->size > 0)
1609 {
1610 bfd_vma entry = 0;
1611
1612 elf_link_hash_traverse (elf_hash_table (info),
1613 rl78_relax_plt_realloc, &entry);
1614
c72f2fb2 1615 for (ibfd = info->input_bfds; ibfd ; ibfd = ibfd->link.next)
99c513f6
DD		 1616 {
1617 bfd_vma *local_plt_offsets = elf_local_got_offsets (ibfd);
1618 unsigned int nlocals = elf_tdata (ibfd)->symtab_hdr.sh_info;
1619 unsigned int idx;
1620
1621 if (! local_plt_offsets)
1622 continue;
1623
1624 for (idx = 0; idx < nlocals; ++idx)
1625 if (local_plt_offsets[idx] != (bfd_vma) -1)
1626 {
07d6d2b8 1627 local_plt_offsets[idx] = entry;
99c513f6
DD		 1628 entry += 4;
1629 }
1630 }
1631 }
1632
1633 return TRUE;
1634}
1635
9cea966c
DD		 1636/* Delete some bytes from a section while relaxing. */
1637
1638static bfd_boolean
1639elf32_rl78_relax_delete_bytes (bfd *abfd, asection *sec, bfd_vma addr, int count,
1740ba0c 1640 Elf_Internal_Rela *alignment_rel, int force_snip)
9cea966c
DD		 1641{
1642 Elf_Internal_Shdr * symtab_hdr;
07d6d2b8
AM		 1643 unsigned int sec_shndx;
1644 bfd_byte * contents;
9cea966c
DD		 1645 Elf_Internal_Rela * irel;
1646 Elf_Internal_Rela * irelend;
1647 Elf_Internal_Sym * isym;
1648 Elf_Internal_Sym * isymend;
07d6d2b8
AM		 1649 bfd_vma toaddr;
1650 unsigned int symcount;
9cea966c
DD		 1651 struct elf_link_hash_entry ** sym_hashes;
1652 struct elf_link_hash_entry ** end_hashes;
1653
1654 if (!alignment_rel)
1655 force_snip = 1;
1656
1657 sec_shndx = _bfd_elf_section_from_bfd_section (abfd, sec);
1658
1659 contents = elf_section_data (sec)->this_hdr.contents;
1660
1661 /* The deletion must stop at the next alignment boundary, if
1662 ALIGNMENT_REL is non-NULL. */
1663 toaddr = sec->size;
1664 if (alignment_rel)
1665 toaddr = alignment_rel->r_offset;
1666
1667 irel = elf_section_data (sec)->relocs;
2bc56d66
DD		 1668 if (irel == NULL)
1669 {
1670 _bfd_elf_link_read_relocs (sec->owner, sec, NULL, NULL, TRUE);
1671 irel = elf_section_data (sec)->relocs;
1672 }
1673
9cea966c
DD		 1674 irelend = irel + sec->reloc_count;
1675
1676 /* Actually delete the bytes. */
1677 memmove (contents + addr, contents + addr + count,
1678 (size_t) (toaddr - addr - count));
1679
1680 /* If we don't have an alignment marker to worry about, we can just
1681 shrink the section. Otherwise, we have to fill in the newly
1682 created gap with NOP insns (0x03). */
1683 if (force_snip)
1684 sec->size -= count;
1685 else
1686 memset (contents + toaddr - count, 0x03, count);
1687
1688 /* Adjust all the relocs. */
2bc56d66 1689 for (; irel && irel < irelend; irel++)
9cea966c
DD		 1690 {
1691 /* Get the new reloc address. */
1692 if (irel->r_offset > addr
1693 && (irel->r_offset < toaddr
1694 || (force_snip && irel->r_offset == toaddr)))
1695 irel->r_offset -= count;
1696
1697 /* If we see an ALIGN marker at the end of the gap, we move it
1698 to the beginning of the gap, since marking these gaps is what
1699 they're for. */
1700 if (irel->r_offset == toaddr
1701 && ELF32_R_TYPE (irel->r_info) == R_RL78_RH_RELAX
1702 && irel->r_addend & RL78_RELAXA_ALIGN)
1703 irel->r_offset -= count;
1704 }
1705
1706 /* Adjust the local symbols defined in this section. */
1707 symtab_hdr = &elf_tdata (abfd)->symtab_hdr;
1708 isym = (Elf_Internal_Sym *) symtab_hdr->contents;
1709 isymend = isym + symtab_hdr->sh_info;
1710
1711 for (; isym < isymend; isym++)
1712 {
1713 /* If the symbol is in the range of memory we just moved, we
1714 have to adjust its value. */
1715 if (isym->st_shndx == sec_shndx
1716 && isym->st_value > addr
1717 && isym->st_value < toaddr)
1718 isym->st_value -= count;
1719
1720 /* If the symbol *spans* the bytes we just deleted (i.e. it's
1721 *end* is in the moved bytes but it's *start* isn't), then we
1722 must adjust its size. */
1723 if (isym->st_shndx == sec_shndx
1724 && isym->st_value < addr
1725 && isym->st_value + isym->st_size > addr
1726 && isym->st_value + isym->st_size < toaddr)
1727 isym->st_size -= count;
1728 }
1729
1730 /* Now adjust the global symbols defined in this section. */
1731 symcount = (symtab_hdr->sh_size / sizeof (Elf32_External_Sym)
1732 - symtab_hdr->sh_info);
1733 sym_hashes = elf_sym_hashes (abfd);
1734 end_hashes = sym_hashes + symcount;
1735
1736 for (; sym_hashes < end_hashes; sym_hashes++)
1737 {
1738 struct elf_link_hash_entry *sym_hash = *sym_hashes;
1739
1740 if ((sym_hash->root.type == bfd_link_hash_defined
1741 || sym_hash->root.type == bfd_link_hash_defweak)
1742 && sym_hash->root.u.def.section == sec)
1743 {
1744 /* As above, adjust the value if needed. */
1745 if (sym_hash->root.u.def.value > addr
1746 && sym_hash->root.u.def.value < toaddr)
1747 sym_hash->root.u.def.value -= count;
1748
1749 /* As above, adjust the size if needed. */
1750 if (sym_hash->root.u.def.value < addr
1751 && sym_hash->root.u.def.value + sym_hash->size > addr
1752 && sym_hash->root.u.def.value + sym_hash->size < toaddr)
1753 sym_hash->size -= count;
1754 }
1755 }
1756
1757 return TRUE;
1758}
1759
1760/* Used to sort relocs by address. If relocs have the same address,
1761 we maintain their relative order, except that R_RL78_RH_RELAX
1762 alignment relocs must be the first reloc for any given address. */
1763
1764static void
1765reloc_bubblesort (Elf_Internal_Rela * r, int count)
1766{
1767 int i;
1768 bfd_boolean again;
1769 bfd_boolean swappit;
1770
1771 /* This is almost a classic bubblesort. It's the slowest sort, but
1772 we're taking advantage of the fact that the relocations are
1773 mostly in order already (the assembler emits them that way) and
1774 we need relocs with the same address to remain in the same
1775 relative order. */
1776 again = TRUE;
1777 while (again)
1778 {
1779 again = FALSE;
1780 for (i = 0; i < count - 1; i ++)
1781 {
1782 if (r[i].r_offset > r[i + 1].r_offset)
1783 swappit = TRUE;
1784 else if (r[i].r_offset < r[i + 1].r_offset)
1785 swappit = FALSE;
1786 else if (ELF32_R_TYPE (r[i + 1].r_info) == R_RL78_RH_RELAX
1787 && (r[i + 1].r_addend & RL78_RELAXA_ALIGN))
1788 swappit = TRUE;
1789 else if (ELF32_R_TYPE (r[i + 1].r_info) == R_RL78_RH_RELAX
1790 && (r[i + 1].r_addend & RL78_RELAXA_ELIGN)
1791 && !(ELF32_R_TYPE (r[i].r_info) == R_RL78_RH_RELAX
1792 && (r[i].r_addend & RL78_RELAXA_ALIGN)))
1793 swappit = TRUE;
1794 else
1795 swappit = FALSE;
1796
1797 if (swappit)
1798 {
1799 Elf_Internal_Rela tmp;
1800
1801 tmp = r[i];
1802 r[i] = r[i + 1];
1803 r[i + 1] = tmp;
1804 /* If we do move a reloc back, re-scan to see if it
1805 needs to be moved even further back. This avoids
1806 most of the O(n^2) behavior for our cases. */
1807 if (i > 0)
1808 i -= 2;
1809 again = TRUE;
1810 }
1811 }
1812 }
1813}
1814
1815
1816#define OFFSET_FOR_RELOC(rel, lrel, scale) \
1817 rl78_offset_for_reloc (abfd, rel + 1, symtab_hdr, shndx_buf, intsyms, \
6ff71e76 1818 lrel, abfd, sec, link_info, scale)
9cea966c
DD		 1819
1820static bfd_vma
07d6d2b8
AM		 1821rl78_offset_for_reloc (bfd * abfd,
1822 Elf_Internal_Rela * rel,
1823 Elf_Internal_Shdr * symtab_hdr,
6ff71e76 1824 Elf_External_Sym_Shndx * shndx_buf ATTRIBUTE_UNUSED,
07d6d2b8
AM		 1825 Elf_Internal_Sym * intsyms,
1826 Elf_Internal_Rela ** lrel,
1827 bfd * input_bfd,
1828 asection * input_section,
1829 struct bfd_link_info * info,
1830 int * scale)
9cea966c
DD		 1831{
1832 bfd_vma symval;
9cea966c
DD		 1833
1834 *scale = 1;
1835
1836 /* REL is the first of 1..N relocations. We compute the symbol
1837 value for each relocation, then combine them if needed. LREL
1838 gets a pointer to the last relocation used. */
1839 while (1)
1840 {
6ff71e76 1841 unsigned long r_type;
9cea966c
DD		 1842
1843 /* Get the value of the symbol referred to by the reloc. */
1844 if (ELF32_R_SYM (rel->r_info) < symtab_hdr->sh_info)
1845 {
1846 /* A local symbol. */
1847 Elf_Internal_Sym *isym;
1848 asection *ssec;
1849
1850 isym = intsyms + ELF32_R_SYM (rel->r_info);
1851
1852 if (isym->st_shndx == SHN_UNDEF)
1853 ssec = bfd_und_section_ptr;
1854 else if (isym->st_shndx == SHN_ABS)
1855 ssec = bfd_abs_section_ptr;
1856 else if (isym->st_shndx == SHN_COMMON)
1857 ssec = bfd_com_section_ptr;
1858 else
1859 ssec = bfd_section_from_elf_index (abfd,
1860 isym->st_shndx);
1861
1862 /* Initial symbol value. */
1863 symval = isym->st_value;
1864
1865 /* GAS may have made this symbol relative to a section, in
1866 which case, we have to add the addend to find the
1867 symbol. */
1868 if (ELF_ST_TYPE (isym->st_info) == STT_SECTION)
1869 symval += rel->r_addend;
1870
1871 if (ssec)
1872 {
1873 if ((ssec->flags & SEC_MERGE)
dbaa2011 1874 && ssec->sec_info_type == SEC_INFO_TYPE_MERGE)
9cea966c
DD		 1875 symval = _bfd_merged_section_offset (abfd, & ssec,
1876 elf_section_data (ssec)->sec_info,
1877 symval);
1878 }
1879
1880 /* Now make the offset relative to where the linker is putting it. */
1881 if (ssec)
1882 symval +=
1883 ssec->output_section->vma + ssec->output_offset;
1884
1885 symval += rel->r_addend;
1886 }
1887 else
1888 {
1889 unsigned long indx;
1890 struct elf_link_hash_entry * h;
1891
1892 /* An external symbol. */
1893 indx = ELF32_R_SYM (rel->r_info) - symtab_hdr->sh_info;
1894 h = elf_sym_hashes (abfd)[indx];
1895 BFD_ASSERT (h != NULL);
1896
1897 if (h->root.type != bfd_link_hash_defined
1898 && h->root.type != bfd_link_hash_defweak)
1899 {
1900 /* This appears to be a reference to an undefined
1901 symbol. Just ignore it--it will be caught by the
1902 regular reloc processing. */
1903 if (lrel)
1904 *lrel = rel;
1905 return 0;
1906 }
1907
1908 symval = (h->root.u.def.value
1909 + h->root.u.def.section->output_section->vma
1910 + h->root.u.def.section->output_offset);
1911
1912 symval += rel->r_addend;
1913 }
1914
6ff71e76
NC		 1915 r_type = ELF32_R_TYPE (rel->r_info);
1916 switch (r_type)
9cea966c
DD		 1917 {
1918 case R_RL78_SYM:
6ff71e76 1919 (void) rl78_compute_complex_reloc (r_type, symval, input_section);
9cea966c
DD		 1920 break;
1921
6ff71e76 1922 case R_RL78_OPromtop:
1a72702b 1923 symval = get_romstart (info, input_bfd, input_section, rel->r_offset);
6ff71e76 1924 (void) rl78_compute_complex_reloc (r_type, symval, input_section);
9cea966c
DD		 1925 break;
1926
6ff71e76 1927 case R_RL78_OPramtop:
1a72702b 1928 symval = get_ramstart (info, input_bfd, input_section, rel->r_offset);
6ff71e76 1929 (void) rl78_compute_complex_reloc (r_type, symval, input_section);
9cea966c
DD		 1930 break;
1931
6ff71e76
NC		 1932 case R_RL78_OPneg:
1933 case R_RL78_OPadd:
9cea966c 1934 case R_RL78_OPsub:
9cea966c 1935 case R_RL78_OPmul:
9cea966c 1936 case R_RL78_OPdiv:
9cea966c 1937 case R_RL78_OPshla:
9cea966c 1938 case R_RL78_OPshra:
9cea966c 1939 case R_RL78_OPsctsize:
9cea966c 1940 case R_RL78_OPscttop:
9cea966c 1941 case R_RL78_OPand:
9cea966c 1942 case R_RL78_OPor:
9cea966c 1943 case R_RL78_OPxor:
9cea966c 1944 case R_RL78_OPnot:
9cea966c 1945 case R_RL78_OPmod:
6ff71e76 1946 (void) rl78_compute_complex_reloc (r_type, 0, input_section);
9cea966c
DD		 1947 break;
1948
1949 case R_RL78_DIR16UL:
1950 case R_RL78_DIR8UL:
1951 case R_RL78_ABS16UL:
1952 case R_RL78_ABS8UL:
9cea966c 1953 *scale = 4;
6ff71e76 1954 goto reloc_computes_value;
9cea966c
DD		 1955
1956 case R_RL78_DIR16UW:
1957 case R_RL78_DIR8UW:
1958 case R_RL78_ABS16UW:
1959 case R_RL78_ABS8UW:
9cea966c 1960 *scale = 2;
6ff71e76 1961 goto reloc_computes_value;
1b786873 1962
9cea966c 1963 default:
6ff71e76 1964 reloc_computes_value:
e896287c 1965 symval = rl78_compute_complex_reloc (r_type, symval, input_section);
1a0670f3 1966 /* Fall through. */
e896287c
DD		 1967 case R_RL78_DIR32:
1968 case R_RL78_DIR24S:
1969 case R_RL78_DIR16:
1970 case R_RL78_DIR16U:
1971 case R_RL78_DIR16S:
1972 case R_RL78_DIR24S_PCREL:
1973 case R_RL78_DIR16S_PCREL:
1974 case R_RL78_DIR8S_PCREL:
9cea966c
DD		 1975 if (lrel)
1976 *lrel = rel;
1977 return symval;
1978 }
1979
1980 rel ++;
1981 }
1982}
1983
1984struct {
1985 int prefix; /* or -1 for "no prefix" */
1986 int insn; /* or -1 for "end of list" */
1987 int insn_for_saddr; /* or -1 for "no alternative" */
1988 int insn_for_sfr; /* or -1 for "no alternative" */
1989} relax_addr16[] = {
1990 { -1, 0x02, 0x06, -1 }, /* ADDW AX, !addr16 */
1991 { -1, 0x22, 0x26, -1 }, /* SUBW AX, !addr16 */
1992 { -1, 0x42, 0x46, -1 }, /* CMPW AX, !addr16 */
1993 { -1, 0x40, 0x4a, -1 }, /* CMP !addr16, #byte */
1994
1995 { -1, 0x0f, 0x0b, -1 }, /* ADD A, !addr16 */
1996 { -1, 0x1f, 0x1b, -1 }, /* ADDC A, !addr16 */
1997 { -1, 0x2f, 0x2b, -1 }, /* SUB A, !addr16 */
1998 { -1, 0x3f, 0x3b, -1 }, /* SUBC A, !addr16 */
1999 { -1, 0x4f, 0x4b, -1 }, /* CMP A, !addr16 */
2000 { -1, 0x5f, 0x5b, -1 }, /* AND A, !addr16 */
2001 { -1, 0x6f, 0x6b, -1 }, /* OR A, !addr16 */
2002 { -1, 0x7f, 0x7b, -1 }, /* XOR A, !addr16 */
2003
2004 { -1, 0x8f, 0x8d, 0x8e }, /* MOV A, !addr16 */
2005 { -1, 0x9f, 0x9d, 0x9e }, /* MOV !addr16, A */
2006 { -1, 0xaf, 0xad, 0xae }, /* MOVW AX, !addr16 */
2007 { -1, 0xbf, 0xbd, 0xbe }, /* MOVW !addr16, AX */
2008 { -1, 0xcf, 0xcd, 0xce }, /* MOVW !addr16, #word */
2009
2010 { -1, 0xa0, 0xa4, -1 }, /* INC !addr16 */
2011 { -1, 0xa2, 0xa6, -1 }, /* INCW !addr16 */
2012 { -1, 0xb0, 0xb4, -1 }, /* DEC !addr16 */
2013 { -1, 0xb2, 0xb6, -1 }, /* DECW !addr16 */
2014
2015 { -1, 0xd5, 0xd4, -1 }, /* CMP0 !addr16 */
2016 { -1, 0xe5, 0xe4, -1 }, /* ONEB !addr16 */
2017 { -1, 0xf5, 0xf4, -1 }, /* CLRB !addr16 */
2018
2019 { -1, 0xd9, 0xd8, -1 }, /* MOV X, !addr16 */
2020 { -1, 0xe9, 0xe8, -1 }, /* MOV B, !addr16 */
2021 { -1, 0xf9, 0xf8, -1 }, /* MOV C, !addr16 */
2022 { -1, 0xdb, 0xda, -1 }, /* MOVW BC, !addr16 */
2023 { -1, 0xeb, 0xea, -1 }, /* MOVW DE, !addr16 */
2024 { -1, 0xfb, 0xfa, -1 }, /* MOVW HL, !addr16 */
2025
2026 { 0x61, 0xaa, 0xa8, -1 }, /* XCH A, !addr16 */
2027
2028 { 0x71, 0x00, 0x02, 0x0a }, /* SET1 !addr16.0 */
2029 { 0x71, 0x10, 0x12, 0x1a }, /* SET1 !addr16.0 */
2030 { 0x71, 0x20, 0x22, 0x2a }, /* SET1 !addr16.0 */
2031 { 0x71, 0x30, 0x32, 0x3a }, /* SET1 !addr16.0 */
2032 { 0x71, 0x40, 0x42, 0x4a }, /* SET1 !addr16.0 */
2033 { 0x71, 0x50, 0x52, 0x5a }, /* SET1 !addr16.0 */
2034 { 0x71, 0x60, 0x62, 0x6a }, /* SET1 !addr16.0 */
2035 { 0x71, 0x70, 0x72, 0x7a }, /* SET1 !addr16.0 */
2036
2037 { 0x71, 0x08, 0x03, 0x0b }, /* CLR1 !addr16.0 */
2038 { 0x71, 0x18, 0x13, 0x1b }, /* CLR1 !addr16.0 */
2039 { 0x71, 0x28, 0x23, 0x2b }, /* CLR1 !addr16.0 */
2040 { 0x71, 0x38, 0x33, 0x3b }, /* CLR1 !addr16.0 */
2041 { 0x71, 0x48, 0x43, 0x4b }, /* CLR1 !addr16.0 */
2042 { 0x71, 0x58, 0x53, 0x5b }, /* CLR1 !addr16.0 */
2043 { 0x71, 0x68, 0x63, 0x6b }, /* CLR1 !addr16.0 */
2044 { 0x71, 0x78, 0x73, 0x7b }, /* CLR1 !addr16.0 */
68ffbac6 2045
9cea966c
DD		 2046 { -1, -1, -1, -1 }
2047};
2048
2049/* Relax one section. */
2050
99c513f6
DD		 2051static bfd_boolean
2052rl78_elf_relax_section
07d6d2b8
AM		 2053 (bfd * abfd,
2054 asection * sec,
99c513f6 2055 struct bfd_link_info * link_info,
07d6d2b8 2056 bfd_boolean * again)
99c513f6 2057{
9cea966c
DD		 2058 Elf_Internal_Shdr * symtab_hdr;
2059 Elf_Internal_Shdr * shndx_hdr;
2060 Elf_Internal_Rela * internal_relocs;
2061 Elf_Internal_Rela * free_relocs = NULL;
2062 Elf_Internal_Rela * irel;
2063 Elf_Internal_Rela * srel;
2064 Elf_Internal_Rela * irelend;
2065 Elf_Internal_Rela * next_alignment;
07d6d2b8
AM		 2066 bfd_byte * contents = NULL;
2067 bfd_byte * free_contents = NULL;
9cea966c
DD		 2068 Elf_Internal_Sym * intsyms = NULL;
2069 Elf_Internal_Sym * free_intsyms = NULL;
2070 Elf_External_Sym_Shndx * shndx_buf = NULL;
2071 bfd_vma pc;
9cea966c
DD		 2072 bfd_vma symval ATTRIBUTE_UNUSED = 0;
2073 int pcrel ATTRIBUTE_UNUSED = 0;
2074 int code ATTRIBUTE_UNUSED = 0;
2075 int section_alignment_glue;
2076 int scale;
2077
99c513f6
DD		 2078 if (abfd == elf_hash_table (link_info)->dynobj
2079 && strcmp (sec->name, ".plt") == 0)
2080 return rl78_elf_relax_plt_section (abfd, sec, link_info, again);
2081
2082 /* Assume nothing changes. */
2083 *again = FALSE;
9cea966c
DD		 2084
2085 /* We don't have to do anything for a relocatable link, if
2086 this section does not have relocs, or if this is not a
2087 code section. */
0e1862bb 2088 if (bfd_link_relocatable (link_info)
9cea966c
DD		 2089 || (sec->flags & SEC_RELOC) == 0
2090 || sec->reloc_count == 0
2091 || (sec->flags & SEC_CODE) == 0)
2092 return TRUE;
2093
6a40cf0c
NC		 2094 symtab_hdr = & elf_symtab_hdr (abfd);
2095 if (elf_symtab_shndx_list (abfd))
2096 shndx_hdr = & elf_symtab_shndx_list (abfd)->hdr;
2097 else
2098 shndx_hdr = NULL;
9cea966c 2099
9cea966c
DD		 2100 /* Get the section contents. */
2101 if (elf_section_data (sec)->this_hdr.contents != NULL)
2102 contents = elf_section_data (sec)->this_hdr.contents;
2103 /* Go get them off disk. */
2104 else
2105 {
2106 if (! bfd_malloc_and_get_section (abfd, sec, &contents))
2107 goto error_return;
2108 elf_section_data (sec)->this_hdr.contents = contents;
2109 }
2110
2111 /* Read this BFD's symbols. */
2112 /* Get cached copy if it exists. */
2113 if (symtab_hdr->contents != NULL)
2114 intsyms = (Elf_Internal_Sym *) symtab_hdr->contents;
2115 else
2116 {
2117 intsyms = bfd_elf_get_elf_syms (abfd, symtab_hdr, symtab_hdr->sh_info, 0, NULL, NULL, NULL);
2118 symtab_hdr->contents = (bfd_byte *) intsyms;
2119 }
2120
6a40cf0c 2121 if (shndx_hdr && shndx_hdr->sh_size != 0)
9cea966c
DD		 2122 {
2123 bfd_size_type amt;
2124
2125 amt = symtab_hdr->sh_info;
2126 amt *= sizeof (Elf_External_Sym_Shndx);
2127 shndx_buf = (Elf_External_Sym_Shndx *) bfd_malloc (amt);
2128 if (shndx_buf == NULL)
2129 goto error_return;
2130 if (bfd_seek (abfd, shndx_hdr->sh_offset, SEEK_SET) != 0
2c3fc389 2131 || bfd_bread (shndx_buf, amt, abfd) != amt)
9cea966c
DD		 2132 goto error_return;
2133 shndx_hdr->contents = (bfd_byte *) shndx_buf;
2134 }
2135
2136 /* Get a copy of the native relocations. */
2137 internal_relocs = (_bfd_elf_link_read_relocs
2c3fc389 2138 (abfd, sec, NULL, (Elf_Internal_Rela *) NULL,
9cea966c
DD		 2139 link_info->keep_memory));
2140 if (internal_relocs == NULL)
2141 goto error_return;
2142 if (! link_info->keep_memory)
2143 free_relocs = internal_relocs;
2144
2145 /* The RL_ relocs must be just before the operand relocs they go
2146 with, so we must sort them to guarantee this. We use bubblesort
2147 instead of qsort so we can guarantee that relocs with the same
2148 address remain in the same relative order. */
2149 reloc_bubblesort (internal_relocs, sec->reloc_count);
2150
2151 /* Walk through them looking for relaxing opportunities. */
2152 irelend = internal_relocs + sec->reloc_count;
2153
2154
2155 /* This will either be NULL or a pointer to the next alignment
2156 relocation. */
2157 next_alignment = internal_relocs;
9cea966c
DD		 2158
2159 /* We calculate worst case shrinkage caused by alignment directives.
2160 No fool-proof, but better than either ignoring the problem or
2161 doing heavy duty analysis of all the alignment markers in all
2162 input sections. */
2163 section_alignment_glue = 0;
2164 for (irel = internal_relocs; irel < irelend; irel++)
2165 if (ELF32_R_TYPE (irel->r_info) == R_RL78_RH_RELAX
2166 && irel->r_addend & RL78_RELAXA_ALIGN)
2167 {
2168 int this_glue = 1 << (irel->r_addend & RL78_RELAXA_ANUM);
2169
2170 if (section_alignment_glue < this_glue)
2171 section_alignment_glue = this_glue;
2172 }
2173 /* Worst case is all 0..N alignments, in order, causing 2*N-1 byte
2174 shrinkage. */
2175 section_alignment_glue *= 2;
2176
2177 for (irel = internal_relocs; irel < irelend; irel++)
2178 {
2179 unsigned char *insn;
2180 int nrelocs;
2181
2182 /* The insns we care about are all marked with one of these. */
2183 if (ELF32_R_TYPE (irel->r_info) != R_RL78_RH_RELAX)
2184 continue;
2185
2186 if (irel->r_addend & RL78_RELAXA_ALIGN
2187 || next_alignment == internal_relocs)
2188 {
2189 /* When we delete bytes, we need to maintain all the alignments
2190 indicated. In addition, we need to be careful about relaxing
2191 jumps across alignment boundaries - these displacements
2192 *grow* when we delete bytes. For now, don't shrink
2193 displacements across an alignment boundary, just in case.
2194 Note that this only affects relocations to the same
2195 section. */
9cea966c
DD		 2196 next_alignment += 2;
2197 while (next_alignment < irelend
2198 && (ELF32_R_TYPE (next_alignment->r_info) != R_RL78_RH_RELAX
2199 || !(next_alignment->r_addend & RL78_RELAXA_ELIGN)))
2200 next_alignment ++;
2201 if (next_alignment >= irelend || next_alignment->r_offset == 0)
2202 next_alignment = NULL;
2203 }
2204
2205 /* When we hit alignment markers, see if we've shrunk enough
2206 before them to reduce the gap without violating the alignment
2207 requirements. */
2208 if (irel->r_addend & RL78_RELAXA_ALIGN)
2209 {
2210 /* At this point, the next relocation *should* be the ELIGN
2211 end marker. */
2212 Elf_Internal_Rela *erel = irel + 1;
2213 unsigned int alignment, nbytes;
2214
2215 if (ELF32_R_TYPE (erel->r_info) != R_RL78_RH_RELAX)
2216 continue;
2217 if (!(erel->r_addend & RL78_RELAXA_ELIGN))
2218 continue;
2219
2220 alignment = 1 << (irel->r_addend & RL78_RELAXA_ANUM);
2221
2222 if (erel->r_offset - irel->r_offset < alignment)
2223 continue;
2224
2225 nbytes = erel->r_offset - irel->r_offset;
2226 nbytes /= alignment;
2227 nbytes *= alignment;
2228
1740ba0c
NC		 2229 elf32_rl78_relax_delete_bytes (abfd, sec, erel->r_offset - nbytes, nbytes,
2230 next_alignment, erel->r_offset == sec->size);
9cea966c
DD		 2231 *again = TRUE;
2232
2233 continue;
2234 }
2235
2236 if (irel->r_addend & RL78_RELAXA_ELIGN)
2237 continue;
2238
2239 insn = contents + irel->r_offset;
2240
2241 nrelocs = irel->r_addend & RL78_RELAXA_RNUM;
2242
2243 /* At this point, we have an insn that is a candidate for linker
2244 relaxation. There are NRELOCS relocs following that may be
2245 relaxed, although each reloc may be made of more than one
2246 reloc entry (such as gp-rel symbols). */
2247
2248 /* Get the value of the symbol referred to by the reloc. Just
07d6d2b8
AM		 2249 in case this is the last reloc in the list, use the RL's
2250 addend to choose between this reloc (no addend) or the next
2251 (yes addend, which means at least one following reloc). */
9cea966c
DD		 2252
2253 /* srel points to the "current" reloction for this insn -
2254 actually the last reloc for a given operand, which is the one
2255 we need to update. We check the relaxations in the same
2256 order that the relocations happen, so we'll just push it
2257 along as we go. */
2258 srel = irel;
2259
2260 pc = sec->output_section->vma + sec->output_offset
2261 + srel->r_offset;
2262
1740ba0c
NC		 2263#define GET_RELOC \
2264 BFD_ASSERT (nrelocs > 0); \
2265 symval = OFFSET_FOR_RELOC (srel, &srel, &scale); \
2266 pcrel = symval - pc + srel->r_addend; \
9cea966c
DD		 2267 nrelocs --;
2268
2269#define SNIPNR(offset, nbytes) \
2270 elf32_rl78_relax_delete_bytes (abfd, sec, (insn - contents) + offset, nbytes, next_alignment, 0);
1740ba0c
NC		 2271
2272#define SNIP(offset, nbytes, newtype) \
07d6d2b8 2273 SNIPNR (offset, nbytes); \
9cea966c
DD		 2274 srel->r_info = ELF32_R_INFO (ELF32_R_SYM (srel->r_info), newtype)
2275
2276 /* The order of these bit tests must match the order that the
2277 relocs appear in. Since we sorted those by offset, we can
2278 predict them. */
2279
2280 /*----------------------------------------------------------------------*/
2281 /* EF ad BR $rel8 pcrel
2282 ED al ah BR !abs16 abs
2283 EE al ah BR $!rel16 pcrel
2284 EC al ah as BR !!abs20 abs
2285
2286 FD al ah CALL !abs16 abs
2287 FE al ah CALL $!rel16 pcrel
2288 FC al ah as CALL !!abs20 abs
2289
2290 DC ad BC $rel8
2291 DE ad BNC $rel8
2292 DD ad BZ $rel8
2293 DF ad BNZ $rel8
2294 61 C3 ad BH $rel8
2295 61 D3 ad BNH $rel8
2296 61 C8 EF ad SKC ; BR $rel8
2297 61 D8 EF ad SKNC ; BR $rel8
2298 61 E8 EF ad SKZ ; BR $rel8
2299 61 F8 EF ad SKNZ ; BR $rel8
2300 61 E3 EF ad SKH ; BR $rel8
2301 61 F3 EF ad SKNH ; BR $rel8
2302 */
2303
32e79d39 2304 if ((irel->r_addend & RL78_RELAXA_MASK) == RL78_RELAXA_BRA)
9cea966c 2305 {
1122dc88
DD		 2306 /* SKIP opcodes that skip non-branches will have a relax tag
2307 but no corresponding symbol to relax against; we just
2308 skip those. */
2309 if (irel->r_addend & RL78_RELAXA_RNUM)
2310 {
2311 GET_RELOC;
2312 }
9cea966c
DD		 2313
2314 switch (insn[0])
2315 {
e896287c
DD		 2316 case 0xdc: /* BC */
2317 case 0xdd: /* BZ */
2318 case 0xde: /* BNC */
2319 case 0xdf: /* BNZ */
2320 if (insn[1] == 0x03 && insn[2] == 0xee /* BR */
2321 && (srel->r_offset - irel->r_offset) > 1) /* a B<c> without its own reloc */
2322 {
2323 /* This is a "long" conditional as generated by gas:
2324 DC 03 EE ad.dr */
2325 if (pcrel < 127
2326 && pcrel > -127)
2327 {
2328 insn[0] ^= 0x02; /* invert conditional */
2329 SNIPNR (4, 1);
2330 SNIP (1, 2, R_RL78_DIR8S_PCREL);
2331 insn[1] = pcrel;
2332 *again = TRUE;
2333 }
2334 }
2335 break;
2336
9cea966c
DD		 2337 case 0xec: /* BR !!abs20 */
2338
2339 if (pcrel < 127
2340 && pcrel > -127)
2341 {
2342 insn[0] = 0xef;
2343 insn[1] = pcrel;
2344 SNIP (2, 2, R_RL78_DIR8S_PCREL);
2345 *again = TRUE;
2346 }
2347 else if (symval < 65536)
2348 {
2349 insn[0] = 0xed;
2350 insn[1] = symval & 0xff;
2351 insn[2] = symval >> 8;
e896287c 2352 SNIP (2, 1, R_RL78_DIR16U);
9cea966c
DD		 2353 *again = TRUE;
2354 }
2355 else if (pcrel < 32767
2356 && pcrel > -32767)
2357 {
2358 insn[0] = 0xee;
2359 insn[1] = pcrel & 0xff;
2360 insn[2] = pcrel >> 8;
2361 SNIP (2, 1, R_RL78_DIR16S_PCREL);
2362 *again = TRUE;
2363 }
2364 break;
2365
2366 case 0xee: /* BR $!pcrel16 */
2367 case 0xed: /* BR $!abs16 */
2368 if (pcrel < 127
2369 && pcrel > -127)
2370 {
2371 insn[0] = 0xef;
2372 insn[1] = pcrel;
2373 SNIP (2, 1, R_RL78_DIR8S_PCREL);
2374 *again = TRUE;
2375 }
2376 break;
2377
2378 case 0xfc: /* CALL !!abs20 */
2379 if (symval < 65536)
2380 {
2381 insn[0] = 0xfd;
2382 insn[1] = symval & 0xff;
2383 insn[2] = symval >> 8;
e896287c 2384 SNIP (2, 1, R_RL78_DIR16U);
9cea966c
DD		 2385 *again = TRUE;
2386 }
2387 else if (pcrel < 32767
2388 && pcrel > -32767)
2389 {
2390 insn[0] = 0xfe;
2391 insn[1] = pcrel & 0xff;
2392 insn[2] = pcrel >> 8;
2393 SNIP (2, 1, R_RL78_DIR16S_PCREL);
2394 *again = TRUE;
2395 }
2396 break;
2397
2398 case 0x61: /* PREFIX */
2399 /* For SKIP/BR, we change the BR opcode and delete the
2400 SKIP. That way, we don't have to find and change the
2401 relocation for the BR. */
1122dc88
DD		 2402 /* Note that, for the case where we're skipping some
2403 other insn, we have no "other" reloc but that's safe
2404 here anyway. */
9cea966c
DD		 2405 switch (insn[1])
2406 {
e896287c
DD		 2407 case 0xd3: /* BNH */
2408 case 0xc3: /* BH */
2409 if (insn[2] == 0x03 && insn[3] == 0xee
2410 && (srel->r_offset - irel->r_offset) > 2) /* a B<c> without its own reloc */
2411 {
2412 /* Another long branch by gas:
2413 61 D3 03 EE ad.dr */
2414 if (pcrel < 127
2415 && pcrel > -127)
2416 {
2417 insn[1] ^= 0x10; /* invert conditional */
2418 SNIPNR (5, 1);
2419 SNIP (2, 2, R_RL78_DIR8S_PCREL);
2420 insn[2] = pcrel;
2421 *again = TRUE;
2422 }
2423 }
2424 break;
2425
9cea966c
DD		 2426 case 0xc8: /* SKC */
2427 if (insn[2] == 0xef)
2428 {
2429 insn[2] = 0xde; /* BNC */
2430 SNIPNR (0, 2);
2431 }
2432 break;
2433
2434 case 0xd8: /* SKNC */
2435 if (insn[2] == 0xef)
2436 {
2437 insn[2] = 0xdc; /* BC */
2438 SNIPNR (0, 2);
2439 }
2440 break;
2441
2442 case 0xe8: /* SKZ */
2443 if (insn[2] == 0xef)
2444 {
2445 insn[2] = 0xdf; /* BNZ */
2446 SNIPNR (0, 2);
2447 }
2448 break;
2449
2450 case 0xf8: /* SKNZ */
2451 if (insn[2] == 0xef)
2452 {
2453 insn[2] = 0xdd; /* BZ */
2454 SNIPNR (0, 2);
2455 }
2456 break;
2457
2458 case 0xe3: /* SKH */
2459 if (insn[2] == 0xef)
2460 {
2461 insn[2] = 0xd3; /* BNH */
2462 SNIPNR (1, 1); /* we reuse the 0x61 prefix from the SKH */
2463 }
2464 break;
2465
2466 case 0xf3: /* SKNH */
2467 if (insn[2] == 0xef)
2468 {
2469 insn[2] = 0xc3; /* BH */
2470 SNIPNR (1, 1); /* we reuse the 0x61 prefix from the SKH */
2471 }
2472 break;
2473 }
2474 break;
2475 }
9cea966c
DD		 2476 }
2477
71eef2bd 2478 if ((irel->r_addend & RL78_RELAXA_MASK) == RL78_RELAXA_ADDR16
07d6d2b8 2479 && nrelocs > 0)
9cea966c
DD		 2480 {
2481 /*----------------------------------------------------------------------*/
2482 /* Some insns have both a 16-bit address operand and an 8-bit
2483 variant if the address is within a special range:
2484
2485 Address 16-bit operand SADDR range SFR range
2486 FFF00-FFFFF 0xff00-0xffff 0x00-0xff
07d6d2b8 2487 FFE20-FFF1F 0xfe20-0xff1f 0x00-0xff
9cea966c
DD		 2488
2489 The RELAX_ADDR16[] array has the insn encodings for the
2490 16-bit operand version, as well as the SFR and SADDR
2491 variants. We only need to replace the encodings and
2492 adjust the operand.
2493
2494 Note: we intentionally do not attempt to decode and skip
2495 any ES: prefix, as adding ES: means the addr16 (likely)
2496 no longer points to saddr/sfr space.
2497 */
2498
2499 int is_sfr;
2500 int is_saddr;
2501 int idx;
2502 int poff;
2503
2504 GET_RELOC;
2505
9cea966c
DD		 2506 if (0xffe20 <= symval && symval <= 0xfffff)
2507 {
2508
2509 is_saddr = (0xffe20 <= symval && symval <= 0xfff1f);
2510 is_sfr = (0xfff00 <= symval && symval <= 0xfffff);
2511
2512 for (idx = 0; relax_addr16[idx].insn != -1; idx ++)
2513 {
2514 if (relax_addr16[idx].prefix != -1
2515 && insn[0] == relax_addr16[idx].prefix
2516 && insn[1] == relax_addr16[idx].insn)
2517 {
2518 poff = 1;
2519 }
2520 else if (relax_addr16[idx].prefix == -1
2521 && insn[0] == relax_addr16[idx].insn)
2522 {
2523 poff = 0;
2524 }
2525 else
2526 continue;
2527
2528 /* We have a matched insn, and poff is 0 or 1 depending
2529 on the base pattern size. */
2530
2531 if (is_sfr && relax_addr16[idx].insn_for_sfr != -1)
2532 {
2533 insn[poff] = relax_addr16[idx].insn_for_sfr;
2534 SNIP (poff+2, 1, R_RL78_RH_SFR);
9cea966c
DD		 2535 }
2536
2537 else if (is_saddr && relax_addr16[idx].insn_for_saddr != -1)
2538 {
2539 insn[poff] = relax_addr16[idx].insn_for_saddr;
2540 SNIP (poff+2, 1, R_RL78_RH_SADDR);
9cea966c 2541 }
9cea966c
DD		 2542 }
2543 }
2544 }
9cea966c 2545 /*----------------------------------------------------------------------*/
9cea966c
DD		 2546 }
2547
2548 return TRUE;
2549
2550 error_return:
2551 if (free_relocs != NULL)
2552 free (free_relocs);
2553
2554 if (free_contents != NULL)
2555 free (free_contents);
2556
2557 if (shndx_buf != NULL)
2558 {
2559 shndx_hdr->contents = NULL;
2560 free (shndx_buf);
2561 }
2562
2563 if (free_intsyms != NULL)
2564 free (free_intsyms);
2565
99c513f6
DD		 2566 return TRUE;
2567}
2568
2569\f
2570
2571#define ELF_ARCH bfd_arch_rl78
2572#define ELF_MACHINE_CODE EM_RL78
2573#define ELF_MAXPAGESIZE 0x1000
2574
6d00b590 2575#define TARGET_LITTLE_SYM rl78_elf32_vec
99c513f6
DD		 2576#define TARGET_LITTLE_NAME "elf32-rl78"
2577
2578#define elf_info_to_howto_rel NULL
2579#define elf_info_to_howto rl78_info_to_howto_rela
2580#define elf_backend_object_p rl78_elf_object_p
2581#define elf_backend_relocate_section rl78_elf_relocate_section
07d6d2b8 2582#define elf_symbol_leading_char ('_')
99c513f6
DD		 2583#define elf_backend_can_gc_sections 1
2584
2585#define bfd_elf32_bfd_reloc_type_lookup rl78_reloc_type_lookup
2586#define bfd_elf32_bfd_reloc_name_lookup rl78_reloc_name_lookup
2587#define bfd_elf32_bfd_set_private_flags rl78_elf_set_private_flags
2588#define bfd_elf32_bfd_merge_private_bfd_data rl78_elf_merge_private_bfd_data
2589#define bfd_elf32_bfd_print_private_bfd_data rl78_elf_print_private_bfd_data
2590
2591#define bfd_elf32_bfd_relax_section rl78_elf_relax_section
07d6d2b8 2592#define elf_backend_check_relocs rl78_elf_check_relocs
99c513f6
DD		 2593#define elf_backend_always_size_sections \
2594 rl78_elf_always_size_sections
2595#define elf_backend_finish_dynamic_sections \
2596 rl78_elf_finish_dynamic_sections
2597
2598#include "elf32-target.h"
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