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[binutils.git] / bfd / elf32-rl78.c
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99c513f6 1/* Renesas RL78 specific support for 32-bit ELF.
219d1afa 2 Copyright (C) 2011-2018 Free Software Foundation, Inc.
99c513f6
DD		 3
4 This file is part of BFD, the Binary File Descriptor library.
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3 of the License, or
9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
863f7a5f
NC		 18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
99c513f6
DD		 20
21#include "sysdep.h"
22#include "bfd.h"
23#include "bfd_stdint.h"
24#include "libbfd.h"
25#include "elf-bfd.h"
26#include "elf/rl78.h"
27#include "libiberty.h"
28
29#define valid_16bit_address(v) ((v) <= 0x0ffff || (v) >= 0xf0000)
30
31#define RL78REL(n,sz,bit,shift,complain,pcrel) \
32 HOWTO (R_RL78_##n, shift, sz, bit, pcrel, 0, complain_overflow_ ## complain, \
33 bfd_elf_generic_reloc, "R_RL78_" #n, FALSE, 0, ~0, FALSE)
34
6ff71e76
NC		 35static bfd_reloc_status_type rl78_special_reloc (bfd *, arelent *, asymbol *, void *,
36 asection *, bfd *, char **);
37
38/* FIXME: We could omit the SHIFT parameter, it is always zero. */
39#define RL78_OP_REL(n,sz,bit,shift,complain,pcrel) \
40 HOWTO (R_RL78_##n, shift, sz, bit, pcrel, 0, complain_overflow_ ## complain, \
41 rl78_special_reloc, "R_RL78_" #n, FALSE, 0, ~0, FALSE)
42
99c513f6
DD		 43/* Note that the relocations around 0x7f are internal to this file;
44 feel free to move them as needed to avoid conflicts with published
45 relocation numbers. */
46
47static reloc_howto_type rl78_elf_howto_table [] =
48{
07d6d2b8
AM		 49 RL78REL (NONE, 3, 0, 0, dont, FALSE),
50 RL78REL (DIR32, 2, 32, 0, signed, FALSE),
51 RL78REL (DIR24S, 2, 24, 0, signed, FALSE),
52 RL78REL (DIR16, 1, 16, 0, dont, FALSE),
53 RL78REL (DIR16U, 1, 16, 0, unsigned, FALSE),
54 RL78REL (DIR16S, 1, 16, 0, signed, FALSE),
55 RL78REL (DIR8, 0, 8, 0, dont, FALSE),
56 RL78REL (DIR8U, 0, 8, 0, unsigned, FALSE),
57 RL78REL (DIR8S, 0, 8, 0, signed, FALSE),
99c513f6
DD		 58 RL78REL (DIR24S_PCREL, 2, 24, 0, signed, TRUE),
59 RL78REL (DIR16S_PCREL, 1, 16, 0, signed, TRUE),
07d6d2b8
AM		 60 RL78REL (DIR8S_PCREL, 0, 8, 0, signed, TRUE),
61 RL78REL (DIR16UL, 1, 16, 2, unsigned, FALSE),
62 RL78REL (DIR16UW, 1, 16, 1, unsigned, FALSE),
63 RL78REL (DIR8UL, 0, 8, 2, unsigned, FALSE),
64 RL78REL (DIR8UW, 0, 8, 1, unsigned, FALSE),
65 RL78REL (DIR32_REV, 1, 16, 0, dont, FALSE),
66 RL78REL (DIR16_REV, 1, 16, 0, dont, FALSE),
67 RL78REL (DIR3U_PCREL, 0, 3, 0, dont, TRUE),
99c513f6
DD		 68
69 EMPTY_HOWTO (0x13),
70 EMPTY_HOWTO (0x14),
71 EMPTY_HOWTO (0x15),
72 EMPTY_HOWTO (0x16),
73 EMPTY_HOWTO (0x17),
74 EMPTY_HOWTO (0x18),
75 EMPTY_HOWTO (0x19),
76 EMPTY_HOWTO (0x1a),
77 EMPTY_HOWTO (0x1b),
78 EMPTY_HOWTO (0x1c),
79 EMPTY_HOWTO (0x1d),
80 EMPTY_HOWTO (0x1e),
81 EMPTY_HOWTO (0x1f),
82
83 EMPTY_HOWTO (0x20),
84 EMPTY_HOWTO (0x21),
85 EMPTY_HOWTO (0x22),
86 EMPTY_HOWTO (0x23),
87 EMPTY_HOWTO (0x24),
88 EMPTY_HOWTO (0x25),
89 EMPTY_HOWTO (0x26),
90 EMPTY_HOWTO (0x27),
91 EMPTY_HOWTO (0x28),
92 EMPTY_HOWTO (0x29),
93 EMPTY_HOWTO (0x2a),
94 EMPTY_HOWTO (0x2b),
95 EMPTY_HOWTO (0x2c),
07d6d2b8 96 RL78REL (RH_RELAX, 0, 0, 0, dont, FALSE),
99c513f6
DD		 97
98 EMPTY_HOWTO (0x2e),
07d6d2b8 99 RL78REL (RH_SADDR, 0, 0, 0, dont, FALSE),
99c513f6
DD		 100 EMPTY_HOWTO (0x30),
101 EMPTY_HOWTO (0x31),
102 EMPTY_HOWTO (0x32),
103 EMPTY_HOWTO (0x33),
104 EMPTY_HOWTO (0x34),
105 EMPTY_HOWTO (0x35),
106 EMPTY_HOWTO (0x36),
107 EMPTY_HOWTO (0x37),
108 EMPTY_HOWTO (0x38),
109 EMPTY_HOWTO (0x39),
110 EMPTY_HOWTO (0x3a),
111 EMPTY_HOWTO (0x3b),
112 EMPTY_HOWTO (0x3c),
113 EMPTY_HOWTO (0x3d),
114 EMPTY_HOWTO (0x3e),
115 EMPTY_HOWTO (0x3f),
116 EMPTY_HOWTO (0x40),
117
07d6d2b8
AM		 118 RL78_OP_REL (ABS32, 2, 32, 0, dont, FALSE),
119 RL78_OP_REL (ABS24S, 2, 24, 0, signed, FALSE),
120 RL78_OP_REL (ABS16, 1, 16, 0, dont, FALSE),
121 RL78_OP_REL (ABS16U, 1, 16, 0, unsigned, FALSE),
122 RL78_OP_REL (ABS16S, 1, 16, 0, signed, FALSE),
123 RL78_OP_REL (ABS8, 0, 8, 0, dont, FALSE),
124 RL78_OP_REL (ABS8U, 0, 8, 0, unsigned, FALSE),
125 RL78_OP_REL (ABS8S, 0, 8, 0, signed, FALSE),
126 RL78_OP_REL (ABS24S_PCREL, 2, 24, 0, signed, TRUE),
127 RL78_OP_REL (ABS16S_PCREL, 1, 16, 0, signed, TRUE),
128 RL78_OP_REL (ABS8S_PCREL, 0, 8, 0, signed, TRUE),
129 RL78_OP_REL (ABS16UL, 1, 16, 0, unsigned, FALSE),
130 RL78_OP_REL (ABS16UW, 1, 16, 0, unsigned, FALSE),
131 RL78_OP_REL (ABS8UL, 0, 8, 0, unsigned, FALSE),
132 RL78_OP_REL (ABS8UW, 0, 8, 0, unsigned, FALSE),
133 RL78_OP_REL (ABS32_REV, 2, 32, 0, dont, FALSE),
134 RL78_OP_REL (ABS16_REV, 1, 16, 0, dont, FALSE),
99c513f6
DD		 135
136#define STACK_REL_P(x) ((x) <= R_RL78_ABS16_REV && (x) >= R_RL78_ABS32)
137
138 EMPTY_HOWTO (0x52),
139 EMPTY_HOWTO (0x53),
140 EMPTY_HOWTO (0x54),
141 EMPTY_HOWTO (0x55),
142 EMPTY_HOWTO (0x56),
143 EMPTY_HOWTO (0x57),
144 EMPTY_HOWTO (0x58),
145 EMPTY_HOWTO (0x59),
146 EMPTY_HOWTO (0x5a),
147 EMPTY_HOWTO (0x5b),
148 EMPTY_HOWTO (0x5c),
149 EMPTY_HOWTO (0x5d),
150 EMPTY_HOWTO (0x5e),
151 EMPTY_HOWTO (0x5f),
152 EMPTY_HOWTO (0x60),
153 EMPTY_HOWTO (0x61),
154 EMPTY_HOWTO (0x62),
155 EMPTY_HOWTO (0x63),
156 EMPTY_HOWTO (0x64),
157 EMPTY_HOWTO (0x65),
158 EMPTY_HOWTO (0x66),
159 EMPTY_HOWTO (0x67),
160 EMPTY_HOWTO (0x68),
161 EMPTY_HOWTO (0x69),
162 EMPTY_HOWTO (0x6a),
163 EMPTY_HOWTO (0x6b),
164 EMPTY_HOWTO (0x6c),
165 EMPTY_HOWTO (0x6d),
166 EMPTY_HOWTO (0x6e),
167 EMPTY_HOWTO (0x6f),
168 EMPTY_HOWTO (0x70),
169 EMPTY_HOWTO (0x71),
170 EMPTY_HOWTO (0x72),
171 EMPTY_HOWTO (0x73),
172 EMPTY_HOWTO (0x74),
173 EMPTY_HOWTO (0x75),
174 EMPTY_HOWTO (0x76),
175 EMPTY_HOWTO (0x77),
176
177 EMPTY_HOWTO (0x78),
178 EMPTY_HOWTO (0x79),
179 EMPTY_HOWTO (0x7a),
180 EMPTY_HOWTO (0x7b),
181 EMPTY_HOWTO (0x7c),
182 EMPTY_HOWTO (0x7d),
183 EMPTY_HOWTO (0x7e),
184 EMPTY_HOWTO (0x7f),
185
07d6d2b8
AM		 186 RL78_OP_REL (SYM, 2, 32, 0, dont, FALSE),
187 RL78_OP_REL (OPneg, 2, 32, 0, dont, FALSE),
188 RL78_OP_REL (OPadd, 2, 32, 0, dont, FALSE),
189 RL78_OP_REL (OPsub, 2, 32, 0, dont, FALSE),
190 RL78_OP_REL (OPmul, 2, 32, 0, dont, FALSE),
191 RL78_OP_REL (OPdiv, 2, 32, 0, dont, FALSE),
192 RL78_OP_REL (OPshla, 2, 32, 0, dont, FALSE),
193 RL78_OP_REL (OPshra, 2, 32, 0, dont, FALSE),
6ff71e76 194 RL78_OP_REL (OPsctsize, 2, 32, 0, dont, FALSE),
99c513f6
DD		 195 EMPTY_HOWTO (0x89),
196 EMPTY_HOWTO (0x8a),
197 EMPTY_HOWTO (0x8b),
198 EMPTY_HOWTO (0x8c),
6ff71e76 199 RL78_OP_REL (OPscttop, 2, 32, 0, dont, FALSE),
99c513f6
DD		 200 EMPTY_HOWTO (0x8e),
201 EMPTY_HOWTO (0x8f),
07d6d2b8
AM		 202 RL78_OP_REL (OPand, 2, 32, 0, dont, FALSE),
203 RL78_OP_REL (OPor, 2, 32, 0, dont, FALSE),
204 RL78_OP_REL (OPxor, 2, 32, 0, dont, FALSE),
205 RL78_OP_REL (OPnot, 2, 32, 0, dont, FALSE),
206 RL78_OP_REL (OPmod, 2, 32, 0, dont, FALSE),
6ff71e76
NC		 207 RL78_OP_REL (OPromtop, 2, 32, 0, dont, FALSE),
208 RL78_OP_REL (OPramtop, 2, 32, 0, dont, FALSE)
99c513f6
DD		 209};
210\f
211/* Map BFD reloc types to RL78 ELF reloc types. */
212
213struct rl78_reloc_map
214{
215 bfd_reloc_code_real_type bfd_reloc_val;
07d6d2b8 216 unsigned int rl78_reloc_val;
99c513f6
DD		 217};
218
219static const struct rl78_reloc_map rl78_reloc_map [] =
220{
221 { BFD_RELOC_NONE, R_RL78_NONE },
222 { BFD_RELOC_8, R_RL78_DIR8S },
223 { BFD_RELOC_16, R_RL78_DIR16S },
224 { BFD_RELOC_24, R_RL78_DIR24S },
225 { BFD_RELOC_32, R_RL78_DIR32 },
226 { BFD_RELOC_RL78_16_OP, R_RL78_DIR16 },
227 { BFD_RELOC_RL78_DIR3U_PCREL, R_RL78_DIR3U_PCREL },
228 { BFD_RELOC_8_PCREL, R_RL78_DIR8S_PCREL },
229 { BFD_RELOC_16_PCREL, R_RL78_DIR16S_PCREL },
230 { BFD_RELOC_24_PCREL, R_RL78_DIR24S_PCREL },
231 { BFD_RELOC_RL78_8U, R_RL78_DIR8U },
232 { BFD_RELOC_RL78_16U, R_RL78_DIR16U },
233 { BFD_RELOC_RL78_SYM, R_RL78_SYM },
234 { BFD_RELOC_RL78_OP_SUBTRACT, R_RL78_OPsub },
235 { BFD_RELOC_RL78_OP_NEG, R_RL78_OPneg },
236 { BFD_RELOC_RL78_OP_AND, R_RL78_OPand },
237 { BFD_RELOC_RL78_OP_SHRA, R_RL78_OPshra },
238 { BFD_RELOC_RL78_ABS8, R_RL78_ABS8 },
239 { BFD_RELOC_RL78_ABS16, R_RL78_ABS16 },
240 { BFD_RELOC_RL78_ABS16_REV, R_RL78_ABS16_REV },
241 { BFD_RELOC_RL78_ABS32, R_RL78_ABS32 },
242 { BFD_RELOC_RL78_ABS32_REV, R_RL78_ABS32_REV },
243 { BFD_RELOC_RL78_ABS16UL, R_RL78_ABS16UL },
244 { BFD_RELOC_RL78_ABS16UW, R_RL78_ABS16UW },
9cea966c 245 { BFD_RELOC_RL78_ABS16U, R_RL78_ABS16U },
54f66250 246 { BFD_RELOC_RL78_SADDR, R_RL78_RH_SADDR },
9cea966c 247 { BFD_RELOC_RL78_RELAX, R_RL78_RH_RELAX }
99c513f6
DD		 248};
249
250static reloc_howto_type *
251rl78_reloc_type_lookup (bfd * abfd ATTRIBUTE_UNUSED,
252 bfd_reloc_code_real_type code)
253{
254 unsigned int i;
255
256 if (code == BFD_RELOC_RL78_32_OP)
257 return rl78_elf_howto_table + R_RL78_DIR32;
258
0ba38529 259 for (i = ARRAY_SIZE (rl78_reloc_map); i--;)
99c513f6
DD		 260 if (rl78_reloc_map [i].bfd_reloc_val == code)
261 return rl78_elf_howto_table + rl78_reloc_map[i].rl78_reloc_val;
262
263 return NULL;
264}
265
266static reloc_howto_type *
267rl78_reloc_name_lookup (bfd * abfd ATTRIBUTE_UNUSED, const char * r_name)
268{
269 unsigned int i;
270
271 for (i = 0; i < ARRAY_SIZE (rl78_elf_howto_table); i++)
272 if (rl78_elf_howto_table[i].name != NULL
273 && strcasecmp (rl78_elf_howto_table[i].name, r_name) == 0)
274 return rl78_elf_howto_table + i;
275
276 return NULL;
277}
278
279/* Set the howto pointer for an RL78 ELF reloc. */
280
281static void
07d6d2b8
AM		 282rl78_info_to_howto_rela (bfd * abfd ATTRIBUTE_UNUSED,
283 arelent * cache_ptr,
99c513f6
DD		 284 Elf_Internal_Rela * dst)
285{
286 unsigned int r_type;
287
288 r_type = ELF32_R_TYPE (dst->r_info);
5860e3f8
NC		 289 if (r_type >= (unsigned int) R_RL78_max)
290 {
695344c0 291 /* xgettext:c-format */
871b3ab2 292 _bfd_error_handler (_("%pB: invalid RL78 reloc number: %d"), abfd, r_type);
5860e3f8
NC		 293 r_type = 0;
294 }
99c513f6
DD		 295 cache_ptr->howto = rl78_elf_howto_table + r_type;
296}
297\f
298static bfd_vma
07d6d2b8 299get_symbol_value (const char * name,
99c513f6 300 struct bfd_link_info * info,
07d6d2b8
AM		 301 bfd * input_bfd,
302 asection * input_section,
99c513f6
DD		 303 int offset)
304{
99c513f6
DD		 305 struct bfd_link_hash_entry * h;
306
6ff71e76
NC		 307 if (info == NULL)
308 return 0;
309
99c513f6
DD		 310 h = bfd_link_hash_lookup (info->hash, name, FALSE, FALSE, TRUE);
311
312 if (h == NULL
313 || (h->type != bfd_link_hash_defined
314 && h->type != bfd_link_hash_defweak))
6ff71e76 315 {
1a72702b 316 (*info->callbacks->undefined_symbol)
6ff71e76 317 (info, name, input_bfd, input_section, offset, TRUE);
6ff71e76
NC		 318 return 0;
319 }
99c513f6 320
6ff71e76
NC		 321 return (h->u.def.value
322 + h->u.def.section->output_section->vma
323 + h->u.def.section->output_offset);
99c513f6
DD		 324}
325
326static bfd_vma
1a72702b 327get_romstart (struct bfd_link_info * info,
07d6d2b8
AM		 328 bfd * abfd,
329 asection * sec,
99c513f6
DD		 330 int offset)
331{
332 static bfd_boolean cached = FALSE;
333 static bfd_vma cached_value = 0;
334
335 if (!cached)
336 {
1a72702b 337 cached_value = get_symbol_value ("_start", info, abfd, sec, offset);
99c513f6
DD		 338 cached = TRUE;
339 }
340 return cached_value;
341}
342
343static bfd_vma
1a72702b 344get_ramstart (struct bfd_link_info * info,
07d6d2b8
AM		 345 bfd * abfd,
346 asection * sec,
99c513f6
DD		 347 int offset)
348{
349 static bfd_boolean cached = FALSE;
350 static bfd_vma cached_value = 0;
351
352 if (!cached)
353 {
1a72702b 354 cached_value = get_symbol_value ("__datastart", info, abfd, sec, offset);
99c513f6
DD		 355 cached = TRUE;
356 }
357 return cached_value;
358}
359
360#define NUM_STACK_ENTRIES 16
361static int32_t rl78_stack [ NUM_STACK_ENTRIES ];
362static unsigned int rl78_stack_top;
363
364#define RL78_STACK_PUSH(val) \
365 do \
366 { \
367 if (rl78_stack_top < NUM_STACK_ENTRIES) \
07d6d2b8 368 rl78_stack [rl78_stack_top ++] = (val); \
99c513f6 369 else \
6ff71e76 370 _bfd_error_handler (_("Internal Error: RL78 reloc stack overflow")); \
99c513f6
DD		 371 } \
372 while (0)
373
374#define RL78_STACK_POP(dest) \
375 do \
376 { \
377 if (rl78_stack_top > 0) \
07d6d2b8 378 (dest) = rl78_stack [-- rl78_stack_top];\
99c513f6 379 else \
6ff71e76 380 { \
07d6d2b8
AM		 381 _bfd_error_handler (_("Internal Error: RL78 reloc stack underflow")); \
382 (dest) = 0; \
383 } \
99c513f6
DD		 384 } \
385 while (0)
386
6ff71e76
NC		 387/* Special handling for RL78 complex relocs. Returns the
388 value of the reloc, or 0 for relocs which do not generate
389 a result. SYMVAL is the value of the symbol for relocs
390 which use a symbolic argument. */
391
392static bfd_vma
393rl78_compute_complex_reloc (unsigned long r_type,
07d6d2b8
AM		 394 bfd_vma symval,
395 asection * input_section)
6ff71e76
NC		 396{
397 int32_t tmp1, tmp2;
398 bfd_vma relocation;
399
400 switch (r_type)
401 {
402 default:
403 return 0;
404
405 case R_RL78_ABS24S_PCREL:
406 case R_RL78_ABS16S_PCREL:
407 case R_RL78_ABS8S_PCREL:
408 RL78_STACK_POP (relocation);
409 relocation -= input_section->output_section->vma + input_section->output_offset;
410 return relocation;
411
412 case R_RL78_ABS32:
413 case R_RL78_ABS32_REV:
414 case R_RL78_ABS16:
415 case R_RL78_ABS16_REV:
416 case R_RL78_ABS16S:
417 case R_RL78_ABS16U:
418 case R_RL78_ABS8:
419 case R_RL78_ABS8U:
420 case R_RL78_ABS8S:
421 RL78_STACK_POP (relocation);
422 return relocation;
423
424 case R_RL78_ABS16UL:
425 case R_RL78_ABS8UL:
426 RL78_STACK_POP (relocation);
427 return relocation >> 2;
428
429 case R_RL78_ABS16UW:
430 case R_RL78_ABS8UW:
431 RL78_STACK_POP (relocation);
432 return relocation >> 1;
433
434 /* The rest of the relocs compute values and then push them onto the stack. */
435 case R_RL78_OPramtop:
436 case R_RL78_OPromtop:
437 case R_RL78_SYM:
438 RL78_STACK_PUSH (symval);
439 return 0;
1b786873 440
6ff71e76
NC		 441 case R_RL78_OPneg:
442 RL78_STACK_POP (tmp1);
443 tmp1 = - tmp1;
444 RL78_STACK_PUSH (tmp1);
445 return 0;
446
447 case R_RL78_OPadd:
448 RL78_STACK_POP (tmp2);
449 RL78_STACK_POP (tmp1);
450 tmp1 += tmp2;
451 RL78_STACK_PUSH (tmp1);
452 return 0;
453
454 case R_RL78_OPsub:
455 /* For the expression "A - B", the assembler pushes A,
456 then B, then OPSUB. So the first op we pop is B, not A. */
457 RL78_STACK_POP (tmp2); /* B */
458 RL78_STACK_POP (tmp1); /* A */
459 tmp1 -= tmp2; /* A - B */
460 RL78_STACK_PUSH (tmp1);
461 return 0;
462
463 case R_RL78_OPmul:
464 RL78_STACK_POP (tmp2);
465 RL78_STACK_POP (tmp1);
466 tmp1 *= tmp2;
467 RL78_STACK_PUSH (tmp1);
468 return 0;
469
470 case R_RL78_OPdiv:
471 RL78_STACK_POP (tmp2);
472 RL78_STACK_POP (tmp1);
473 tmp1 /= tmp2;
474 RL78_STACK_PUSH (tmp1);
475 return 0;
476
477 case R_RL78_OPshla:
478 RL78_STACK_POP (tmp2);
479 RL78_STACK_POP (tmp1);
480 tmp1 <<= tmp2;
481 RL78_STACK_PUSH (tmp1);
482 return 0;
483
484 case R_RL78_OPshra:
485 RL78_STACK_POP (tmp2);
486 RL78_STACK_POP (tmp1);
487 tmp1 >>= tmp2;
488 RL78_STACK_PUSH (tmp1);
489 return 0;
490
491 case R_RL78_OPsctsize:
492 RL78_STACK_PUSH (input_section->size);
493 return 0;
494
495 case R_RL78_OPscttop:
496 RL78_STACK_PUSH (input_section->output_section->vma);
497 return 0;
498
499 case R_RL78_OPand:
500 RL78_STACK_POP (tmp2);
501 RL78_STACK_POP (tmp1);
502 tmp1 &= tmp2;
503 RL78_STACK_PUSH (tmp1);
504 return 0;
505
506 case R_RL78_OPor:
507 RL78_STACK_POP (tmp2);
508 RL78_STACK_POP (tmp1);
509 tmp1 |= tmp2;
510 RL78_STACK_PUSH (tmp1);
511 return 0;
512
513 case R_RL78_OPxor:
514 RL78_STACK_POP (tmp2);
515 RL78_STACK_POP (tmp1);
516 tmp1 ^= tmp2;
517 RL78_STACK_PUSH (tmp1);
518 return 0;
519
520 case R_RL78_OPnot:
521 RL78_STACK_POP (tmp1);
522 tmp1 = ~ tmp1;
523 RL78_STACK_PUSH (tmp1);
524 return 0;
525
526 case R_RL78_OPmod:
527 RL78_STACK_POP (tmp2);
528 RL78_STACK_POP (tmp1);
529 tmp1 %= tmp2;
530 RL78_STACK_PUSH (tmp1);
531 return 0;
532 }
533}
534
535#undef RL78_STACK_PUSH
536#undef RL78_STACK_POP
537
538#define OP(i) (contents[reloc->address + (i)])
539
540static bfd_reloc_status_type
541rl78_special_reloc (bfd * input_bfd,
542 arelent * reloc,
543 asymbol * symbol,
544 void * data,
545 asection * input_section,
546 bfd * output_bfd ATTRIBUTE_UNUSED,
547 char ** error_message ATTRIBUTE_UNUSED)
548{
07d6d2b8
AM		 549 bfd_reloc_status_type r = bfd_reloc_ok;
550 bfd_vma relocation = 0;
551 unsigned long r_type = reloc->howto->type;
552 bfd_byte * contents = data;
6ff71e76
NC		 553
554 /* If necessary, compute the symbolic value of the relocation. */
555 switch (r_type)
556 {
557 case R_RL78_SYM:
558 relocation = (symbol->value
559 + symbol->section->output_section->vma
560 + symbol->section->output_offset
561 + reloc->addend);
562 break;
563
564 case R_RL78_OPromtop:
1a72702b 565 relocation = get_romstart (NULL, input_bfd, input_section,
6ff71e76
NC		 566 reloc->address);
567 break;
568
569 case R_RL78_OPramtop:
1a72702b 570 relocation = get_ramstart (NULL, input_bfd, input_section,
6ff71e76
NC		 571 reloc->address);
572 break;
573 }
574
575 /* Get the value of the relocation. */
576 relocation = rl78_compute_complex_reloc (r_type, relocation, input_section);
577
578 /* If the relocation alters the contents of the section then apply it now.
579 Note - since this function is called from
580 bfd_generic_get_relocated_section_contents via bfd_perform_relocation,
581 and not from the linker, we do not perform any range checking. The
582 clients who are calling us are only interested in some relocated section
583 contents, and not any linkage problems that might occur later. */
584 switch (r_type)
585 {
586 case R_RL78_ABS32:
587 OP (0) = relocation;
588 OP (1) = relocation >> 8;
589 OP (2) = relocation >> 16;
590 OP (3) = relocation >> 24;
591 break;
592
593 case R_RL78_ABS32_REV:
594 OP (3) = relocation;
595 OP (2) = relocation >> 8;
596 OP (1) = relocation >> 16;
597 OP (0) = relocation >> 24;
598 break;
599
600 case R_RL78_ABS24S_PCREL:
601 case R_RL78_ABS24S:
602 OP (0) = relocation;
603 OP (1) = relocation >> 8;
604 OP (2) = relocation >> 16;
605 break;
606
607 case R_RL78_ABS16_REV:
608 OP (1) = relocation;
609 OP (0) = relocation >> 8;
610 break;
611
612 case R_RL78_ABS16S_PCREL:
613 case R_RL78_ABS16:
614 case R_RL78_ABS16S:
615 case R_RL78_ABS16U:
616 case R_RL78_ABS16UL:
617 case R_RL78_ABS16UW:
618 OP (0) = relocation;
619 OP (1) = relocation >> 8;
620 break;
621
622 case R_RL78_ABS8S_PCREL:
623 case R_RL78_ABS8:
624 case R_RL78_ABS8U:
625 case R_RL78_ABS8UL:
626 case R_RL78_ABS8UW:
627 case R_RL78_ABS8S:
628 OP (0) = relocation;
629 break;
630
631 default:
632 break;
633 }
634
635 return r;
636}
637
638#undef OP
639#define OP(i) (contents[rel->r_offset + (i)])
640
99c513f6
DD		 641/* Relocate an RL78 ELF section.
642 There is some attempt to make this function usable for many architectures,
643 both USE_REL and USE_RELA ['twould be nice if such a critter existed],
644 if only to serve as a learning tool.
645
646 The RELOCATE_SECTION function is called by the new ELF backend linker
647 to handle the relocations for a section.
648
649 The relocs are always passed as Rela structures; if the section
650 actually uses Rel structures, the r_addend field will always be
651 zero.
652
653 This function is responsible for adjusting the section contents as
654 necessary, and (if using Rela relocs and generating a relocatable
655 output file) adjusting the reloc addend as necessary.
656
657 This function does not have to worry about setting the reloc
658 address or the reloc symbol index.
659
660 LOCAL_SYMS is a pointer to the swapped in local symbols.
661
662 LOCAL_SECTIONS is an array giving the section in the input file
663 corresponding to the st_shndx field of each local symbol.
664
665 The global hash table entry for the global symbols can be found
666 via elf_sym_hashes (input_bfd).
667
668 When generating relocatable output, this function must handle
669 STB_LOCAL/STT_SECTION symbols specially. The output symbol is
670 going to be the section symbol corresponding to the output
671 section, which means that the addend must be adjusted
672 accordingly. */
673
674static bfd_boolean
675rl78_elf_relocate_section
07d6d2b8 676 (bfd * output_bfd,
99c513f6 677 struct bfd_link_info * info,
07d6d2b8
AM		 678 bfd * input_bfd,
679 asection * input_section,
680 bfd_byte * contents,
99c513f6 681 Elf_Internal_Rela * relocs,
07d6d2b8
AM		 682 Elf_Internal_Sym * local_syms,
683 asection ** local_sections)
99c513f6 684{
07d6d2b8 685 Elf_Internal_Shdr * symtab_hdr;
99c513f6 686 struct elf_link_hash_entry ** sym_hashes;
07d6d2b8
AM		 687 Elf_Internal_Rela * rel;
688 Elf_Internal_Rela * relend;
99c513f6
DD		 689 asection *splt;
690
691 symtab_hdr = & elf_tdata (input_bfd)->symtab_hdr;
692 sym_hashes = elf_sym_hashes (input_bfd);
693 relend = relocs + input_section->reloc_count;
694
ce558b89 695 splt = elf_hash_table (info)->splt;
99c513f6
DD		 696
697 for (rel = relocs; rel < relend; rel ++)
698 {
07d6d2b8
AM		 699 reloc_howto_type * howto;
700 unsigned long r_symndx;
701 Elf_Internal_Sym * sym;
702 asection * sec;
99c513f6 703 struct elf_link_hash_entry * h;
07d6d2b8
AM		 704 bfd_vma relocation;
705 bfd_reloc_status_type r;
706 const char * name = NULL;
707 bfd_boolean unresolved_reloc = TRUE;
708 int r_type;
99c513f6
DD		 709
710 r_type = ELF32_R_TYPE (rel->r_info);
711 r_symndx = ELF32_R_SYM (rel->r_info);
712
713 howto = rl78_elf_howto_table + ELF32_R_TYPE (rel->r_info);
07d6d2b8 714 h = NULL;
99c513f6
DD		 715 sym = NULL;
716 sec = NULL;
717 relocation = 0;
718
719 if (r_symndx < symtab_hdr->sh_info)
720 {
721 sym = local_syms + r_symndx;
722 sec = local_sections [r_symndx];
723 relocation = _bfd_elf_rela_local_sym (output_bfd, sym, & sec, rel);
724
725 name = bfd_elf_string_from_elf_section
726 (input_bfd, symtab_hdr->sh_link, sym->st_name);
727 name = (sym->st_name == 0) ? bfd_section_name (input_bfd, sec) : name;
728 }
729 else
730 {
62d887d4
L		 731 bfd_boolean warned ATTRIBUTE_UNUSED;
732 bfd_boolean ignored ATTRIBUTE_UNUSED;
99c513f6
DD		 733
734 RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel,
735 r_symndx, symtab_hdr, sym_hashes, h,
736 sec, relocation, unresolved_reloc,
62d887d4 737 warned, ignored);
99c513f6
DD		 738
739 name = h->root.root.string;
740 }
741
95b57ade 742 if (sec != NULL && discarded_section (sec))
99c513f6 743 RELOC_AGAINST_DISCARDED_SECTION (info, input_bfd, input_section,
545fd46b 744 rel, 1, relend, howto, 0, contents);
99c513f6 745
0e1862bb 746 if (bfd_link_relocatable (info))
99c513f6
DD		 747 {
748 /* This is a relocatable link. We don't have to change
07d6d2b8
AM		 749 anything, unless the reloc is against a section symbol,
750 in which case we have to adjust according to where the
751 section symbol winds up in the output section. */
99c513f6
DD		 752 if (sym != NULL && ELF_ST_TYPE (sym->st_info) == STT_SECTION)
753 rel->r_addend += sec->output_offset;
754 continue;
755 }
756
757 switch (ELF32_R_TYPE (rel->r_info))
758 {
759 case R_RL78_DIR16S:
760 {
761 bfd_vma *plt_offset;
762
763 if (h != NULL)
764 plt_offset = &h->plt.offset;
765 else
766 plt_offset = elf_local_got_offsets (input_bfd) + r_symndx;
767
9cea966c 768 if (! valid_16bit_address (relocation))
99c513f6 769 {
99c513f6
DD		 770 /* If this is the first time we've processed this symbol,
771 fill in the plt entry with the correct symbol address. */
772 if ((*plt_offset & 1) == 0)
773 {
774 unsigned int x;
775
776 x = 0x000000ec; /* br !!abs24 */
777 x |= (relocation << 8) & 0xffffff00;
778 bfd_put_32 (input_bfd, x, splt->contents + *plt_offset);
779 *plt_offset |= 1;
780 }
781
782 relocation = (splt->output_section->vma
783 + splt->output_offset
784 + (*plt_offset & -2));
785 if (name)
786 {
787 char *newname = bfd_malloc (strlen(name)+5);
788 strcpy (newname, name);
789 strcat(newname, ".plt");
790 _bfd_generic_link_add_one_symbol (info,
791 input_bfd,
792 newname,
793 BSF_FUNCTION | BSF_WEAK,
794 splt,
795 (*plt_offset & -2),
796 0,
797 1,
798 0,
799 0);
800 }
801 }
802 }
803 break;
804 }
805
806 if (h != NULL && h->root.type == bfd_link_hash_undefweak)
807 /* If the symbol is undefined and weak
808 then the relocation resolves to zero. */
809 relocation = 0;
810 else
811 {
812 if (howto->pc_relative)
813 {
814 relocation -= (input_section->output_section->vma
815 + input_section->output_offset
816 + rel->r_offset);
817 relocation -= bfd_get_reloc_size (howto);
818 }
819
820 relocation += rel->r_addend;
821 }
822
823 r = bfd_reloc_ok;
824
825#define RANGE(a,b) if (a > (long) relocation || (long) relocation > b) r = bfd_reloc_overflow
99c513f6
DD		 826
827 /* Opcode relocs are always big endian. Data relocs are bi-endian. */
828 switch (r_type)
829 {
830 case R_RL78_NONE:
831 break;
832
9cea966c
DD		 833 case R_RL78_RH_RELAX:
834 break;
835
99c513f6
DD		 836 case R_RL78_DIR8S_PCREL:
837 RANGE (-128, 127);
838 OP (0) = relocation;
839 break;
840
841 case R_RL78_DIR8S:
842 RANGE (-128, 255);
843 OP (0) = relocation;
844 break;
845
846 case R_RL78_DIR8U:
847 RANGE (0, 255);
848 OP (0) = relocation;
849 break;
850
851 case R_RL78_DIR16S_PCREL:
852 RANGE (-32768, 32767);
853 OP (0) = relocation;
854 OP (1) = relocation >> 8;
855 break;
856
857 case R_RL78_DIR16S:
858 if ((relocation & 0xf0000) == 0xf0000)
859 relocation &= 0xffff;
860 RANGE (-32768, 65535);
861 OP (0) = relocation;
862 OP (1) = relocation >> 8;
863 break;
864
865 case R_RL78_DIR16U:
866 RANGE (0, 65536);
867 OP (0) = relocation;
868 OP (1) = relocation >> 8;
869 break;
870
871 case R_RL78_DIR16:
872 RANGE (-32768, 65536);
873 OP (0) = relocation;
874 OP (1) = relocation >> 8;
875 break;
876
877 case R_RL78_DIR16_REV:
878 RANGE (-32768, 65536);
879 OP (1) = relocation;
880 OP (0) = relocation >> 8;
881 break;
882
883 case R_RL78_DIR3U_PCREL:
884 RANGE (3, 10);
885 OP (0) &= 0xf8;
886 OP (0) |= relocation & 0x07;
887 break;
888
889 case R_RL78_DIR24S_PCREL:
890 RANGE (-0x800000, 0x7fffff);
891 OP (0) = relocation;
892 OP (1) = relocation >> 8;
893 OP (2) = relocation >> 16;
894 break;
895
896 case R_RL78_DIR24S:
897 RANGE (-0x800000, 0x7fffff);
898 OP (0) = relocation;
899 OP (1) = relocation >> 8;
900 OP (2) = relocation >> 16;
901 break;
902
903 case R_RL78_DIR32:
904 OP (0) = relocation;
905 OP (1) = relocation >> 8;
906 OP (2) = relocation >> 16;
907 OP (3) = relocation >> 24;
908 break;
909
910 case R_RL78_DIR32_REV:
911 OP (3) = relocation;
912 OP (2) = relocation >> 8;
913 OP (1) = relocation >> 16;
914 OP (0) = relocation >> 24;
915 break;
916
9cea966c 917 case R_RL78_RH_SFR:
9cea966c
DD		 918 RANGE (0xfff00, 0xfffff);
919 OP (0) = relocation & 0xff;
920 break;
921
922 case R_RL78_RH_SADDR:
9cea966c
DD		 923 RANGE (0xffe20, 0xfff1f);
924 OP (0) = relocation & 0xff;
9cea966c
DD		 925 break;
926
99c513f6 927 /* Complex reloc handling: */
99c513f6 928 case R_RL78_ABS32:
99c513f6 929 case R_RL78_ABS32_REV:
99c513f6
DD		 930 case R_RL78_ABS24S_PCREL:
931 case R_RL78_ABS24S:
99c513f6 932 case R_RL78_ABS16:
99c513f6 933 case R_RL78_ABS16_REV:
99c513f6
DD		 934 case R_RL78_ABS16S_PCREL:
935 case R_RL78_ABS16S:
99c513f6 936 case R_RL78_ABS16U:
99c513f6 937 case R_RL78_ABS16UL:
99c513f6 938 case R_RL78_ABS16UW:
99c513f6 939 case R_RL78_ABS8:
99c513f6 940 case R_RL78_ABS8U:
99c513f6 941 case R_RL78_ABS8UL:
99c513f6 942 case R_RL78_ABS8UW:
99c513f6
DD		 943 case R_RL78_ABS8S_PCREL:
944 case R_RL78_ABS8S:
99c513f6 945 case R_RL78_OPneg:
99c513f6 946 case R_RL78_OPadd:
99c513f6 947 case R_RL78_OPsub:
99c513f6 948 case R_RL78_OPmul:
99c513f6 949 case R_RL78_OPdiv:
99c513f6 950 case R_RL78_OPshla:
99c513f6 951 case R_RL78_OPshra:
99c513f6 952 case R_RL78_OPsctsize:
99c513f6 953 case R_RL78_OPscttop:
99c513f6 954 case R_RL78_OPand:
6ff71e76
NC		 955 case R_RL78_OPor:
956 case R_RL78_OPxor:
957 case R_RL78_OPnot:
958 case R_RL78_OPmod:
959 relocation = rl78_compute_complex_reloc (r_type, 0, input_section);
99c513f6 960
6ff71e76
NC		 961 switch (r_type)
962 {
963 case R_RL78_ABS32:
964 OP (0) = relocation;
965 OP (1) = relocation >> 8;
966 OP (2) = relocation >> 16;
967 OP (3) = relocation >> 24;
968 break;
99c513f6 969
6ff71e76
NC		 970 case R_RL78_ABS32_REV:
971 OP (3) = relocation;
972 OP (2) = relocation >> 8;
973 OP (1) = relocation >> 16;
974 OP (0) = relocation >> 24;
975 break;
99c513f6 976
6ff71e76
NC		 977 case R_RL78_ABS24S_PCREL:
978 case R_RL78_ABS24S:
979 RANGE (-0x800000, 0x7fffff);
980 OP (0) = relocation;
981 OP (1) = relocation >> 8;
982 OP (2) = relocation >> 16;
983 break;
99c513f6 984
6ff71e76
NC		 985 case R_RL78_ABS16:
986 RANGE (-32768, 65535);
987 OP (0) = relocation;
988 OP (1) = relocation >> 8;
989 break;
99c513f6 990
6ff71e76
NC		 991 case R_RL78_ABS16_REV:
992 RANGE (-32768, 65535);
993 OP (1) = relocation;
994 OP (0) = relocation >> 8;
995 break;
99c513f6 996
6ff71e76
NC		 997 case R_RL78_ABS16S_PCREL:
998 case R_RL78_ABS16S:
999 RANGE (-32768, 32767);
1000 OP (0) = relocation;
1001 OP (1) = relocation >> 8;
1002 break;
99c513f6 1003
6ff71e76
NC		 1004 case R_RL78_ABS16U:
1005 case R_RL78_ABS16UL:
1006 case R_RL78_ABS16UW:
1007 RANGE (0, 65536);
1008 OP (0) = relocation;
1009 OP (1) = relocation >> 8;
1010 break;
99c513f6 1011
6ff71e76
NC		 1012 case R_RL78_ABS8:
1013 RANGE (-128, 255);
1014 OP (0) = relocation;
1015 break;
99c513f6 1016
6ff71e76
NC		 1017 case R_RL78_ABS8U:
1018 case R_RL78_ABS8UL:
1019 case R_RL78_ABS8UW:
1020 RANGE (0, 255);
1021 OP (0) = relocation;
1022 break;
1023
1024 case R_RL78_ABS8S_PCREL:
1025 case R_RL78_ABS8S:
1026 RANGE (-128, 127);
1027 OP (0) = relocation;
1028 break;
1029
1030 default:
1031 break;
1032 }
1033 break;
1b786873 1034
6ff71e76
NC		 1035 case R_RL78_SYM:
1036 if (r_symndx < symtab_hdr->sh_info)
1037 relocation = sec->output_section->vma + sec->output_offset
1038 + sym->st_value + rel->r_addend;
1039 else if (h != NULL
1040 && (h->root.type == bfd_link_hash_defined
1041 || h->root.type == bfd_link_hash_defweak))
1042 relocation = h->root.u.def.value
1043 + sec->output_section->vma
1044 + sec->output_offset
1045 + rel->r_addend;
1046 else
1047 {
1048 relocation = 0;
1049 if (h->root.type != bfd_link_hash_undefweak)
1050 _bfd_error_handler (_("Warning: RL78_SYM reloc with an unknown symbol"));
1051 }
1052 (void) rl78_compute_complex_reloc (r_type, relocation, input_section);
99c513f6
DD		 1053 break;
1054
1055 case R_RL78_OPromtop:
1a72702b 1056 relocation = get_romstart (info, input_bfd, input_section, rel->r_offset);
6ff71e76 1057 (void) rl78_compute_complex_reloc (r_type, relocation, input_section);
99c513f6
DD		 1058 break;
1059
1060 case R_RL78_OPramtop:
1a72702b 1061 relocation = get_ramstart (info, input_bfd, input_section, rel->r_offset);
6ff71e76 1062 (void) rl78_compute_complex_reloc (r_type, relocation, input_section);
99c513f6
DD		 1063 break;
1064
1065 default:
1066 r = bfd_reloc_notsupported;
1067 break;
1068 }
1069
1070 if (r != bfd_reloc_ok)
1071 {
1072 const char * msg = NULL;
1073
1074 switch (r)
1075 {
1076 case bfd_reloc_overflow:
1077 /* Catch the case of a missing function declaration
1078 and emit a more helpful error message. */
1079 if (r_type == R_RL78_DIR24S_PCREL)
695344c0 1080 /* xgettext:c-format */
871b3ab2 1081 msg = _("%pB(%pA): error: call to undefined function '%s'");
99c513f6 1082 else
1a72702b 1083 (*info->callbacks->reloc_overflow)
99c513f6
DD		 1084 (info, (h ? &h->root : NULL), name, howto->name, (bfd_vma) 0,
1085 input_bfd, input_section, rel->r_offset);
1086 break;
1087
1088 case bfd_reloc_undefined:
1a72702b
AM		 1089 (*info->callbacks->undefined_symbol)
1090 (info, name, input_bfd, input_section, rel->r_offset, TRUE);
99c513f6
DD		 1091 break;
1092
1093 case bfd_reloc_other:
695344c0 1094 /* xgettext:c-format */
871b3ab2 1095 msg = _("%pB(%pA): warning: unaligned access to symbol '%s' in the small data area");
99c513f6
DD		 1096 break;
1097
1098 case bfd_reloc_outofrange:
695344c0 1099 /* xgettext:c-format */
871b3ab2 1100 msg = _("%pB(%pA): internal error: out of range error");
99c513f6
DD		 1101 break;
1102
1103 case bfd_reloc_notsupported:
695344c0 1104 /* xgettext:c-format */
871b3ab2 1105 msg = _("%pB(%pA): internal error: unsupported relocation error");
99c513f6
DD		 1106 break;
1107
1108 case bfd_reloc_dangerous:
695344c0 1109 /* xgettext:c-format */
871b3ab2 1110 msg = _("%pB(%pA): internal error: dangerous relocation");
99c513f6
DD		 1111 break;
1112
1113 default:
695344c0 1114 /* xgettext:c-format */
871b3ab2 1115 msg = _("%pB(%pA): internal error: unknown error");
99c513f6
DD		 1116 break;
1117 }
1118
1119 if (msg)
1120 _bfd_error_handler (msg, input_bfd, input_section, name);
99c513f6
DD		 1121 }
1122 }
1123
1124 return TRUE;
1125}
1126\f
1127/* Function to set the ELF flag bits. */
1128
1129static bfd_boolean
1130rl78_elf_set_private_flags (bfd * abfd, flagword flags)
1131{
1132 elf_elfheader (abfd)->e_flags = flags;
1133 elf_flags_init (abfd) = TRUE;
1134 return TRUE;
1135}
1136
1137static bfd_boolean no_warn_mismatch = FALSE;
1138
1139void bfd_elf32_rl78_set_target_flags (bfd_boolean);
1140
1141void
1142bfd_elf32_rl78_set_target_flags (bfd_boolean user_no_warn_mismatch)
1143{
1144 no_warn_mismatch = user_no_warn_mismatch;
1145}
1146
1740ba0c
NC		 1147static const char *
1148rl78_cpu_name (flagword flags)
1149{
1150 switch (flags & E_FLAG_RL78_CPU_MASK)
1151 {
1152 default: return "";
1153 case E_FLAG_RL78_G10: return "G10";
1154 case E_FLAG_RL78_G13: return "G13";
1155 case E_FLAG_RL78_G14: return "G14";
1156 }
1157}
1158
99c513f6
DD		 1159/* Merge backend specific data from an object file to the output
1160 object file when linking. */
1161
1162static bfd_boolean
50e03d47 1163rl78_elf_merge_private_bfd_data (bfd *ibfd, struct bfd_link_info *info)
99c513f6 1164{
50e03d47 1165 bfd *obfd = info->output_bfd;
99c513f6 1166 flagword new_flags;
4046d87a 1167 flagword old_flags;
99c513f6
DD		 1168 bfd_boolean error = FALSE;
1169
1170 new_flags = elf_elfheader (ibfd)->e_flags;
4046d87a 1171 old_flags = elf_elfheader (obfd)->e_flags;
99c513f6
DD		 1172
1173 if (!elf_flags_init (obfd))
1174 {
1175 /* First call, no flags set. */
1176 elf_flags_init (obfd) = TRUE;
1177 elf_elfheader (obfd)->e_flags = new_flags;
1178 }
4046d87a
NC		 1179 else if (old_flags != new_flags)
1180 {
1181 flagword changed_flags = old_flags ^ new_flags;
1182
1740ba0c 1183 if (changed_flags & E_FLAG_RL78_CPU_MASK)
4046d87a 1184 {
1740ba0c
NC		 1185 flagword out_cpu = old_flags & E_FLAG_RL78_CPU_MASK;
1186 flagword in_cpu = new_flags & E_FLAG_RL78_CPU_MASK;
4046d87a 1187
1740ba0c
NC		 1188 if (in_cpu == E_FLAG_RL78_ANY_CPU || in_cpu == out_cpu)
1189 /* It does not matter what new_cpu may have. */;
1190 else if (out_cpu == E_FLAG_RL78_ANY_CPU)
1191 {
1192 if (in_cpu == E_FLAG_RL78_G10)
1193 {
1194 /* G10 files can only be linked with other G10 files.
1195 If the output is set to "any" this means that it is
1196 a G14 file that does not use hardware multiply/divide,
1197 but that is still incompatible with the G10 ABI. */
1198 error = TRUE;
1199
4eca0228 1200 _bfd_error_handler
695344c0 1201 /* xgettext:c-format */
871b3ab2
AM		 1202 (_("RL78 ABI conflict: G10 file %pB cannot be linked"
1203 " with %s file %pB"),
dae82561 1204 ibfd, rl78_cpu_name (out_cpu), obfd);
1740ba0c
NC		 1205 }
1206 else
1207 {
1208 old_flags &= ~ E_FLAG_RL78_CPU_MASK;
1209 old_flags |= in_cpu;
1210 elf_elfheader (obfd)->e_flags = old_flags;
1211 }
1212 }
4046d87a 1213 else
1740ba0c
NC		 1214 {
1215 error = TRUE;
1216
4eca0228 1217 _bfd_error_handler
695344c0 1218 /* xgettext:c-format */
871b3ab2 1219 (_("RL78 ABI conflict: cannot link %s file %pB with %s file %pB"),
dae82561
AM		 1220 rl78_cpu_name (in_cpu), ibfd,
1221 rl78_cpu_name (out_cpu), obfd);
1740ba0c 1222 }
4046d87a 1223 }
856ea05c
KP		 1224
1225 if (changed_flags & E_FLAG_RL78_64BIT_DOUBLES)
1226 {
4eca0228 1227 _bfd_error_handler
856ea05c
KP		 1228 (_("RL78 merge conflict: cannot link 32-bit and 64-bit objects together"));
1229
1230 if (old_flags & E_FLAG_RL78_64BIT_DOUBLES)
695344c0 1231 /* xgettext:c-format */
871b3ab2 1232 _bfd_error_handler (_("- %pB is 64-bit, %pB is not"),
dae82561 1233 obfd, ibfd);
856ea05c 1234 else
695344c0 1235 /* xgettext:c-format */
871b3ab2 1236 _bfd_error_handler (_("- %pB is 64-bit, %pB is not"),
dae82561 1237 ibfd, obfd);
1740ba0c 1238 error = TRUE;
1b786873 1239 }
4046d87a 1240 }
99c513f6
DD		 1241
1242 return !error;
1243}
1244\f
1245static bfd_boolean
1246rl78_elf_print_private_bfd_data (bfd * abfd, void * ptr)
1247{
1248 FILE * file = (FILE *) ptr;
1249 flagword flags;
1250
1251 BFD_ASSERT (abfd != NULL && ptr != NULL);
1252
1253 /* Print normal ELF private data. */
1254 _bfd_elf_print_private_bfd_data (abfd, ptr);
1255
1256 flags = elf_elfheader (abfd)->e_flags;
1257 fprintf (file, _("private flags = 0x%lx:"), (long) flags);
1258
1740ba0c
NC		 1259 if (flags & E_FLAG_RL78_CPU_MASK)
1260 fprintf (file, " [%s]", rl78_cpu_name (flags));
4046d87a 1261
856ea05c
KP		 1262 if (flags & E_FLAG_RL78_64BIT_DOUBLES)
1263 fprintf (file, _(" [64-bit doubles]"));
1264
99c513f6
DD		 1265 fputc ('\n', file);
1266 return TRUE;
1267}
1268
1269/* Return the MACH for an e_flags value. */
1270
1271static int
1740ba0c 1272elf32_rl78_machine (bfd * abfd ATTRIBUTE_UNUSED)
99c513f6 1273{
1740ba0c 1274 return bfd_mach_rl78;
99c513f6
DD		 1275}
1276
1277static bfd_boolean
1278rl78_elf_object_p (bfd * abfd)
1279{
1280 bfd_default_set_arch_mach (abfd, bfd_arch_rl78,
1281 elf32_rl78_machine (abfd));
1282 return TRUE;
1283}
99c513f6
DD		 1284\f
1285/* support PLT for 16-bit references to 24-bit functions. */
1286
1287/* We support 16-bit pointers to code above 64k by generating a thunk
1288 below 64k containing a JMP instruction to the final address. */
68ffbac6 1289
99c513f6
DD		 1290static bfd_boolean
1291rl78_elf_check_relocs
07d6d2b8 1292 (bfd * abfd,
99c513f6 1293 struct bfd_link_info * info,
07d6d2b8 1294 asection * sec,
99c513f6
DD		 1295 const Elf_Internal_Rela * relocs)
1296{
07d6d2b8 1297 Elf_Internal_Shdr * symtab_hdr;
99c513f6 1298 struct elf_link_hash_entry ** sym_hashes;
07d6d2b8
AM		 1299 const Elf_Internal_Rela * rel;
1300 const Elf_Internal_Rela * rel_end;
99c513f6
DD		 1301 bfd_vma *local_plt_offsets;
1302 asection *splt;
1303 bfd *dynobj;
1304
0e1862bb 1305 if (bfd_link_relocatable (info))
99c513f6 1306 return TRUE;
68ffbac6 1307
99c513f6
DD		 1308 symtab_hdr = &elf_tdata (abfd)->symtab_hdr;
1309 sym_hashes = elf_sym_hashes (abfd);
1310 local_plt_offsets = elf_local_got_offsets (abfd);
99c513f6
DD		 1311 dynobj = elf_hash_table(info)->dynobj;
1312
1313 rel_end = relocs + sec->reloc_count;
1314 for (rel = relocs; rel < rel_end; rel++)
1315 {
1316 struct elf_link_hash_entry *h;
1317 unsigned long r_symndx;
1318 bfd_vma *offset;
68ffbac6 1319
99c513f6
DD		 1320 r_symndx = ELF32_R_SYM (rel->r_info);
1321 if (r_symndx < symtab_hdr->sh_info)
07d6d2b8 1322 h = NULL;
99c513f6
DD		 1323 else
1324 {
1325 h = sym_hashes[r_symndx - symtab_hdr->sh_info];
1326 while (h->root.type == bfd_link_hash_indirect
1327 || h->root.type == bfd_link_hash_warning)
1328 h = (struct elf_link_hash_entry *) h->root.u.i.link;
1329 }
68ffbac6 1330
99c513f6 1331 switch (ELF32_R_TYPE (rel->r_info))
07d6d2b8 1332 {
99c513f6
DD		 1333 /* This relocation describes a 16-bit pointer to a function.
1334 We may need to allocate a thunk in low memory; reserve memory
1335 for it now. */
1336 case R_RL78_DIR16S:
1337 if (dynobj == NULL)
1338 elf_hash_table (info)->dynobj = dynobj = abfd;
ce558b89 1339 splt = elf_hash_table (info)->splt;
99c513f6
DD		 1340 if (splt == NULL)
1341 {
ce558b89
AM		 1342 flagword flags = (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS
1343 | SEC_IN_MEMORY | SEC_LINKER_CREATED
1344 | SEC_READONLY | SEC_CODE);
1345 splt = bfd_make_section_anyway_with_flags (dynobj, ".plt",
1346 flags);
1347 elf_hash_table (info)->splt = splt;
1348 if (splt == NULL
1349 || ! bfd_set_section_alignment (dynobj, splt, 1))
1350 return FALSE;
99c513f6
DD		 1351 }
1352
1353 if (h != NULL)
1354 offset = &h->plt.offset;
1355 else
1356 {
1357 if (local_plt_offsets == NULL)
1358 {
1359 size_t size;
1360 unsigned int i;
1361
1362 size = symtab_hdr->sh_info * sizeof (bfd_vma);
1363 local_plt_offsets = (bfd_vma *) bfd_alloc (abfd, size);
1364 if (local_plt_offsets == NULL)
1365 return FALSE;
1366 elf_local_got_offsets (abfd) = local_plt_offsets;
1367
1368 for (i = 0; i < symtab_hdr->sh_info; i++)
1369 local_plt_offsets[i] = (bfd_vma) -1;
1370 }
1371 offset = &local_plt_offsets[r_symndx];
1372 }
1373
1374 if (*offset == (bfd_vma) -1)
1375 {
1376 *offset = splt->size;
1377 splt->size += 4;
1378 }
1379 break;
07d6d2b8 1380 }
99c513f6 1381 }
68ffbac6 1382
99c513f6
DD		 1383 return TRUE;
1384}
1385
1386/* This must exist if dynobj is ever set. */
1387
1388static bfd_boolean
1389rl78_elf_finish_dynamic_sections (bfd *abfd ATTRIBUTE_UNUSED,
07d6d2b8 1390 struct bfd_link_info *info)
99c513f6
DD		 1391{
1392 bfd *dynobj;
1393 asection *splt;
1394
47fc0f1f
NC		 1395 if (!elf_hash_table (info)->dynamic_sections_created)
1396 return TRUE;
1397
9cea966c
DD		 1398 /* As an extra sanity check, verify that all plt entries have been
1399 filled in. However, relaxing might have changed the relocs so
1400 that some plt entries don't get filled in, so we have to skip
1401 this check if we're relaxing. Unfortunately, check_relocs is
1402 called before relaxation. */
99c513f6 1403
1740ba0c 1404 if (info->relax_trip > 0)
47fc0f1f
NC		 1405 return TRUE;
1406
ce558b89
AM		 1407 dynobj = elf_hash_table (info)->dynobj;
1408 splt = elf_hash_table (info)->splt;
1409 if (dynobj != NULL && splt != NULL)
99c513f6 1410 {
47fc0f1f
NC		 1411 bfd_byte *contents = splt->contents;
1412 unsigned int i, size = splt->size;
1413
1414 for (i = 0; i < size; i += 4)
99c513f6 1415 {
47fc0f1f
NC		 1416 unsigned int x = bfd_get_32 (dynobj, contents + i);
1417 BFD_ASSERT (x != 0);
99c513f6
DD		 1418 }
1419 }
1420
1421 return TRUE;
1422}
1423
1424static bfd_boolean
1425rl78_elf_always_size_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
07d6d2b8 1426 struct bfd_link_info *info)
99c513f6
DD		 1427{
1428 bfd *dynobj;
1429 asection *splt;
1430
0e1862bb 1431 if (bfd_link_relocatable (info))
99c513f6
DD		 1432 return TRUE;
1433
1434 dynobj = elf_hash_table (info)->dynobj;
1435 if (dynobj == NULL)
1436 return TRUE;
1437
ce558b89 1438 splt = elf_hash_table (info)->splt;
99c513f6
DD		 1439 BFD_ASSERT (splt != NULL);
1440
1441 splt->contents = (bfd_byte *) bfd_zalloc (dynobj, splt->size);
1442 if (splt->contents == NULL)
1443 return FALSE;
1444
1445 return TRUE;
1446}
1447
1448\f
1449
1450/* Handle relaxing. */
1451
1452/* A subroutine of rl78_elf_relax_section. If the global symbol H
1453 is within the low 64k, remove any entry for it in the plt. */
1454
1455struct relax_plt_data
1456{
1457 asection *splt;
1458 bfd_boolean *again;
1459};
1460
1461static bfd_boolean
2c3fc389 1462rl78_relax_plt_check (struct elf_link_hash_entry *h, void * xdata)
99c513f6
DD		 1463{
1464 struct relax_plt_data *data = (struct relax_plt_data *) xdata;
1465
1466 if (h->plt.offset != (bfd_vma) -1)
1467 {
1468 bfd_vma address;
1469
1470 if (h->root.type == bfd_link_hash_undefined
1471 || h->root.type == bfd_link_hash_undefweak)
1472 address = 0;
1473 else
1474 address = (h->root.u.def.section->output_section->vma
1475 + h->root.u.def.section->output_offset
1476 + h->root.u.def.value);
1477
1478 if (valid_16bit_address (address))
1479 {
1480 h->plt.offset = -1;
1481 data->splt->size -= 4;
1482 *data->again = TRUE;
1483 }
1484 }
1485
1486 return TRUE;
1487}
1488
1489/* A subroutine of rl78_elf_relax_section. If the global symbol H
1490 previously had a plt entry, give it a new entry offset. */
1491
1492static bfd_boolean
2c3fc389 1493rl78_relax_plt_realloc (struct elf_link_hash_entry *h, void * xdata)
99c513f6
DD		 1494{
1495 bfd_vma *entry = (bfd_vma *) xdata;
1496
1497 if (h->plt.offset != (bfd_vma) -1)
1498 {
1499 h->plt.offset = *entry;
1500 *entry += 4;
1501 }
1502
1503 return TRUE;
1504}
1505
1506static bfd_boolean
1507rl78_elf_relax_plt_section (bfd *dynobj,
07d6d2b8
AM		 1508 asection *splt,
1509 struct bfd_link_info *info,
1510 bfd_boolean *again)
99c513f6
DD		 1511{
1512 struct relax_plt_data relax_plt_data;
1513 bfd *ibfd;
1514
1515 /* Assume nothing changes. */
1516 *again = FALSE;
1517
0e1862bb 1518 if (bfd_link_relocatable (info))
99c513f6
DD		 1519 return TRUE;
1520
1521 /* We only relax the .plt section at the moment. */
1522 if (dynobj != elf_hash_table (info)->dynobj
1523 || strcmp (splt->name, ".plt") != 0)
1524 return TRUE;
1525
1526 /* Quick check for an empty plt. */
1527 if (splt->size == 0)
1528 return TRUE;
1529
1530 /* Map across all global symbols; see which ones happen to
1531 fall in the low 64k. */
1532 relax_plt_data.splt = splt;
1533 relax_plt_data.again = again;
1534 elf_link_hash_traverse (elf_hash_table (info), rl78_relax_plt_check,
1535 &relax_plt_data);
1536
1537 /* Likewise for local symbols, though that's somewhat less convenient
1538 as we have to walk the list of input bfds and swap in symbol data. */
c72f2fb2 1539 for (ibfd = info->input_bfds; ibfd ; ibfd = ibfd->link.next)
99c513f6
DD		 1540 {
1541 bfd_vma *local_plt_offsets = elf_local_got_offsets (ibfd);
1542 Elf_Internal_Shdr *symtab_hdr;
1543 Elf_Internal_Sym *isymbuf = NULL;
1544 unsigned int idx;
1545
1546 if (! local_plt_offsets)
1547 continue;
1548
1549 symtab_hdr = &elf_tdata (ibfd)->symtab_hdr;
1550 if (symtab_hdr->sh_info != 0)
1551 {
1552 isymbuf = (Elf_Internal_Sym *) symtab_hdr->contents;
1553 if (isymbuf == NULL)
1554 isymbuf = bfd_elf_get_elf_syms (ibfd, symtab_hdr,
1555 symtab_hdr->sh_info, 0,
1556 NULL, NULL, NULL);
1557 if (isymbuf == NULL)
1558 return FALSE;
1559 }
1560
1561 for (idx = 0; idx < symtab_hdr->sh_info; ++idx)
1562 {
1563 Elf_Internal_Sym *isym;
1564 asection *tsec;
1565 bfd_vma address;
1566
1567 if (local_plt_offsets[idx] == (bfd_vma) -1)
1568 continue;
1569
1570 isym = &isymbuf[idx];
1571 if (isym->st_shndx == SHN_UNDEF)
1572 continue;
1573 else if (isym->st_shndx == SHN_ABS)
1574 tsec = bfd_abs_section_ptr;
1575 else if (isym->st_shndx == SHN_COMMON)
1576 tsec = bfd_com_section_ptr;
1577 else
1578 tsec = bfd_section_from_elf_index (ibfd, isym->st_shndx);
1579
1580 address = (tsec->output_section->vma
1581 + tsec->output_offset
1582 + isym->st_value);
1583 if (valid_16bit_address (address))
1584 {
1585 local_plt_offsets[idx] = -1;
1586 splt->size -= 4;
1587 *again = TRUE;
1588 }
1589 }
1590
1591 if (isymbuf != NULL
1592 && symtab_hdr->contents != (unsigned char *) isymbuf)
1593 {
1594 if (! info->keep_memory)
1595 free (isymbuf);
1596 else
1597 {
1598 /* Cache the symbols for elf_link_input_bfd. */
1599 symtab_hdr->contents = (unsigned char *) isymbuf;
1600 }
1601 }
1602 }
1603
1604 /* If we changed anything, walk the symbols again to reallocate
1605 .plt entry addresses. */
1606 if (*again && splt->size > 0)
1607 {
1608 bfd_vma entry = 0;
1609
1610 elf_link_hash_traverse (elf_hash_table (info),
1611 rl78_relax_plt_realloc, &entry);
1612
c72f2fb2 1613 for (ibfd = info->input_bfds; ibfd ; ibfd = ibfd->link.next)
99c513f6
DD		 1614 {
1615 bfd_vma *local_plt_offsets = elf_local_got_offsets (ibfd);
1616 unsigned int nlocals = elf_tdata (ibfd)->symtab_hdr.sh_info;
1617 unsigned int idx;
1618
1619 if (! local_plt_offsets)
1620 continue;
1621
1622 for (idx = 0; idx < nlocals; ++idx)
1623 if (local_plt_offsets[idx] != (bfd_vma) -1)
1624 {
07d6d2b8 1625 local_plt_offsets[idx] = entry;
99c513f6
DD		 1626 entry += 4;
1627 }
1628 }
1629 }
1630
1631 return TRUE;
1632}
1633
9cea966c
DD		 1634/* Delete some bytes from a section while relaxing. */
1635
1636static bfd_boolean
1637elf32_rl78_relax_delete_bytes (bfd *abfd, asection *sec, bfd_vma addr, int count,
1740ba0c 1638 Elf_Internal_Rela *alignment_rel, int force_snip)
9cea966c
DD		 1639{
1640 Elf_Internal_Shdr * symtab_hdr;
07d6d2b8
AM		 1641 unsigned int sec_shndx;
1642 bfd_byte * contents;
9cea966c
DD		 1643 Elf_Internal_Rela * irel;
1644 Elf_Internal_Rela * irelend;
1645 Elf_Internal_Sym * isym;
1646 Elf_Internal_Sym * isymend;
07d6d2b8
AM		 1647 bfd_vma toaddr;
1648 unsigned int symcount;
9cea966c
DD		 1649 struct elf_link_hash_entry ** sym_hashes;
1650 struct elf_link_hash_entry ** end_hashes;
1651
1652 if (!alignment_rel)
1653 force_snip = 1;
1654
1655 sec_shndx = _bfd_elf_section_from_bfd_section (abfd, sec);
1656
1657 contents = elf_section_data (sec)->this_hdr.contents;
1658
1659 /* The deletion must stop at the next alignment boundary, if
1660 ALIGNMENT_REL is non-NULL. */
1661 toaddr = sec->size;
1662 if (alignment_rel)
1663 toaddr = alignment_rel->r_offset;
1664
1665 irel = elf_section_data (sec)->relocs;
2bc56d66
DD		 1666 if (irel == NULL)
1667 {
1668 _bfd_elf_link_read_relocs (sec->owner, sec, NULL, NULL, TRUE);
1669 irel = elf_section_data (sec)->relocs;
1670 }
1671
9cea966c
DD		 1672 irelend = irel + sec->reloc_count;
1673
1674 /* Actually delete the bytes. */
1675 memmove (contents + addr, contents + addr + count,
1676 (size_t) (toaddr - addr - count));
1677
1678 /* If we don't have an alignment marker to worry about, we can just
1679 shrink the section. Otherwise, we have to fill in the newly
1680 created gap with NOP insns (0x03). */
1681 if (force_snip)
1682 sec->size -= count;
1683 else
1684 memset (contents + toaddr - count, 0x03, count);
1685
1686 /* Adjust all the relocs. */
2bc56d66 1687 for (; irel && irel < irelend; irel++)
9cea966c
DD		 1688 {
1689 /* Get the new reloc address. */
1690 if (irel->r_offset > addr
1691 && (irel->r_offset < toaddr
1692 || (force_snip && irel->r_offset == toaddr)))
1693 irel->r_offset -= count;
1694
1695 /* If we see an ALIGN marker at the end of the gap, we move it
1696 to the beginning of the gap, since marking these gaps is what
1697 they're for. */
1698 if (irel->r_offset == toaddr
1699 && ELF32_R_TYPE (irel->r_info) == R_RL78_RH_RELAX
1700 && irel->r_addend & RL78_RELAXA_ALIGN)
1701 irel->r_offset -= count;
1702 }
1703
1704 /* Adjust the local symbols defined in this section. */
1705 symtab_hdr = &elf_tdata (abfd)->symtab_hdr;
1706 isym = (Elf_Internal_Sym *) symtab_hdr->contents;
1707 isymend = isym + symtab_hdr->sh_info;
1708
1709 for (; isym < isymend; isym++)
1710 {
1711 /* If the symbol is in the range of memory we just moved, we
1712 have to adjust its value. */
1713 if (isym->st_shndx == sec_shndx
1714 && isym->st_value > addr
1715 && isym->st_value < toaddr)
1716 isym->st_value -= count;
1717
1718 /* If the symbol *spans* the bytes we just deleted (i.e. it's
1719 *end* is in the moved bytes but it's *start* isn't), then we
1720 must adjust its size. */
1721 if (isym->st_shndx == sec_shndx
1722 && isym->st_value < addr
1723 && isym->st_value + isym->st_size > addr
1724 && isym->st_value + isym->st_size < toaddr)
1725 isym->st_size -= count;
1726 }
1727
1728 /* Now adjust the global symbols defined in this section. */
1729 symcount = (symtab_hdr->sh_size / sizeof (Elf32_External_Sym)
1730 - symtab_hdr->sh_info);
1731 sym_hashes = elf_sym_hashes (abfd);
1732 end_hashes = sym_hashes + symcount;
1733
1734 for (; sym_hashes < end_hashes; sym_hashes++)
1735 {
1736 struct elf_link_hash_entry *sym_hash = *sym_hashes;
1737
1738 if ((sym_hash->root.type == bfd_link_hash_defined
1739 || sym_hash->root.type == bfd_link_hash_defweak)
1740 && sym_hash->root.u.def.section == sec)
1741 {
1742 /* As above, adjust the value if needed. */
1743 if (sym_hash->root.u.def.value > addr
1744 && sym_hash->root.u.def.value < toaddr)
1745 sym_hash->root.u.def.value -= count;
1746
1747 /* As above, adjust the size if needed. */
1748 if (sym_hash->root.u.def.value < addr
1749 && sym_hash->root.u.def.value + sym_hash->size > addr
1750 && sym_hash->root.u.def.value + sym_hash->size < toaddr)
1751 sym_hash->size -= count;
1752 }
1753 }
1754
1755 return TRUE;
1756}
1757
1758/* Used to sort relocs by address. If relocs have the same address,
1759 we maintain their relative order, except that R_RL78_RH_RELAX
1760 alignment relocs must be the first reloc for any given address. */
1761
1762static void
1763reloc_bubblesort (Elf_Internal_Rela * r, int count)
1764{
1765 int i;
1766 bfd_boolean again;
1767 bfd_boolean swappit;
1768
1769 /* This is almost a classic bubblesort. It's the slowest sort, but
1770 we're taking advantage of the fact that the relocations are
1771 mostly in order already (the assembler emits them that way) and
1772 we need relocs with the same address to remain in the same
1773 relative order. */
1774 again = TRUE;
1775 while (again)
1776 {
1777 again = FALSE;
1778 for (i = 0; i < count - 1; i ++)
1779 {
1780 if (r[i].r_offset > r[i + 1].r_offset)
1781 swappit = TRUE;
1782 else if (r[i].r_offset < r[i + 1].r_offset)
1783 swappit = FALSE;
1784 else if (ELF32_R_TYPE (r[i + 1].r_info) == R_RL78_RH_RELAX
1785 && (r[i + 1].r_addend & RL78_RELAXA_ALIGN))
1786 swappit = TRUE;
1787 else if (ELF32_R_TYPE (r[i + 1].r_info) == R_RL78_RH_RELAX
1788 && (r[i + 1].r_addend & RL78_RELAXA_ELIGN)
1789 && !(ELF32_R_TYPE (r[i].r_info) == R_RL78_RH_RELAX
1790 && (r[i].r_addend & RL78_RELAXA_ALIGN)))
1791 swappit = TRUE;
1792 else
1793 swappit = FALSE;
1794
1795 if (swappit)
1796 {
1797 Elf_Internal_Rela tmp;
1798
1799 tmp = r[i];
1800 r[i] = r[i + 1];
1801 r[i + 1] = tmp;
1802 /* If we do move a reloc back, re-scan to see if it
1803 needs to be moved even further back. This avoids
1804 most of the O(n^2) behavior for our cases. */
1805 if (i > 0)
1806 i -= 2;
1807 again = TRUE;
1808 }
1809 }
1810 }
1811}
1812
1813
1814#define OFFSET_FOR_RELOC(rel, lrel, scale) \
1815 rl78_offset_for_reloc (abfd, rel + 1, symtab_hdr, shndx_buf, intsyms, \
6ff71e76 1816 lrel, abfd, sec, link_info, scale)
9cea966c
DD		 1817
1818static bfd_vma
07d6d2b8
AM		 1819rl78_offset_for_reloc (bfd * abfd,
1820 Elf_Internal_Rela * rel,
1821 Elf_Internal_Shdr * symtab_hdr,
6ff71e76 1822 Elf_External_Sym_Shndx * shndx_buf ATTRIBUTE_UNUSED,
07d6d2b8
AM		 1823 Elf_Internal_Sym * intsyms,
1824 Elf_Internal_Rela ** lrel,
1825 bfd * input_bfd,
1826 asection * input_section,
1827 struct bfd_link_info * info,
1828 int * scale)
9cea966c
DD		 1829{
1830 bfd_vma symval;
9cea966c
DD		 1831
1832 *scale = 1;
1833
1834 /* REL is the first of 1..N relocations. We compute the symbol
1835 value for each relocation, then combine them if needed. LREL
1836 gets a pointer to the last relocation used. */
1837 while (1)
1838 {
6ff71e76 1839 unsigned long r_type;
9cea966c
DD		 1840
1841 /* Get the value of the symbol referred to by the reloc. */
1842 if (ELF32_R_SYM (rel->r_info) < symtab_hdr->sh_info)
1843 {
1844 /* A local symbol. */
1845 Elf_Internal_Sym *isym;
1846 asection *ssec;
1847
1848 isym = intsyms + ELF32_R_SYM (rel->r_info);
1849
1850 if (isym->st_shndx == SHN_UNDEF)
1851 ssec = bfd_und_section_ptr;
1852 else if (isym->st_shndx == SHN_ABS)
1853 ssec = bfd_abs_section_ptr;
1854 else if (isym->st_shndx == SHN_COMMON)
1855 ssec = bfd_com_section_ptr;
1856 else
1857 ssec = bfd_section_from_elf_index (abfd,
1858 isym->st_shndx);
1859
1860 /* Initial symbol value. */
1861 symval = isym->st_value;
1862
1863 /* GAS may have made this symbol relative to a section, in
1864 which case, we have to add the addend to find the
1865 symbol. */
1866 if (ELF_ST_TYPE (isym->st_info) == STT_SECTION)
1867 symval += rel->r_addend;
1868
1869 if (ssec)
1870 {
1871 if ((ssec->flags & SEC_MERGE)
dbaa2011 1872 && ssec->sec_info_type == SEC_INFO_TYPE_MERGE)
9cea966c
DD		 1873 symval = _bfd_merged_section_offset (abfd, & ssec,
1874 elf_section_data (ssec)->sec_info,
1875 symval);
1876 }
1877
1878 /* Now make the offset relative to where the linker is putting it. */
1879 if (ssec)
1880 symval +=
1881 ssec->output_section->vma + ssec->output_offset;
1882
1883 symval += rel->r_addend;
1884 }
1885 else
1886 {
1887 unsigned long indx;
1888 struct elf_link_hash_entry * h;
1889
1890 /* An external symbol. */
1891 indx = ELF32_R_SYM (rel->r_info) - symtab_hdr->sh_info;
1892 h = elf_sym_hashes (abfd)[indx];
1893 BFD_ASSERT (h != NULL);
1894
1895 if (h->root.type != bfd_link_hash_defined
1896 && h->root.type != bfd_link_hash_defweak)
1897 {
1898 /* This appears to be a reference to an undefined
1899 symbol. Just ignore it--it will be caught by the
1900 regular reloc processing. */
1901 if (lrel)
1902 *lrel = rel;
1903 return 0;
1904 }
1905
1906 symval = (h->root.u.def.value
1907 + h->root.u.def.section->output_section->vma
1908 + h->root.u.def.section->output_offset);
1909
1910 symval += rel->r_addend;
1911 }
1912
6ff71e76
NC		 1913 r_type = ELF32_R_TYPE (rel->r_info);
1914 switch (r_type)
9cea966c
DD		 1915 {
1916 case R_RL78_SYM:
6ff71e76 1917 (void) rl78_compute_complex_reloc (r_type, symval, input_section);
9cea966c
DD		 1918 break;
1919
6ff71e76 1920 case R_RL78_OPromtop:
1a72702b 1921 symval = get_romstart (info, input_bfd, input_section, rel->r_offset);
6ff71e76 1922 (void) rl78_compute_complex_reloc (r_type, symval, input_section);
9cea966c
DD		 1923 break;
1924
6ff71e76 1925 case R_RL78_OPramtop:
1a72702b 1926 symval = get_ramstart (info, input_bfd, input_section, rel->r_offset);
6ff71e76 1927 (void) rl78_compute_complex_reloc (r_type, symval, input_section);
9cea966c
DD		 1928 break;
1929
6ff71e76
NC		 1930 case R_RL78_OPneg:
1931 case R_RL78_OPadd:
9cea966c 1932 case R_RL78_OPsub:
9cea966c 1933 case R_RL78_OPmul:
9cea966c 1934 case R_RL78_OPdiv:
9cea966c 1935 case R_RL78_OPshla:
9cea966c 1936 case R_RL78_OPshra:
9cea966c 1937 case R_RL78_OPsctsize:
9cea966c 1938 case R_RL78_OPscttop:
9cea966c 1939 case R_RL78_OPand:
9cea966c 1940 case R_RL78_OPor:
9cea966c 1941 case R_RL78_OPxor:
9cea966c 1942 case R_RL78_OPnot:
9cea966c 1943 case R_RL78_OPmod:
6ff71e76 1944 (void) rl78_compute_complex_reloc (r_type, 0, input_section);
9cea966c
DD		 1945 break;
1946
1947 case R_RL78_DIR16UL:
1948 case R_RL78_DIR8UL:
1949 case R_RL78_ABS16UL:
1950 case R_RL78_ABS8UL:
9cea966c 1951 *scale = 4;
6ff71e76 1952 goto reloc_computes_value;
9cea966c
DD		 1953
1954 case R_RL78_DIR16UW:
1955 case R_RL78_DIR8UW:
1956 case R_RL78_ABS16UW:
1957 case R_RL78_ABS8UW:
9cea966c 1958 *scale = 2;
6ff71e76 1959 goto reloc_computes_value;
1b786873 1960
9cea966c 1961 default:
6ff71e76 1962 reloc_computes_value:
e896287c 1963 symval = rl78_compute_complex_reloc (r_type, symval, input_section);
1a0670f3 1964 /* Fall through. */
e896287c
DD		 1965 case R_RL78_DIR32:
1966 case R_RL78_DIR24S:
1967 case R_RL78_DIR16:
1968 case R_RL78_DIR16U:
1969 case R_RL78_DIR16S:
1970 case R_RL78_DIR24S_PCREL:
1971 case R_RL78_DIR16S_PCREL:
1972 case R_RL78_DIR8S_PCREL:
9cea966c
DD		 1973 if (lrel)
1974 *lrel = rel;
1975 return symval;
1976 }
1977
1978 rel ++;
1979 }
1980}
1981
1982struct {
1983 int prefix; /* or -1 for "no prefix" */
1984 int insn; /* or -1 for "end of list" */
1985 int insn_for_saddr; /* or -1 for "no alternative" */
1986 int insn_for_sfr; /* or -1 for "no alternative" */
1987} relax_addr16[] = {
1988 { -1, 0x02, 0x06, -1 }, /* ADDW AX, !addr16 */
1989 { -1, 0x22, 0x26, -1 }, /* SUBW AX, !addr16 */
1990 { -1, 0x42, 0x46, -1 }, /* CMPW AX, !addr16 */
1991 { -1, 0x40, 0x4a, -1 }, /* CMP !addr16, #byte */
1992
1993 { -1, 0x0f, 0x0b, -1 }, /* ADD A, !addr16 */
1994 { -1, 0x1f, 0x1b, -1 }, /* ADDC A, !addr16 */
1995 { -1, 0x2f, 0x2b, -1 }, /* SUB A, !addr16 */
1996 { -1, 0x3f, 0x3b, -1 }, /* SUBC A, !addr16 */
1997 { -1, 0x4f, 0x4b, -1 }, /* CMP A, !addr16 */
1998 { -1, 0x5f, 0x5b, -1 }, /* AND A, !addr16 */
1999 { -1, 0x6f, 0x6b, -1 }, /* OR A, !addr16 */
2000 { -1, 0x7f, 0x7b, -1 }, /* XOR A, !addr16 */
2001
2002 { -1, 0x8f, 0x8d, 0x8e }, /* MOV A, !addr16 */
2003 { -1, 0x9f, 0x9d, 0x9e }, /* MOV !addr16, A */
2004 { -1, 0xaf, 0xad, 0xae }, /* MOVW AX, !addr16 */
2005 { -1, 0xbf, 0xbd, 0xbe }, /* MOVW !addr16, AX */
2006 { -1, 0xcf, 0xcd, 0xce }, /* MOVW !addr16, #word */
2007
2008 { -1, 0xa0, 0xa4, -1 }, /* INC !addr16 */
2009 { -1, 0xa2, 0xa6, -1 }, /* INCW !addr16 */
2010 { -1, 0xb0, 0xb4, -1 }, /* DEC !addr16 */
2011 { -1, 0xb2, 0xb6, -1 }, /* DECW !addr16 */
2012
2013 { -1, 0xd5, 0xd4, -1 }, /* CMP0 !addr16 */
2014 { -1, 0xe5, 0xe4, -1 }, /* ONEB !addr16 */
2015 { -1, 0xf5, 0xf4, -1 }, /* CLRB !addr16 */
2016
2017 { -1, 0xd9, 0xd8, -1 }, /* MOV X, !addr16 */
2018 { -1, 0xe9, 0xe8, -1 }, /* MOV B, !addr16 */
2019 { -1, 0xf9, 0xf8, -1 }, /* MOV C, !addr16 */
2020 { -1, 0xdb, 0xda, -1 }, /* MOVW BC, !addr16 */
2021 { -1, 0xeb, 0xea, -1 }, /* MOVW DE, !addr16 */
2022 { -1, 0xfb, 0xfa, -1 }, /* MOVW HL, !addr16 */
2023
2024 { 0x61, 0xaa, 0xa8, -1 }, /* XCH A, !addr16 */
2025
2026 { 0x71, 0x00, 0x02, 0x0a }, /* SET1 !addr16.0 */
2027 { 0x71, 0x10, 0x12, 0x1a }, /* SET1 !addr16.0 */
2028 { 0x71, 0x20, 0x22, 0x2a }, /* SET1 !addr16.0 */
2029 { 0x71, 0x30, 0x32, 0x3a }, /* SET1 !addr16.0 */
2030 { 0x71, 0x40, 0x42, 0x4a }, /* SET1 !addr16.0 */
2031 { 0x71, 0x50, 0x52, 0x5a }, /* SET1 !addr16.0 */
2032 { 0x71, 0x60, 0x62, 0x6a }, /* SET1 !addr16.0 */
2033 { 0x71, 0x70, 0x72, 0x7a }, /* SET1 !addr16.0 */
2034
2035 { 0x71, 0x08, 0x03, 0x0b }, /* CLR1 !addr16.0 */
2036 { 0x71, 0x18, 0x13, 0x1b }, /* CLR1 !addr16.0 */
2037 { 0x71, 0x28, 0x23, 0x2b }, /* CLR1 !addr16.0 */
2038 { 0x71, 0x38, 0x33, 0x3b }, /* CLR1 !addr16.0 */
2039 { 0x71, 0x48, 0x43, 0x4b }, /* CLR1 !addr16.0 */
2040 { 0x71, 0x58, 0x53, 0x5b }, /* CLR1 !addr16.0 */
2041 { 0x71, 0x68, 0x63, 0x6b }, /* CLR1 !addr16.0 */
2042 { 0x71, 0x78, 0x73, 0x7b }, /* CLR1 !addr16.0 */
68ffbac6 2043
9cea966c
DD		 2044 { -1, -1, -1, -1 }
2045};
2046
2047/* Relax one section. */
2048
99c513f6
DD		 2049static bfd_boolean
2050rl78_elf_relax_section
07d6d2b8
AM		 2051 (bfd * abfd,
2052 asection * sec,
99c513f6 2053 struct bfd_link_info * link_info,
07d6d2b8 2054 bfd_boolean * again)
99c513f6 2055{
9cea966c
DD		 2056 Elf_Internal_Shdr * symtab_hdr;
2057 Elf_Internal_Shdr * shndx_hdr;
2058 Elf_Internal_Rela * internal_relocs;
2059 Elf_Internal_Rela * free_relocs = NULL;
2060 Elf_Internal_Rela * irel;
2061 Elf_Internal_Rela * srel;
2062 Elf_Internal_Rela * irelend;
2063 Elf_Internal_Rela * next_alignment;
07d6d2b8
AM		 2064 bfd_byte * contents = NULL;
2065 bfd_byte * free_contents = NULL;
9cea966c
DD		 2066 Elf_Internal_Sym * intsyms = NULL;
2067 Elf_Internal_Sym * free_intsyms = NULL;
2068 Elf_External_Sym_Shndx * shndx_buf = NULL;
2069 bfd_vma pc;
9cea966c
DD		 2070 bfd_vma symval ATTRIBUTE_UNUSED = 0;
2071 int pcrel ATTRIBUTE_UNUSED = 0;
2072 int code ATTRIBUTE_UNUSED = 0;
2073 int section_alignment_glue;
2074 int scale;
2075
99c513f6
DD		 2076 if (abfd == elf_hash_table (link_info)->dynobj
2077 && strcmp (sec->name, ".plt") == 0)
2078 return rl78_elf_relax_plt_section (abfd, sec, link_info, again);
2079
2080 /* Assume nothing changes. */
2081 *again = FALSE;
9cea966c
DD		 2082
2083 /* We don't have to do anything for a relocatable link, if
2084 this section does not have relocs, or if this is not a
2085 code section. */
0e1862bb 2086 if (bfd_link_relocatable (link_info)
9cea966c
DD		 2087 || (sec->flags & SEC_RELOC) == 0
2088 || sec->reloc_count == 0
2089 || (sec->flags & SEC_CODE) == 0)
2090 return TRUE;
2091
6a40cf0c
NC		 2092 symtab_hdr = & elf_symtab_hdr (abfd);
2093 if (elf_symtab_shndx_list (abfd))
2094 shndx_hdr = & elf_symtab_shndx_list (abfd)->hdr;
2095 else
2096 shndx_hdr = NULL;
9cea966c 2097
9cea966c
DD		 2098 /* Get the section contents. */
2099 if (elf_section_data (sec)->this_hdr.contents != NULL)
2100 contents = elf_section_data (sec)->this_hdr.contents;
2101 /* Go get them off disk. */
2102 else
2103 {
2104 if (! bfd_malloc_and_get_section (abfd, sec, &contents))
2105 goto error_return;
2106 elf_section_data (sec)->this_hdr.contents = contents;
2107 }
2108
2109 /* Read this BFD's symbols. */
2110 /* Get cached copy if it exists. */
2111 if (symtab_hdr->contents != NULL)
2112 intsyms = (Elf_Internal_Sym *) symtab_hdr->contents;
2113 else
2114 {
2115 intsyms = bfd_elf_get_elf_syms (abfd, symtab_hdr, symtab_hdr->sh_info, 0, NULL, NULL, NULL);
2116 symtab_hdr->contents = (bfd_byte *) intsyms;
2117 }
2118
6a40cf0c 2119 if (shndx_hdr && shndx_hdr->sh_size != 0)
9cea966c
DD		 2120 {
2121 bfd_size_type amt;
2122
2123 amt = symtab_hdr->sh_info;
2124 amt *= sizeof (Elf_External_Sym_Shndx);
2125 shndx_buf = (Elf_External_Sym_Shndx *) bfd_malloc (amt);
2126 if (shndx_buf == NULL)
2127 goto error_return;
2128 if (bfd_seek (abfd, shndx_hdr->sh_offset, SEEK_SET) != 0
2c3fc389 2129 || bfd_bread (shndx_buf, amt, abfd) != amt)
9cea966c
DD		 2130 goto error_return;
2131 shndx_hdr->contents = (bfd_byte *) shndx_buf;
2132 }
2133
2134 /* Get a copy of the native relocations. */
2135 internal_relocs = (_bfd_elf_link_read_relocs
2c3fc389 2136 (abfd, sec, NULL, (Elf_Internal_Rela *) NULL,
9cea966c
DD		 2137 link_info->keep_memory));
2138 if (internal_relocs == NULL)
2139 goto error_return;
2140 if (! link_info->keep_memory)
2141 free_relocs = internal_relocs;
2142
2143 /* The RL_ relocs must be just before the operand relocs they go
2144 with, so we must sort them to guarantee this. We use bubblesort
2145 instead of qsort so we can guarantee that relocs with the same
2146 address remain in the same relative order. */
2147 reloc_bubblesort (internal_relocs, sec->reloc_count);
2148
2149 /* Walk through them looking for relaxing opportunities. */
2150 irelend = internal_relocs + sec->reloc_count;
2151
2152
2153 /* This will either be NULL or a pointer to the next alignment
2154 relocation. */
2155 next_alignment = internal_relocs;
9cea966c
DD		 2156
2157 /* We calculate worst case shrinkage caused by alignment directives.
2158 No fool-proof, but better than either ignoring the problem or
2159 doing heavy duty analysis of all the alignment markers in all
2160 input sections. */
2161 section_alignment_glue = 0;
2162 for (irel = internal_relocs; irel < irelend; irel++)
2163 if (ELF32_R_TYPE (irel->r_info) == R_RL78_RH_RELAX
2164 && irel->r_addend & RL78_RELAXA_ALIGN)
2165 {
2166 int this_glue = 1 << (irel->r_addend & RL78_RELAXA_ANUM);
2167
2168 if (section_alignment_glue < this_glue)
2169 section_alignment_glue = this_glue;
2170 }
2171 /* Worst case is all 0..N alignments, in order, causing 2*N-1 byte
2172 shrinkage. */
2173 section_alignment_glue *= 2;
2174
2175 for (irel = internal_relocs; irel < irelend; irel++)
2176 {
2177 unsigned char *insn;
2178 int nrelocs;
2179
2180 /* The insns we care about are all marked with one of these. */
2181 if (ELF32_R_TYPE (irel->r_info) != R_RL78_RH_RELAX)
2182 continue;
2183
2184 if (irel->r_addend & RL78_RELAXA_ALIGN
2185 || next_alignment == internal_relocs)
2186 {
2187 /* When we delete bytes, we need to maintain all the alignments
2188 indicated. In addition, we need to be careful about relaxing
2189 jumps across alignment boundaries - these displacements
2190 *grow* when we delete bytes. For now, don't shrink
2191 displacements across an alignment boundary, just in case.
2192 Note that this only affects relocations to the same
2193 section. */
9cea966c
DD		 2194 next_alignment += 2;
2195 while (next_alignment < irelend
2196 && (ELF32_R_TYPE (next_alignment->r_info) != R_RL78_RH_RELAX
2197 || !(next_alignment->r_addend & RL78_RELAXA_ELIGN)))
2198 next_alignment ++;
2199 if (next_alignment >= irelend || next_alignment->r_offset == 0)
2200 next_alignment = NULL;
2201 }
2202
2203 /* When we hit alignment markers, see if we've shrunk enough
2204 before them to reduce the gap without violating the alignment
2205 requirements. */
2206 if (irel->r_addend & RL78_RELAXA_ALIGN)
2207 {
2208 /* At this point, the next relocation *should* be the ELIGN
2209 end marker. */
2210 Elf_Internal_Rela *erel = irel + 1;
2211 unsigned int alignment, nbytes;
2212
2213 if (ELF32_R_TYPE (erel->r_info) != R_RL78_RH_RELAX)
2214 continue;
2215 if (!(erel->r_addend & RL78_RELAXA_ELIGN))
2216 continue;
2217
2218 alignment = 1 << (irel->r_addend & RL78_RELAXA_ANUM);
2219
2220 if (erel->r_offset - irel->r_offset < alignment)
2221 continue;
2222
2223 nbytes = erel->r_offset - irel->r_offset;
2224 nbytes /= alignment;
2225 nbytes *= alignment;
2226
1740ba0c
NC		 2227 elf32_rl78_relax_delete_bytes (abfd, sec, erel->r_offset - nbytes, nbytes,
2228 next_alignment, erel->r_offset == sec->size);
9cea966c
DD		 2229 *again = TRUE;
2230
2231 continue;
2232 }
2233
2234 if (irel->r_addend & RL78_RELAXA_ELIGN)
2235 continue;
2236
2237 insn = contents + irel->r_offset;
2238
2239 nrelocs = irel->r_addend & RL78_RELAXA_RNUM;
2240
2241 /* At this point, we have an insn that is a candidate for linker
2242 relaxation. There are NRELOCS relocs following that may be
2243 relaxed, although each reloc may be made of more than one
2244 reloc entry (such as gp-rel symbols). */
2245
2246 /* Get the value of the symbol referred to by the reloc. Just
07d6d2b8
AM		 2247 in case this is the last reloc in the list, use the RL's
2248 addend to choose between this reloc (no addend) or the next
2249 (yes addend, which means at least one following reloc). */
9cea966c
DD		 2250
2251 /* srel points to the "current" reloction for this insn -
2252 actually the last reloc for a given operand, which is the one
2253 we need to update. We check the relaxations in the same
2254 order that the relocations happen, so we'll just push it
2255 along as we go. */
2256 srel = irel;
2257
2258 pc = sec->output_section->vma + sec->output_offset
2259 + srel->r_offset;
2260
1740ba0c
NC		 2261#define GET_RELOC \
2262 BFD_ASSERT (nrelocs > 0); \
2263 symval = OFFSET_FOR_RELOC (srel, &srel, &scale); \
2264 pcrel = symval - pc + srel->r_addend; \
9cea966c
DD		 2265 nrelocs --;
2266
2267#define SNIPNR(offset, nbytes) \
2268 elf32_rl78_relax_delete_bytes (abfd, sec, (insn - contents) + offset, nbytes, next_alignment, 0);
1740ba0c
NC		 2269
2270#define SNIP(offset, nbytes, newtype) \
07d6d2b8 2271 SNIPNR (offset, nbytes); \
9cea966c
DD		 2272 srel->r_info = ELF32_R_INFO (ELF32_R_SYM (srel->r_info), newtype)
2273
2274 /* The order of these bit tests must match the order that the
2275 relocs appear in. Since we sorted those by offset, we can
2276 predict them. */
2277
2278 /*----------------------------------------------------------------------*/
2279 /* EF ad BR $rel8 pcrel
2280 ED al ah BR !abs16 abs
2281 EE al ah BR $!rel16 pcrel
2282 EC al ah as BR !!abs20 abs
2283
2284 FD al ah CALL !abs16 abs
2285 FE al ah CALL $!rel16 pcrel
2286 FC al ah as CALL !!abs20 abs
2287
2288 DC ad BC $rel8
2289 DE ad BNC $rel8
2290 DD ad BZ $rel8
2291 DF ad BNZ $rel8
2292 61 C3 ad BH $rel8
2293 61 D3 ad BNH $rel8
2294 61 C8 EF ad SKC ; BR $rel8
2295 61 D8 EF ad SKNC ; BR $rel8
2296 61 E8 EF ad SKZ ; BR $rel8
2297 61 F8 EF ad SKNZ ; BR $rel8
2298 61 E3 EF ad SKH ; BR $rel8
2299 61 F3 EF ad SKNH ; BR $rel8
2300 */
2301
32e79d39 2302 if ((irel->r_addend & RL78_RELAXA_MASK) == RL78_RELAXA_BRA)
9cea966c 2303 {
1122dc88
DD		 2304 /* SKIP opcodes that skip non-branches will have a relax tag
2305 but no corresponding symbol to relax against; we just
2306 skip those. */
2307 if (irel->r_addend & RL78_RELAXA_RNUM)
2308 {
2309 GET_RELOC;
2310 }
9cea966c
DD		 2311
2312 switch (insn[0])
2313 {
e896287c
DD		 2314 case 0xdc: /* BC */
2315 case 0xdd: /* BZ */
2316 case 0xde: /* BNC */
2317 case 0xdf: /* BNZ */
2318 if (insn[1] == 0x03 && insn[2] == 0xee /* BR */
2319 && (srel->r_offset - irel->r_offset) > 1) /* a B<c> without its own reloc */
2320 {
2321 /* This is a "long" conditional as generated by gas:
2322 DC 03 EE ad.dr */
2323 if (pcrel < 127
2324 && pcrel > -127)
2325 {
2326 insn[0] ^= 0x02; /* invert conditional */
2327 SNIPNR (4, 1);
2328 SNIP (1, 2, R_RL78_DIR8S_PCREL);
2329 insn[1] = pcrel;
2330 *again = TRUE;
2331 }
2332 }
2333 break;
2334
9cea966c
DD		 2335 case 0xec: /* BR !!abs20 */
2336
2337 if (pcrel < 127
2338 && pcrel > -127)
2339 {
2340 insn[0] = 0xef;
2341 insn[1] = pcrel;
2342 SNIP (2, 2, R_RL78_DIR8S_PCREL);
2343 *again = TRUE;
2344 }
2345 else if (symval < 65536)
2346 {
2347 insn[0] = 0xed;
2348 insn[1] = symval & 0xff;
2349 insn[2] = symval >> 8;
e896287c 2350 SNIP (2, 1, R_RL78_DIR16U);
9cea966c
DD		 2351 *again = TRUE;
2352 }
2353 else if (pcrel < 32767
2354 && pcrel > -32767)
2355 {
2356 insn[0] = 0xee;
2357 insn[1] = pcrel & 0xff;
2358 insn[2] = pcrel >> 8;
2359 SNIP (2, 1, R_RL78_DIR16S_PCREL);
2360 *again = TRUE;
2361 }
2362 break;
2363
2364 case 0xee: /* BR $!pcrel16 */
2365 case 0xed: /* BR $!abs16 */
2366 if (pcrel < 127
2367 && pcrel > -127)
2368 {
2369 insn[0] = 0xef;
2370 insn[1] = pcrel;
2371 SNIP (2, 1, R_RL78_DIR8S_PCREL);
2372 *again = TRUE;
2373 }
2374 break;
2375
2376 case 0xfc: /* CALL !!abs20 */
2377 if (symval < 65536)
2378 {
2379 insn[0] = 0xfd;
2380 insn[1] = symval & 0xff;
2381 insn[2] = symval >> 8;
e896287c 2382 SNIP (2, 1, R_RL78_DIR16U);
9cea966c
DD		 2383 *again = TRUE;
2384 }
2385 else if (pcrel < 32767
2386 && pcrel > -32767)
2387 {
2388 insn[0] = 0xfe;
2389 insn[1] = pcrel & 0xff;
2390 insn[2] = pcrel >> 8;
2391 SNIP (2, 1, R_RL78_DIR16S_PCREL);
2392 *again = TRUE;
2393 }
2394 break;
2395
2396 case 0x61: /* PREFIX */
2397 /* For SKIP/BR, we change the BR opcode and delete the
2398 SKIP. That way, we don't have to find and change the
2399 relocation for the BR. */
1122dc88
DD		 2400 /* Note that, for the case where we're skipping some
2401 other insn, we have no "other" reloc but that's safe
2402 here anyway. */
9cea966c
DD		 2403 switch (insn[1])
2404 {
e896287c
DD		 2405 case 0xd3: /* BNH */
2406 case 0xc3: /* BH */
2407 if (insn[2] == 0x03 && insn[3] == 0xee
2408 && (srel->r_offset - irel->r_offset) > 2) /* a B<c> without its own reloc */
2409 {
2410 /* Another long branch by gas:
2411 61 D3 03 EE ad.dr */
2412 if (pcrel < 127
2413 && pcrel > -127)
2414 {
2415 insn[1] ^= 0x10; /* invert conditional */
2416 SNIPNR (5, 1);
2417 SNIP (2, 2, R_RL78_DIR8S_PCREL);
2418 insn[2] = pcrel;
2419 *again = TRUE;
2420 }
2421 }
2422 break;
2423
9cea966c
DD		 2424 case 0xc8: /* SKC */
2425 if (insn[2] == 0xef)
2426 {
2427 insn[2] = 0xde; /* BNC */
2428 SNIPNR (0, 2);
2429 }
2430 break;
2431
2432 case 0xd8: /* SKNC */
2433 if (insn[2] == 0xef)
2434 {
2435 insn[2] = 0xdc; /* BC */
2436 SNIPNR (0, 2);
2437 }
2438 break;
2439
2440 case 0xe8: /* SKZ */
2441 if (insn[2] == 0xef)
2442 {
2443 insn[2] = 0xdf; /* BNZ */
2444 SNIPNR (0, 2);
2445 }
2446 break;
2447
2448 case 0xf8: /* SKNZ */
2449 if (insn[2] == 0xef)
2450 {
2451 insn[2] = 0xdd; /* BZ */
2452 SNIPNR (0, 2);
2453 }
2454 break;
2455
2456 case 0xe3: /* SKH */
2457 if (insn[2] == 0xef)
2458 {
2459 insn[2] = 0xd3; /* BNH */
2460 SNIPNR (1, 1); /* we reuse the 0x61 prefix from the SKH */
2461 }
2462 break;
2463
2464 case 0xf3: /* SKNH */
2465 if (insn[2] == 0xef)
2466 {
2467 insn[2] = 0xc3; /* BH */
2468 SNIPNR (1, 1); /* we reuse the 0x61 prefix from the SKH */
2469 }
2470 break;
2471 }
2472 break;
2473 }
9cea966c
DD		 2474 }
2475
71eef2bd 2476 if ((irel->r_addend & RL78_RELAXA_MASK) == RL78_RELAXA_ADDR16
07d6d2b8 2477 && nrelocs > 0)
9cea966c
DD		 2478 {
2479 /*----------------------------------------------------------------------*/
2480 /* Some insns have both a 16-bit address operand and an 8-bit
2481 variant if the address is within a special range:
2482
2483 Address 16-bit operand SADDR range SFR range
2484 FFF00-FFFFF 0xff00-0xffff 0x00-0xff
07d6d2b8 2485 FFE20-FFF1F 0xfe20-0xff1f 0x00-0xff
9cea966c
DD		 2486
2487 The RELAX_ADDR16[] array has the insn encodings for the
2488 16-bit operand version, as well as the SFR and SADDR
2489 variants. We only need to replace the encodings and
2490 adjust the operand.
2491
2492 Note: we intentionally do not attempt to decode and skip
2493 any ES: prefix, as adding ES: means the addr16 (likely)
2494 no longer points to saddr/sfr space.
2495 */
2496
2497 int is_sfr;
2498 int is_saddr;
2499 int idx;
2500 int poff;
2501
2502 GET_RELOC;
2503
9cea966c
DD		 2504 if (0xffe20 <= symval && symval <= 0xfffff)
2505 {
2506
2507 is_saddr = (0xffe20 <= symval && symval <= 0xfff1f);
2508 is_sfr = (0xfff00 <= symval && symval <= 0xfffff);
2509
2510 for (idx = 0; relax_addr16[idx].insn != -1; idx ++)
2511 {
2512 if (relax_addr16[idx].prefix != -1
2513 && insn[0] == relax_addr16[idx].prefix
2514 && insn[1] == relax_addr16[idx].insn)
2515 {
2516 poff = 1;
2517 }
2518 else if (relax_addr16[idx].prefix == -1
2519 && insn[0] == relax_addr16[idx].insn)
2520 {
2521 poff = 0;
2522 }
2523 else
2524 continue;
2525
2526 /* We have a matched insn, and poff is 0 or 1 depending
2527 on the base pattern size. */
2528
2529 if (is_sfr && relax_addr16[idx].insn_for_sfr != -1)
2530 {
2531 insn[poff] = relax_addr16[idx].insn_for_sfr;
2532 SNIP (poff+2, 1, R_RL78_RH_SFR);
9cea966c
DD		 2533 }
2534
2535 else if (is_saddr && relax_addr16[idx].insn_for_saddr != -1)
2536 {
2537 insn[poff] = relax_addr16[idx].insn_for_saddr;
2538 SNIP (poff+2, 1, R_RL78_RH_SADDR);
9cea966c 2539 }
9cea966c
DD		 2540 }
2541 }
2542 }
9cea966c 2543 /*----------------------------------------------------------------------*/
9cea966c
DD		 2544 }
2545
2546 return TRUE;
2547
2548 error_return:
2549 if (free_relocs != NULL)
2550 free (free_relocs);
2551
2552 if (free_contents != NULL)
2553 free (free_contents);
2554
2555 if (shndx_buf != NULL)
2556 {
2557 shndx_hdr->contents = NULL;
2558 free (shndx_buf);
2559 }
2560
2561 if (free_intsyms != NULL)
2562 free (free_intsyms);
2563
99c513f6
DD		 2564 return TRUE;
2565}
2566
2567\f
2568
2569#define ELF_ARCH bfd_arch_rl78
2570#define ELF_MACHINE_CODE EM_RL78
2571#define ELF_MAXPAGESIZE 0x1000
2572
6d00b590 2573#define TARGET_LITTLE_SYM rl78_elf32_vec
99c513f6
DD		 2574#define TARGET_LITTLE_NAME "elf32-rl78"
2575
2576#define elf_info_to_howto_rel NULL
2577#define elf_info_to_howto rl78_info_to_howto_rela
2578#define elf_backend_object_p rl78_elf_object_p
2579#define elf_backend_relocate_section rl78_elf_relocate_section
07d6d2b8 2580#define elf_symbol_leading_char ('_')
99c513f6
DD		 2581#define elf_backend_can_gc_sections 1
2582
2583#define bfd_elf32_bfd_reloc_type_lookup rl78_reloc_type_lookup
2584#define bfd_elf32_bfd_reloc_name_lookup rl78_reloc_name_lookup
2585#define bfd_elf32_bfd_set_private_flags rl78_elf_set_private_flags
2586#define bfd_elf32_bfd_merge_private_bfd_data rl78_elf_merge_private_bfd_data
2587#define bfd_elf32_bfd_print_private_bfd_data rl78_elf_print_private_bfd_data
2588
2589#define bfd_elf32_bfd_relax_section rl78_elf_relax_section
07d6d2b8 2590#define elf_backend_check_relocs rl78_elf_check_relocs
99c513f6
DD		 2591#define elf_backend_always_size_sections \
2592 rl78_elf_always_size_sections
2593#define elf_backend_finish_dynamic_sections \
2594 rl78_elf_finish_dynamic_sections
2595
2596#include "elf32-target.h"
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