include/configs/MPC8308RDB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2009-2010 Freescale Semiconductor, Inc.
   4  * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, [email protected]
   5  *
   6  */
   7
   8 #ifndef __CONFIG_H
   9 #define __CONFIG_H
  10
  11 /*
  12  * High Level Configuration Options
  13  */
  14 #define CONFIG_E300             1 /* E300 family */
  15
  16 #ifdef CONFIG_MMC
  17 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC83xx_ESDHC_ADDR
  18 #define CONFIG_SYS_FSL_ESDHC_USE_PIO
  19 #endif
  20
  21 /*
  22  * On-board devices
  23  *
  24  * TSEC1 is SoC TSEC
  25  * TSEC2 is VSC switch
  26  */
  27 #define CONFIG_TSEC1
  28 #define CONFIG_VSC7385_ENET
  29
  30 /*
  31  * Hardware Reset Configuration Word
  32  * if CLKIN is 66.66MHz, then
  33  * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz
  34  * We choose the A type silicon as default, so the core is 400Mhz.
  35  */
  36 #define CONFIG_SYS_HRCW_LOW (\
  37         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  38         HRCWL_DDR_TO_SCB_CLK_2X1 |\
  39         HRCWL_SVCOD_DIV_2 |\
  40         HRCWL_CSB_TO_CLKIN_4X1 |\
  41         HRCWL_CORE_TO_CSB_3X1)
  42 /*
  43  * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits
  44  * in 8308's HRCWH according to the manual, but original Freescale's
  45  * code has them and I've expirienced some problems using the board
  46  * with BDI3000 attached when I've tried to set these bits to zero
  47  * (UART doesn't work after the 'reset run' command).
  48  */
  49 #define CONFIG_SYS_HRCW_HIGH (\
  50         HRCWH_PCI_HOST |\
  51         HRCWH_PCI1_ARBITER_ENABLE |\
  52         HRCWH_CORE_ENABLE |\
  53         HRCWH_FROM_0X00000100 |\
  54         HRCWH_BOOTSEQ_DISABLE |\
  55         HRCWH_SW_WATCHDOG_DISABLE |\
  56         HRCWH_ROM_LOC_LOCAL_16BIT |\
  57         HRCWH_RL_EXT_LEGACY |\
  58         HRCWH_TSEC1M_IN_RGMII |\
  59         HRCWH_TSEC2M_IN_RGMII |\
  60         HRCWH_BIG_ENDIAN)
  61
  62 /*
  63  * System IO Config
  64  */
  65 #define CONFIG_SYS_SICRH (\
  66         SICRH_ESDHC_A_SD |\
  67         SICRH_ESDHC_B_SD |\
  68         SICRH_ESDHC_C_SD |\
  69         SICRH_GPIO_A_TSEC2 |\
  70         SICRH_GPIO_B_TSEC2_GTX_CLK125 |\
  71         SICRH_IEEE1588_A_GPIO |\
  72         SICRH_USB |\
  73         SICRH_GTM_GPIO |\
  74         SICRH_IEEE1588_B_GPIO |\
  75         SICRH_ETSEC2_CRS |\
  76         SICRH_GPIOSEL_1 |\
  77         SICRH_TMROBI_V3P3 |\
  78         SICRH_TSOBI1_V2P5 |\
  79         SICRH_TSOBI2_V2P5)      /* 0x01b7d103 */
  80 #define CONFIG_SYS_SICRL (\
  81         SICRL_SPI_PF0 |\
  82         SICRL_UART_PF0 |\
  83         SICRL_IRQ_PF0 |\
  84         SICRL_I2C2_PF0 |\
  85         SICRL_ETSEC1_GTX_CLK125)        /* 0x00000040 */
  86
  87 /*
  88  * IMMR new address
  89  */
  90 #define CONFIG_SYS_IMMR         0xE0000000
  91
  92 /*
  93  * SERDES
  94  */
  95 #define CONFIG_FSL_SERDES
  96 #define CONFIG_FSL_SERDES1      0xe3000
  97
  98 /*
  99  * Arbiter Setup
 100  */
 101 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
 102 #define CONFIG_SYS_ACR_RPTCNT   3 /* Arbiter repeat count is 4 */
 103 #define CONFIG_SYS_SPCR_TSECEP  3 /* eTSEC emergency priority is highest */
 104
 105 /*
 106  * DDR Setup
 107  */
 108 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory */
 109 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
 110 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
 111 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
 112 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
 113                                 | DDRCDR_PZ_LOZ \
 114                                 | DDRCDR_NZ_LOZ \
 115                                 | DDRCDR_ODT \
 116                                 | DDRCDR_Q_DRN)
 117                                 /* 0x7b880001 */
 118 /*
 119  * Manually set up DDR parameters
 120  * consist of two chips HY5PS12621BFP-C4 from HYNIX
 121  */
 122
 123 #define CONFIG_SYS_DDR_SIZE             128 /* MB */
 124
 125 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
 126 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
 127                                 | CSCONFIG_ODT_RD_NEVER \
 128                                 | CSCONFIG_ODT_WR_ONLY_CURRENT \
 129                                 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
 130                                 /* 0x80010102 */
 131 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
 132 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
 133                                 | (0 << TIMING_CFG0_WRT_SHIFT) \
 134                                 | (0 << TIMING_CFG0_RRT_SHIFT) \
 135                                 | (0 << TIMING_CFG0_WWT_SHIFT) \
 136                                 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
 137                                 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
 138                                 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
 139                                 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
 140                                 /* 0x00220802 */
 141 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
 142                                 | (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \
 143                                 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
 144                                 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
 145                                 | (6 << TIMING_CFG1_REFREC_SHIFT) \
 146                                 | (2 << TIMING_CFG1_WRREC_SHIFT) \
 147                                 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
 148                                 | (2 << TIMING_CFG1_WRTORD_SHIFT))
 149                                 /* 0x27256222 */
 150 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
 151                                 | (4 << TIMING_CFG2_CPO_SHIFT) \
 152                                 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
 153                                 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
 154                                 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
 155                                 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
 156                                 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
 157                                 /* 0x121048c5 */
 158 #define CONFIG_SYS_DDR_INTERVAL ((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \
 159                                 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
 160                                 /* 0x03600100 */
 161 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SREN \
 162                                 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
 163                                 | SDRAM_CFG_DBW_32)
 164                                 /* 0x43080000 */
 165
 166 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000 /* 1 posted refresh */
 167 #define CONFIG_SYS_DDR_MODE             ((0x0448 << SDRAM_MODE_ESD_SHIFT) \
 168                                 | (0x0232 << SDRAM_MODE_SD_SHIFT))
 169                                 /* ODT 150ohm CL=3, AL=1 on SDRAM */
 170 #define CONFIG_SYS_DDR_MODE2            0x00000000
 171
 172 /*
 173  * Memory test
 174  */
 175 #define CONFIG_SYS_MEMTEST_START        0x00001000 /* memtest region */
 176 #define CONFIG_SYS_MEMTEST_END          0x07f00000
 177
 178 /*
 179  * The reserved memory
 180  */
 181 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
 182
 183 #define CONFIG_SYS_MONITOR_LEN  (512 * 1024) /* Reserve 512 kB for Mon */
 184 #define CONFIG_SYS_MALLOC_LEN   (512 * 1024) /* Reserved for malloc */
 185
 186 /*
 187  * Initial RAM Base Address Setup
 188  */
 189 #define CONFIG_SYS_INIT_RAM_LOCK        1
 190 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
 191 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* Size of used area in RAM */
 192 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 193         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 194
 195 /*
 196  * Local Bus Configuration & Clock Setup
 197  */
 198 #define CONFIG_SYS_LCRR_DBYP            LCRR_DBYP
 199 #define CONFIG_SYS_LCRR_CLKDIV          LCRR_CLKDIV_2
 200 #define CONFIG_SYS_LBC_LBCR             0x00040000
 201
 202 /*
 203  * FLASH on the Local Bus
 204  */
 205 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
 206
 207 #define CONFIG_SYS_FLASH_BASE           0xFE000000 /* FLASH base address */
 208 #define CONFIG_SYS_FLASH_SIZE           8 /* FLASH size is 8M */
 209
 210 /* Window base at flash base */
 211 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 212 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_8MB)
 213
 214 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE \
 215                                 | BR_PS_16      /* 16 bit port */ \
 216                                 | BR_MS_GPCM    /* MSEL = GPCM */ \
 217                                 | BR_V)         /* valid */
 218 #define CONFIG_SYS_OR0_PRELIM   (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
 219                                 | OR_UPM_XAM \
 220                                 | OR_GPCM_CSNT \
 221                                 | OR_GPCM_ACS_DIV2 \
 222                                 | OR_GPCM_XACS \
 223                                 | OR_GPCM_SCY_15 \
 224                                 | OR_GPCM_TRLX_SET \
 225                                 | OR_GPCM_EHTR_SET)
 226
 227 #define CONFIG_SYS_MAX_FLASH_BANKS      1 /* number of banks */
 228 /* 127 64KB sectors and 8 8KB top sectors per device */
 229 #define CONFIG_SYS_MAX_FLASH_SECT       135
 230
 231 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000 /* Flash Erase Timeout (ms) */
 232 #define CONFIG_SYS_FLASH_WRITE_TOUT     500 /* Flash Write Timeout (ms) */
 233
 234 /*
 235  * NAND Flash on the Local Bus
 236  */
 237 #define CONFIG_SYS_NAND_BASE    0xE0600000              /* 0xE0600000 */
 238 #define CONFIG_SYS_NAND_WINDOW_SIZE     (32 * 1024)     /* 0x00008000 */
 239 #define CONFIG_SYS_BR1_PRELIM   (CONFIG_SYS_NAND_BASE \
 240                                 | BR_DECC_CHK_GEN       /* Use HW ECC */ \
 241                                 | BR_PS_8               /* 8 bit Port */ \
 242                                 | BR_MS_FCM             /* MSEL = FCM */ \
 243                                 | BR_V)                 /* valid */
 244 #define CONFIG_SYS_OR1_PRELIM   (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \
 245                                 | OR_FCM_CSCT \
 246                                 | OR_FCM_CST \
 247                                 | OR_FCM_CHT \
 248                                 | OR_FCM_SCY_1 \
 249                                 | OR_FCM_TRLX \
 250                                 | OR_FCM_EHTR)
 251                                 /* 0xFFFF8396 */
 252
 253 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_NAND_BASE
 254 #define CONFIG_SYS_LBLAWAR1_PRELIM      (LBLAWAR_EN | LBLAWAR_32KB)
 255
 256 #ifdef CONFIG_VSC7385_ENET
 257 #define CONFIG_TSEC2
 258                                         /* VSC7385 Base address on CS2 */
 259 #define CONFIG_SYS_VSC7385_BASE         0xF0000000
 260 #define CONFIG_SYS_VSC7385_SIZE         (128 * 1024) /* 0x00020000 */
 261 #define CONFIG_SYS_BR2_PRELIM           (CONFIG_SYS_VSC7385_BASE \
 262                                         | BR_PS_8       /* 8-bit port */ \
 263                                         | BR_MS_GPCM    /* MSEL = GPCM */ \
 264                                         | BR_V)         /* valid */
 265                                         /* 0xF0000801 */
 266 #define CONFIG_SYS_OR2_PRELIM           (P2SZ_TO_AM(CONFIG_SYS_VSC7385_SIZE) \
 267                                         | OR_GPCM_CSNT \
 268                                         | OR_GPCM_XACS \
 269                                         | OR_GPCM_SCY_15 \
 270                                         | OR_GPCM_SETA \
 271                                         | OR_GPCM_TRLX_SET \
 272                                         | OR_GPCM_EHTR_SET)
 273                                         /* 0xFFFE09FF */
 274 /* Access window base at VSC7385 base */
 275 #define CONFIG_SYS_LBLAWBAR2_PRELIM     CONFIG_SYS_VSC7385_BASE
 276 /* Access window size 128K */
 277 #define CONFIG_SYS_LBLAWAR2_PRELIM      (LBLAWAR_EN | LBLAWAR_128KB)
 278 /* The flash address and size of the VSC7385 firmware image */
 279 #define CONFIG_VSC7385_IMAGE            0xFE7FE000
 280 #define CONFIG_VSC7385_IMAGE_SIZE       8192
 281 #endif
 282 /*
 283  * Serial Port
 284  */
 285 #define CONFIG_SYS_NS16550_SERIAL
 286 #define CONFIG_SYS_NS16550_REG_SIZE     1
 287 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 288
 289 #define CONFIG_SYS_BAUDRATE_TABLE  \
 290         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 291
 292 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
 293 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
 294
 295 /* I2C */
 296 #define CONFIG_SYS_I2C
 297 #define CONFIG_SYS_I2C_FSL
 298 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 299 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 300 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 301 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 302 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 303 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 304 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x51} }
 305
 306 /*
 307  * SPI on header J8
 308  *
 309  * WARNING: enabling this will break TSEC2 (connected to the Vitesse switch)
 310  * due to a pinmux conflict between GPIO9 (SPI chip select )and the TSEC2 pins.
 311  */
 312 #ifdef CONFIG_MPC8XXX_SPI
 313 #define CONFIG_USE_SPIFLASH
 314 #endif
 315
 316 /*
 317  * Board info - revision and where boot from
 318  */
 319 #define CONFIG_SYS_I2C_PCF8574A_ADDR    0x39
 320
 321 /*
 322  * Config on-board RTC
 323  */
 324 #define CONFIG_RTC_DS1337       /* ds1339 on board, use ds1337 rtc via i2c */
 325 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
 326
 327 /*
 328  * General PCI
 329  * Addresses are mapped 1-1.
 330  */
 331 #define CONFIG_SYS_PCIE1_BASE           0xA0000000
 332 #define CONFIG_SYS_PCIE1_MEM_BASE       0xA0000000
 333 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xA0000000
 334 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000
 335 #define CONFIG_SYS_PCIE1_CFG_BASE       0xB0000000
 336 #define CONFIG_SYS_PCIE1_CFG_SIZE       0x01000000
 337 #define CONFIG_SYS_PCIE1_IO_BASE        0x00000000
 338 #define CONFIG_SYS_PCIE1_IO_PHYS        0xB1000000
 339 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00800000
 340
 341 /* enable PCIE clock */
 342 #define CONFIG_SYS_SCCR_PCIEXP1CM       1
 343
 344 #define CONFIG_PCI_INDIRECT_BRIDGE
 345 #define CONFIG_PCIE
 346
 347 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957   /* Freescale */
 348 #define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1
 349
 350 /*
 351  * TSEC
 352  */
 353 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 354 #define CONFIG_SYS_TSEC1        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
 355 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
 356 #define CONFIG_SYS_TSEC2        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
 357
 358 /*
 359  * TSEC ethernet configuration
 360  */
 361 #define CONFIG_TSEC1_NAME       "eTSEC0"
 362 #define CONFIG_TSEC2_NAME       "eTSEC1"
 363 #define TSEC1_PHY_ADDR          2
 364 #define TSEC2_PHY_ADDR          1
 365 #define TSEC1_PHYIDX            0
 366 #define TSEC2_PHYIDX            0
 367 #define TSEC1_FLAGS             TSEC_GIGABIT
 368 #define TSEC2_FLAGS             TSEC_GIGABIT
 369
 370 /* Options are: eTSEC[0-1] */
 371 #define CONFIG_ETHPRIME         "eTSEC0"
 372
 373 /*
 374  * Environment
 375  */
 376 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + \
 377                                  CONFIG_SYS_MONITOR_LEN)
 378 #define CONFIG_ENV_SECT_SIZE    0x10000 /* 64K(one sector) for env */
 379 #define CONFIG_ENV_SIZE         0x2000
 380 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
 381 #define CONFIG_ENV_SIZE_REDUND  CONFIG_ENV_SIZE
 382
 383 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 384 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 385
 386 /*
 387  * BOOTP options
 388  */
 389 #define CONFIG_BOOTP_BOOTFILESIZE
 390
 391 /*
 392  * Command line configuration.
 393  */
 394
 395 /*
 396  * Miscellaneous configurable options
 397  */
 398 #define CONFIG_SYS_LOAD_ADDR            0x2000000 /* default load address */
 399
 400 #define CONFIG_SYS_CBSIZE       1024 /* Console I/O Buffer Size */
 401
 402 /* Boot Argument Buffer Size */
 403 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 404
 405 /*
 406  * For booting Linux, the board info and command line data
 407  * have to be in the first 256 MB of memory, since this is
 408  * the maximum mapped by the Linux kernel during initialization.
 409  */
 410 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20) /* Initial Memory map for Linux */
 411 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 412
 413 /*
 414  * Core HID Setup
 415  */
 416 #define CONFIG_SYS_HID0_INIT    0x000000000
 417 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK | \
 418                                  HID0_ENABLE_INSTRUCTION_CACHE | \
 419                                  HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
 420 #define CONFIG_SYS_HID2         HID2_HBE
 421
 422 /*
 423  * MMU Setup
 424  */
 425
 426 /* DDR: cache cacheable */
 427 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
 428                                         BATL_MEMCOHERENCE)
 429 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \
 430                                         BATU_VS | BATU_VP)
 431 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 432 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 433
 434 /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
 435 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_IMMR | BATL_PP_RW | \
 436                         BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 437 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \
 438                                         BATU_VP)
 439 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 440 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 441
 442 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
 443 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
 444                                         BATL_MEMCOHERENCE)
 445 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \
 446                                         BATU_VS | BATU_VP)
 447 #define CONFIG_SYS_DBAT2L       (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
 448                                         BATL_CACHEINHIBIT | \
 449                                         BATL_GUARDEDSTORAGE)
 450 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 451
 452 /* Stack in dcache: cacheable, no memory coherence */
 453 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
 454 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
 455                                         BATU_VS | BATU_VP)
 456 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
 457 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 458
 459 /*
 460  * Environment Configuration
 461  */
 462
 463 #define CONFIG_ENV_OVERWRITE
 464
 465 #if defined(CONFIG_TSEC_ENET)
 466 #define CONFIG_HAS_ETH0
 467 #define CONFIG_HAS_ETH1
 468 #endif
 469
 470 #define CONFIG_LOADADDR 800000  /* default location for tftp and bootm */
 471
 472
 473 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 474         "netdev=eth0\0"                                                 \
 475         "consoledev=ttyS0\0"                                            \
 476         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 477                 "nfsroot=${serverip}:${rootpath}\0"                     \
 478         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 479         "addip=setenv bootargs ${bootargs} "                            \
 480                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 481                 ":${hostname}:${netdev}:off panic=1\0"                  \
 482         "addtty=setenv bootargs ${bootargs}"                            \
 483                 " console=${consoledev},${baudrate}\0"                  \
 484         "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"              \
 485         "addmisc=setenv bootargs ${bootargs}\0"                         \
 486         "kernel_addr=FE080000\0"                                        \
 487         "fdt_addr=FE280000\0"                                           \
 488         "ramdisk_addr=FE290000\0"                                       \
 489         "u-boot=mpc8308rdb/u-boot.bin\0"                                \
 490         "kernel_addr_r=1000000\0"                                       \
 491         "fdt_addr_r=C00000\0"                                           \
 492         "hostname=mpc8308rdb\0"                                         \
 493         "bootfile=mpc8308rdb/uImage\0"                                  \
 494         "fdtfile=mpc8308rdb/mpc8308rdb.dtb\0"                           \
 495         "rootpath=/opt/eldk-4.2/ppc_6xx\0"                              \
 496         "flash_self=run ramargs addip addtty addmtd addmisc;"           \
 497                 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"    \
 498         "flash_nfs=run nfsargs addip addtty addmtd addmisc;"            \
 499                 "bootm ${kernel_addr} - ${fdt_addr}\0"                  \
 500         "net_nfs=tftp ${kernel_addr_r} ${bootfile};"                    \
 501                 "tftp ${fdt_addr_r} ${fdtfile};"                        \
 502                 "run nfsargs addip addtty addmtd addmisc;"              \
 503                 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0"              \
 504         "bootcmd=run flash_self\0"                                      \
 505         "load=tftp ${loadaddr} ${u-boot}\0"                             \
 506         "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE)      \
 507                 " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
 508                 " +${filesize};cp.b ${fileaddr} "                       \
 509                 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0"   \
 510         "upd=run load update\0"                                         \
 511
 512 #endif  /* __CONFIG_H */