drivers/net/dwc_eth_qos_stm32.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2024, Marek Vasut <[email protected]>
   4  *
   5  * This is code moved from drivers/net/dwc_eth_qos.c , which is:
   6  * Copyright (c) 2016, NVIDIA CORPORATION.
   7  */
   8
   9 #include <asm/cache.h>
  10 #include <asm/gpio.h>
  11 #include <asm/io.h>
  12 #include <clk.h>
  13 #include <cpu_func.h>
  14 #include <dm.h>
  15 #include <dm/device_compat.h>
  16 #include <errno.h>
  17 #include <eth_phy.h>
  18 #include <log.h>
  19 #include <malloc.h>
  20 #include <memalign.h>
  21 #include <miiphy.h>
  22 #include <net.h>
  23 #include <netdev.h>
  24 #include <phy.h>
  25 #include <regmap.h>
  26 #include <reset.h>
  27 #include <syscon.h>
  28 #include <wait_bit.h>
  29 #include <linux/bitfield.h>
  30 #include <linux/delay.h>
  31
  32 #include "dwc_eth_qos.h"
  33
  34 /* SYSCFG registers */
  35 #define SYSCFG_PMCSETR          0x04
  36 #define SYSCFG_PMCCLRR_MP13     0x08
  37 #define SYSCFG_PMCCLRR_MP15     0x44
  38
  39 #define SYSCFG_PMCSETR_ETH1_MASK        GENMASK(23, 16)
  40 #define SYSCFG_PMCSETR_ETH2_MASK        GENMASK(31, 24)
  41
  42 #define SYSCFG_PMCSETR_ETH_CLK_SEL      BIT(16)
  43 #define SYSCFG_PMCSETR_ETH_REF_CLK_SEL  BIT(17)
  44
  45 /* STM32MP15xx specific bit */
  46 #define SYSCFG_PMCSETR_ETH_SELMII       BIT(20)
  47
  48 #define SYSCFG_PMCSETR_ETH_SEL_MASK     GENMASK(23, 21)
  49 #define SYSCFG_PMCSETR_ETH_SEL_GMII_MII 0x0
  50 #define SYSCFG_PMCSETR_ETH_SEL_RGMII    0x1
  51 #define SYSCFG_PMCSETR_ETH_SEL_RMII     0x4
  52
  53 static ulong eqos_get_tick_clk_rate_stm32(struct udevice *dev)
  54 {
  55         struct eqos_priv __maybe_unused *eqos = dev_get_priv(dev);
  56
  57         if (!CONFIG_IS_ENABLED(CLK))
  58                 return 0;
  59
  60         return clk_get_rate(&eqos->clk_master_bus);
  61 }
  62
  63 static int eqos_start_clks_stm32(struct udevice *dev)
  64 {
  65         struct eqos_priv __maybe_unused *eqos = dev_get_priv(dev);
  66         int ret;
  67
  68         if (!CONFIG_IS_ENABLED(CLK))
  69                 return 0;
  70
  71         dev_dbg(dev, "%s:\n", __func__);
  72
  73         ret = clk_enable(&eqos->clk_master_bus);
  74         if (ret < 0) {
  75                 dev_err(dev, "clk_enable(clk_master_bus) failed: %d\n", ret);
  76                 goto err;
  77         }
  78
  79         ret = clk_enable(&eqos->clk_rx);
  80         if (ret < 0) {
  81                 dev_err(dev, "clk_enable(clk_rx) failed: %d\n", ret);
  82                 goto err_disable_clk_master_bus;
  83         }
  84
  85         ret = clk_enable(&eqos->clk_tx);
  86         if (ret < 0) {
  87                 dev_err(dev, "clk_enable(clk_tx) failed: %d\n", ret);
  88                 goto err_disable_clk_rx;
  89         }
  90
  91         if (clk_valid(&eqos->clk_ck) && !eqos->clk_ck_enabled) {
  92                 ret = clk_enable(&eqos->clk_ck);
  93                 if (ret < 0) {
  94                         dev_err(dev, "clk_enable(clk_ck) failed: %d\n", ret);
  95                         goto err_disable_clk_tx;
  96                 }
  97                 eqos->clk_ck_enabled = true;
  98         }
  99
 100         dev_dbg(dev, "%s: OK\n", __func__);
 101         return 0;
 102
 103 err_disable_clk_tx:
 104         clk_disable(&eqos->clk_tx);
 105 err_disable_clk_rx:
 106         clk_disable(&eqos->clk_rx);
 107 err_disable_clk_master_bus:
 108         clk_disable(&eqos->clk_master_bus);
 109 err:
 110         dev_dbg(dev, "%s: FAILED: %d\n", __func__, ret);
 111
 112         return ret;
 113 }
 114
 115 static int eqos_stop_clks_stm32(struct udevice *dev)
 116 {
 117         struct eqos_priv __maybe_unused *eqos = dev_get_priv(dev);
 118
 119         if (!CONFIG_IS_ENABLED(CLK))
 120                 return 0;
 121
 122         dev_dbg(dev, "%s:\n", __func__);
 123
 124         clk_disable(&eqos->clk_tx);
 125         clk_disable(&eqos->clk_rx);
 126         clk_disable(&eqos->clk_master_bus);
 127
 128         dev_dbg(dev, "%s: OK\n", __func__);
 129
 130         return 0;
 131 }
 132
 133 static int eqos_probe_syscfg_stm32(struct udevice *dev,
 134                                    phy_interface_t interface_type)
 135 {
 136         /* Ethernet 50MHz RMII clock selection. */
 137         const bool eth_ref_clk_sel = dev_read_bool(dev, "st,eth-ref-clk-sel");
 138         /* SoC is STM32MP13xx with two ethernet MACs */
 139         const bool is_mp13 = device_is_compatible(dev, "st,stm32mp13-dwmac");
 140         /* Gigabit Ethernet 125MHz clock selection. */
 141         const bool eth_clk_sel = dev_read_bool(dev, "st,eth-clk-sel");
 142         /* Ethernet clock source is RCC. */
 143         const bool ext_phyclk = dev_read_bool(dev, "st,ext-phyclk");
 144         struct regmap *regmap;
 145         u32 regmap_mask;
 146         u32 value;
 147
 148         regmap = syscon_regmap_lookup_by_phandle(dev, "st,syscon");
 149         if (IS_ERR(regmap))
 150                 return PTR_ERR(regmap);
 151
 152         regmap_mask = dev_read_u32_index_default(dev, "st,syscon", 2,
 153                                                  SYSCFG_PMCSETR_ETH1_MASK);
 154
 155         switch (interface_type) {
 156         case PHY_INTERFACE_MODE_MII:
 157                 dev_dbg(dev, "PHY_INTERFACE_MODE_MII\n");
 158                 value = FIELD_PREP(SYSCFG_PMCSETR_ETH_SEL_MASK,
 159                                    SYSCFG_PMCSETR_ETH_SEL_GMII_MII);
 160                 /*
 161                  * STM32MP15xx supports both MII and GMII, STM32MP13xx MII only.
 162                  * SYSCFG_PMCSETR ETH_SELMII is present only on STM32MP15xx and
 163                  * acts as a selector between 0:GMII and 1:MII. As STM32MP13xx
 164                  * supports only MII, ETH_SELMII is not present.
 165                  */
 166                 if (!is_mp13)   /* Select MII mode on STM32MP15xx */
 167                         value |= SYSCFG_PMCSETR_ETH_SELMII;
 168                 break;
 169         case PHY_INTERFACE_MODE_GMII:   /* STM32MP15xx only */
 170                 dev_dbg(dev, "PHY_INTERFACE_MODE_GMII\n");
 171                 value = FIELD_PREP(SYSCFG_PMCSETR_ETH_SEL_MASK,
 172                                    SYSCFG_PMCSETR_ETH_SEL_GMII_MII);
 173                 /*
 174                  * If eth_clk_sel is set, use internal ETH_CLKx clock from RCC,
 175                  * otherwise use external clock from IO pin (requires matching
 176                  * GPIO block AF setting of that pin).
 177                  */
 178                 if (eth_clk_sel || ext_phyclk)
 179                         value |= SYSCFG_PMCSETR_ETH_CLK_SEL;
 180                 break;
 181         case PHY_INTERFACE_MODE_RMII:
 182                 dev_dbg(dev, "PHY_INTERFACE_MODE_RMII\n");
 183                 value = FIELD_PREP(SYSCFG_PMCSETR_ETH_SEL_MASK,
 184                                    SYSCFG_PMCSETR_ETH_SEL_RMII);
 185                 /*
 186                  * If eth_ref_clk_sel is set, use internal clock from RCC,
 187                  * otherwise use external clock from ETHn_RX_CLK/ETHn_REF_CLK
 188                  * IO pin (requires matching GPIO block AF setting of that
 189                  * pin).
 190                  */
 191                 if (eth_ref_clk_sel || ext_phyclk)
 192                         value |= SYSCFG_PMCSETR_ETH_REF_CLK_SEL;
 193                 break;
 194         case PHY_INTERFACE_MODE_RGMII:
 195         case PHY_INTERFACE_MODE_RGMII_ID:
 196         case PHY_INTERFACE_MODE_RGMII_RXID:
 197         case PHY_INTERFACE_MODE_RGMII_TXID:
 198                 dev_dbg(dev, "PHY_INTERFACE_MODE_RGMII\n");
 199                 value = FIELD_PREP(SYSCFG_PMCSETR_ETH_SEL_MASK,
 200                                    SYSCFG_PMCSETR_ETH_SEL_RGMII);
 201                 /*
 202                  * If eth_clk_sel is set, use internal ETH_CLKx clock from RCC,
 203                  * otherwise use external clock from ETHx_CLK125 pin (requires
 204                  * matching GPIO block AF setting of that pin).
 205                  */
 206                 if (eth_clk_sel || ext_phyclk)
 207                         value |= SYSCFG_PMCSETR_ETH_CLK_SEL;
 208                 break;
 209         default:
 210                 dev_dbg(dev, "Do not manage %d interface\n",
 211                         interface_type);
 212                 /* Do not manage others interfaces */
 213                 return -EINVAL;
 214         }
 215
 216         /* Shift value at correct ethernet MAC offset in SYSCFG_PMCSETR */
 217         value <<= ffs(regmap_mask) - ffs(SYSCFG_PMCSETR_ETH1_MASK);
 218
 219         /* Update PMCCLRR (clear register) */
 220         regmap_write(regmap, is_mp13 ?
 221                              SYSCFG_PMCCLRR_MP13 : SYSCFG_PMCCLRR_MP15,
 222                              regmap_mask);
 223
 224         return regmap_update_bits(regmap, SYSCFG_PMCSETR, regmap_mask, value);
 225 }
 226
 227 static int eqos_probe_resources_stm32(struct udevice *dev)
 228 {
 229         struct eqos_priv *eqos = dev_get_priv(dev);
 230         phy_interface_t interface;
 231         int ret;
 232
 233         dev_dbg(dev, "%s:\n", __func__);
 234
 235         interface = eqos->config->interface(dev);
 236
 237         if (interface == PHY_INTERFACE_MODE_NA) {
 238                 dev_err(dev, "Invalid PHY interface\n");
 239                 return -EINVAL;
 240         }
 241
 242         ret = eqos_probe_syscfg_stm32(dev, interface);
 243         if (ret)
 244                 return -EINVAL;
 245
 246         ret = clk_get_by_name(dev, "stmmaceth", &eqos->clk_master_bus);
 247         if (ret) {
 248                 dev_err(dev, "clk_get_by_name(master_bus) failed: %d\n", ret);
 249                 goto err_probe;
 250         }
 251
 252         ret = clk_get_by_name(dev, "mac-clk-rx", &eqos->clk_rx);
 253         if (ret) {
 254                 dev_err(dev, "clk_get_by_name(rx) failed: %d\n", ret);
 255                 goto err_probe;
 256         }
 257
 258         ret = clk_get_by_name(dev, "mac-clk-tx", &eqos->clk_tx);
 259         if (ret) {
 260                 dev_err(dev, "clk_get_by_name(tx) failed: %d\n", ret);
 261                 goto err_probe;
 262         }
 263
 264         /*  Get ETH_CLK clocks (optional) */
 265         ret = clk_get_by_name(dev, "eth-ck", &eqos->clk_ck);
 266         if (ret)
 267                 dev_warn(dev, "No phy clock provided %d\n", ret);
 268
 269         dev_dbg(dev, "%s: OK\n", __func__);
 270
 271         return 0;
 272
 273 err_probe:
 274
 275         dev_dbg(dev, "%s: returns %d\n", __func__, ret);
 276
 277         return ret;
 278 }
 279
 280 static int eqos_remove_resources_stm32(struct udevice *dev)
 281 {
 282         dev_dbg(dev, "%s:\n", __func__);
 283
 284         return 0;
 285 }
 286
 287 static struct eqos_ops eqos_stm32_ops = {
 288         .eqos_inval_desc = eqos_inval_desc_generic,
 289         .eqos_flush_desc = eqos_flush_desc_generic,
 290         .eqos_inval_buffer = eqos_inval_buffer_generic,
 291         .eqos_flush_buffer = eqos_flush_buffer_generic,
 292         .eqos_probe_resources = eqos_probe_resources_stm32,
 293         .eqos_remove_resources = eqos_remove_resources_stm32,
 294         .eqos_stop_resets = eqos_null_ops,
 295         .eqos_start_resets = eqos_null_ops,
 296         .eqos_stop_clks = eqos_stop_clks_stm32,
 297         .eqos_start_clks = eqos_start_clks_stm32,
 298         .eqos_calibrate_pads = eqos_null_ops,
 299         .eqos_disable_calibration = eqos_null_ops,
 300         .eqos_set_tx_clk_speed = eqos_null_ops,
 301         .eqos_get_enetaddr = eqos_null_ops,
 302         .eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_stm32
 303 };
 304
 305 struct eqos_config __maybe_unused eqos_stm32mp13_config = {
 306         .reg_access_always_ok = false,
 307         .mdio_wait = 10000,
 308         .swr_wait = 50,
 309         .config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB,
 310         .config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_250_300,
 311         .axi_bus_width = EQOS_AXI_WIDTH_32,
 312         .interface = dev_read_phy_mode,
 313         .ops = &eqos_stm32_ops
 314 };
 315
 316 struct eqos_config __maybe_unused eqos_stm32mp15_config = {
 317         .reg_access_always_ok = false,
 318         .mdio_wait = 10000,
 319         .swr_wait = 50,
 320         .config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_AV,
 321         .config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_250_300,
 322         .axi_bus_width = EQOS_AXI_WIDTH_64,
 323         .interface = dev_read_phy_mode,
 324         .ops = &eqos_stm32_ops
 325 };