arch/arm/cpu/armv7/ls102xa/soc.c

   1 /*
   2  * Copyright 2015 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <asm/arch/clock.h>
   9 #include <asm/io.h>
  10 #include <asm/arch/immap_ls102xa.h>
  11 #include <asm/arch/ls102xa_soc.h>
  12 #include <asm/arch/ls102xa_stream_id.h>
  13
  14 struct liodn_id_table sec_liodn_tbl[] = {
  15         SET_SEC_JR_LIODN_ENTRY(0, 0x10, 0x10),
  16         SET_SEC_JR_LIODN_ENTRY(1, 0x10, 0x10),
  17         SET_SEC_JR_LIODN_ENTRY(2, 0x10, 0x10),
  18         SET_SEC_JR_LIODN_ENTRY(3, 0x10, 0x10),
  19         SET_SEC_RTIC_LIODN_ENTRY(a, 0x10),
  20         SET_SEC_RTIC_LIODN_ENTRY(b, 0x10),
  21         SET_SEC_RTIC_LIODN_ENTRY(c, 0x10),
  22         SET_SEC_RTIC_LIODN_ENTRY(d, 0x10),
  23         SET_SEC_DECO_LIODN_ENTRY(0, 0x10, 0x10),
  24         SET_SEC_DECO_LIODN_ENTRY(1, 0x10, 0x10),
  25         SET_SEC_DECO_LIODN_ENTRY(2, 0x10, 0x10),
  26         SET_SEC_DECO_LIODN_ENTRY(3, 0x10, 0x10),
  27         SET_SEC_DECO_LIODN_ENTRY(4, 0x10, 0x10),
  28         SET_SEC_DECO_LIODN_ENTRY(5, 0x10, 0x10),
  29         SET_SEC_DECO_LIODN_ENTRY(6, 0x10, 0x10),
  30         SET_SEC_DECO_LIODN_ENTRY(7, 0x10, 0x10),
  31 };
  32
  33 struct smmu_stream_id dev_stream_id[] = {
  34         { 0x100, 0x01, "ETSEC MAC1" },
  35         { 0x104, 0x02, "ETSEC MAC2" },
  36         { 0x108, 0x03, "ETSEC MAC3" },
  37         { 0x10c, 0x04, "PEX1" },
  38         { 0x110, 0x05, "PEX2" },
  39         { 0x114, 0x06, "qDMA" },
  40         { 0x118, 0x07, "SATA" },
  41         { 0x11c, 0x08, "USB3" },
  42         { 0x120, 0x09, "QE" },
  43         { 0x124, 0x0a, "eSDHC" },
  44         { 0x128, 0x0b, "eMA" },
  45         { 0x14c, 0x0c, "2D-ACE" },
  46         { 0x150, 0x0d, "USB2" },
  47         { 0x18c, 0x0e, "DEBUG" },
  48 };
  49
  50 unsigned int get_soc_major_rev(void)
  51 {
  52         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  53         unsigned int svr, major;
  54
  55         svr = in_be32(&gur->svr);
  56         major = SVR_MAJ(svr);
  57
  58         return major;
  59 }
  60
  61 int arch_soc_init(void)
  62 {
  63         struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
  64         struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
  65         unsigned int major;
  66
  67 #ifdef CONFIG_FSL_QSPI
  68         out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
  69 #endif
  70
  71 #ifdef CONFIG_FSL_DCU_FB
  72         out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN);
  73 #endif
  74
  75         /* Configure Little endian for SAI, ASRC and SPDIF */
  76         out_be32(&scfg->endiancr, SCFG_ENDIANCR_LE);
  77
  78         /*
  79          * Enable snoop requests and DVM message requests for
  80          * All the slave insterfaces.
  81          */
  82         out_le32(&cci->slave[0].snoop_ctrl,
  83                  CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
  84         out_le32(&cci->slave[1].snoop_ctrl,
  85                  CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
  86         out_le32(&cci->slave[2].snoop_ctrl,
  87                  CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
  88         out_le32(&cci->slave[4].snoop_ctrl,
  89                  CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
  90
  91         major = get_soc_major_rev();
  92         if (major == SOC_MAJOR_VER_1_0) {
  93                 /*
  94                  * Set CCI-400 Slave interface S1, S2 Shareable Override
  95                  * Register All transactions are treated as non-shareable
  96                  */
  97                 out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
  98                 out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
  99
 100                 /* Workaround for the issue that DDR could not respond to
 101                  * barrier transaction which is generated by executing DSB/ISB
 102                  * instruction. Set CCI-400 control override register to
 103                  * terminate the barrier transaction. After DDR is initialized,
 104                  * allow barrier transaction to DDR again */
 105                 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
 106         }
 107
 108         /* Enable all the snoop signal for various masters */
 109         out_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SEC_RD_WR |
 110                                 SCFG_SNPCNFGCR_DCU_RD_WR |
 111                                 SCFG_SNPCNFGCR_SATA_RD_WR |
 112                                 SCFG_SNPCNFGCR_USB3_RD_WR |
 113                                 SCFG_SNPCNFGCR_DBG_RD_WR |
 114                                 SCFG_SNPCNFGCR_EDMA_SNP);
 115
 116         /*
 117          * Memory controller require a register write before being enabled.
 118          * Affects: DDR
 119          * Register: EDDRTQCFG
 120          * Description: Memory controller performance is not optimal with
 121          *              default internal target queue register values.
 122          * Workaround: Write a value of 63b2_0042h to address: 157_020Ch.
 123          */
 124         out_be32(&scfg->eddrtqcfg, 0x63b20042);
 125
 126         return 0;
 127 }
 128
 129 int ls102xa_smmu_stream_id_init(void)
 130 {
 131         ls1021x_config_caam_stream_id(sec_liodn_tbl,
 132                                       ARRAY_SIZE(sec_liodn_tbl));
 133
 134         ls102xa_config_smmu_stream_id(dev_stream_id,
 135                                       ARRAY_SIZE(dev_stream_id));
 136
 137         return 0;
 138 }