board/freescale/t102xqds/t102xqds.c

   1 /*
   2  * Copyright 2014 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <command.h>
   9 #include <i2c.h>
  10 #include <netdev.h>
  11 #include <linux/compiler.h>
  12 #include <asm/mmu.h>
  13 #include <asm/processor.h>
  14 #include <asm/cache.h>
  15 #include <asm/immap_85xx.h>
  16 #include <asm/fsl_law.h>
  17 #include <asm/fsl_serdes.h>
  18 #include <asm/fsl_portals.h>
  19 #include <asm/fsl_liodn.h>
  20 #include <fm_eth.h>
  21 #include <hwconfig.h>
  22 #include "../common/qixis.h"
  23 #include "t102xqds.h"
  24 #include "t102xqds_qixis.h"
  25 #include "../common/sleep.h"
  26
  27 DECLARE_GLOBAL_DATA_PTR;
  28
  29 int checkboard(void)
  30 {
  31         char buf[64];
  32         struct cpu_type *cpu = gd->arch.cpu;
  33         static const char *const freq[] = {"100", "125", "156.25", "100.0"};
  34         int clock;
  35         u8 sw = QIXIS_READ(arch);
  36
  37         printf("Board: %sQDS, ", cpu->name);
  38         printf("Sys ID: 0x%02x, Board Arch: V%d, ", QIXIS_READ(id), sw >> 4);
  39         printf("Board Version: %c, boot from ", (sw & 0xf) + 'A' - 1);
  40
  41 #ifdef CONFIG_SDCARD
  42         puts("SD/MMC\n");
  43 #elif CONFIG_SPIFLASH
  44         puts("SPI\n");
  45 #else
  46         sw = QIXIS_READ(brdcfg[0]);
  47         sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
  48
  49         if (sw < 0x8)
  50                 printf("vBank: %d\n", sw);
  51         else if (sw == 0x8)
  52                 puts("PromJet\n");
  53         else if (sw == 0x9)
  54                 puts("NAND\n");
  55         else if (sw == 0x15)
  56                 printf("IFC Card\n");
  57         else
  58                 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
  59 #endif
  60
  61         printf("FPGA: v%d (%s), build %d",
  62                (int)QIXIS_READ(scver), qixis_read_tag(buf),
  63                (int)qixis_read_minor());
  64         /* the timestamp string contains "\n" at the end */
  65         printf(" on %s", qixis_read_time(buf));
  66
  67         puts("SERDES Reference: ");
  68         sw = QIXIS_READ(brdcfg[2]);
  69         clock = (sw >> 6) & 3;
  70         printf("Clock1=%sMHz ", freq[clock]);
  71         clock = (sw >> 4) & 3;
  72         printf("Clock2=%sMHz\n", freq[clock]);
  73
  74         return 0;
  75 }
  76
  77 int select_i2c_ch_pca9547(u8 ch)
  78 {
  79         int ret;
  80
  81         ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
  82         if (ret) {
  83                 puts("PCA: failed to select proper channel\n");
  84                 return ret;
  85         }
  86
  87         return 0;
  88 }
  89
  90 static int board_mux_lane_to_slot(void)
  91 {
  92         ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  93         u32 srds_prtcl_s1;
  94         u8 brdcfg9;
  95
  96         srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
  97                                 FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
  98         srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
  99
 100
 101         brdcfg9 = QIXIS_READ(brdcfg[9]);
 102         QIXIS_WRITE(brdcfg[9], brdcfg9 | BRDCFG9_XFI_TX_DISABLE);
 103
 104         switch (srds_prtcl_s1) {
 105         case 0:
 106                 /* SerDes1 is not enabled */
 107                 break;
 108         case 0xd5:
 109         case 0x5b:
 110         case 0x6b:
 111         case 0x77:
 112         case 0x6f:
 113         case 0x7f:
 114                 QIXIS_WRITE(brdcfg[12], 0x8c);
 115                 break;
 116         case 0x40:
 117                 QIXIS_WRITE(brdcfg[12], 0xfc);
 118                 break;
 119         case 0xd6:
 120         case 0x5a:
 121         case 0x6a:
 122         case 0x56:
 123                 QIXIS_WRITE(brdcfg[12], 0x88);
 124                 break;
 125         case 0x47:
 126                 QIXIS_WRITE(brdcfg[12], 0xcc);
 127                 break;
 128         case 0x46:
 129                 QIXIS_WRITE(brdcfg[12], 0xc8);
 130                 break;
 131         case 0x95:
 132         case 0x99:
 133                 brdcfg9 &= ~BRDCFG9_XFI_TX_DISABLE;
 134                 QIXIS_WRITE(brdcfg[9], brdcfg9);
 135                 QIXIS_WRITE(brdcfg[12], 0x8c);
 136                 break;
 137         case 0x116:
 138                 QIXIS_WRITE(brdcfg[12], 0x00);
 139                 break;
 140         case 0x115:
 141         case 0x119:
 142         case 0x129:
 143         case 0x12b:
 144                 /* Aurora, PCIe, SGMII, SATA */
 145                 QIXIS_WRITE(brdcfg[12], 0x04);
 146                 break;
 147         default:
 148                 printf("WARNING: unsupported for SerDes Protocol %d\n",
 149                        srds_prtcl_s1);
 150                 return -1;
 151         }
 152
 153         return 0;
 154 }
 155
 156 #ifdef CONFIG_PPC_T1024
 157 static void board_mux_setup(void)
 158 {
 159         u8 brdcfg15;
 160
 161         brdcfg15 = QIXIS_READ(brdcfg[15]);
 162         brdcfg15 &= ~BRDCFG15_DIUSEL_MASK;
 163
 164         if (hwconfig_arg_cmp("pin_mux", "tdm")) {
 165                 /* Route QE_TDM multiplexed signals to TDM Riser slot */
 166                 QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_DIUSEL_TDM);
 167                 QIXIS_WRITE(brdcfg[13], BRDCFG13_TDM_INTERFACE << 2);
 168                 QIXIS_WRITE(brdcfg[5], (QIXIS_READ(brdcfg[5]) &
 169                             ~BRDCFG5_SPIRTE_MASK) | BRDCFG5_SPIRTE_TDM);
 170         } else if (hwconfig_arg_cmp("pin_mux", "ucc")) {
 171                 /* to UCC (ProfiBus) interface */
 172                 QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_DIUSEL_UCC);
 173         } else if (hwconfig_arg_cmp("pin_mux", "hdmi")) {
 174                 /* to DVI (HDMI) encoder */
 175                 QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_DIUSEL_HDMI);
 176         } else if (hwconfig_arg_cmp("pin_mux", "lcd")) {
 177                 /* to DFP (LCD) encoder */
 178                 QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_LCDFM |
 179                             BRDCFG15_LCDPD | BRDCFG15_DIUSEL_LCD);
 180         }
 181
 182         if (hwconfig_arg_cmp("adaptor", "sdxc"))
 183                 /* Route SPI_CS multiplexed signals to SD slot */
 184                 QIXIS_WRITE(brdcfg[5], (QIXIS_READ(brdcfg[5]) &
 185                             ~BRDCFG5_SPIRTE_MASK) | BRDCFG5_SPIRTE_SDHC);
 186 }
 187 #endif
 188
 189 void board_retimer_ds125df111_init(void)
 190 {
 191         u8 reg;
 192
 193         /* Retimer DS125DF111 is connected to I2C1_CH7_CH5 */
 194         reg = I2C_MUX_CH7;
 195         i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &reg, 1);
 196         reg = I2C_MUX_CH5;
 197         i2c_write(I2C_MUX_PCA_ADDR_SEC, 0, 1, &reg, 1);
 198
 199         /* Access to Control/Shared register */
 200         reg = 0x0;
 201         i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
 202
 203         /* Read device revision and ID */
 204         i2c_read(I2C_RETIMER_ADDR, 1, 1, &reg, 1);
 205         debug("Retimer version id = 0x%x\n", reg);
 206
 207         /* Enable Broadcast */
 208         reg = 0x0c;
 209         i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
 210
 211         /* Reset Channel Registers */
 212         i2c_read(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
 213         reg |= 0x4;
 214         i2c_write(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
 215
 216         /* Enable override divider select and Enable Override Output Mux */
 217         i2c_read(I2C_RETIMER_ADDR, 9, 1, &reg, 1);
 218         reg |= 0x24;
 219         i2c_write(I2C_RETIMER_ADDR, 9, 1, &reg, 1);
 220
 221         /* Select VCO Divider to full rate (000) */
 222         i2c_read(I2C_RETIMER_ADDR, 0x18, 1, &reg, 1);
 223         reg &= 0x8f;
 224         i2c_write(I2C_RETIMER_ADDR, 0x18, 1, &reg, 1);
 225
 226         /* Select active PFD MUX input as re-timed data (001) */
 227         i2c_read(I2C_RETIMER_ADDR, 0x1e, 1, &reg, 1);
 228         reg &= 0x3f;
 229         reg |= 0x20;
 230         i2c_write(I2C_RETIMER_ADDR, 0x1e, 1, &reg, 1);
 231
 232         /* Set data rate as 10.3125 Gbps */
 233         reg = 0x0;
 234         i2c_write(I2C_RETIMER_ADDR, 0x60, 1, &reg, 1);
 235         reg = 0xb2;
 236         i2c_write(I2C_RETIMER_ADDR, 0x61, 1, &reg, 1);
 237         reg = 0x90;
 238         i2c_write(I2C_RETIMER_ADDR, 0x62, 1, &reg, 1);
 239         reg = 0xb3;
 240         i2c_write(I2C_RETIMER_ADDR, 0x63, 1, &reg, 1);
 241         reg = 0xcd;
 242         i2c_write(I2C_RETIMER_ADDR, 0x64, 1, &reg, 1);
 243 }
 244
 245 int board_early_init_f(void)
 246 {
 247 #if defined(CONFIG_DEEP_SLEEP)
 248         if (is_warm_boot())
 249                 fsl_dp_disable_console();
 250 #endif
 251
 252         return 0;
 253 }
 254
 255 int board_early_init_r(void)
 256 {
 257 #ifdef CONFIG_SYS_FLASH_BASE
 258         const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
 259         int flash_esel = find_tlb_idx((void *)flashbase, 1);
 260
 261         /*
 262          * Remap Boot flash + PROMJET region to caching-inhibited
 263          * so that flash can be erased properly.
 264          */
 265
 266         /* Flush d-cache and invalidate i-cache of any FLASH data */
 267         flush_dcache();
 268         invalidate_icache();
 269
 270         if (flash_esel == -1) {
 271                 /* very unlikely unless something is messed up */
 272                 puts("Error: Could not find TLB for FLASH BASE\n");
 273                 flash_esel = 2; /* give our best effort to continue */
 274         } else {
 275                 /* invalidate existing TLB entry for flash + promjet */
 276                 disable_tlb(flash_esel);
 277         }
 278
 279         set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
 280                 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 281                 0, flash_esel, BOOKE_PAGESZ_256M, 1);
 282 #endif
 283         set_liodns();
 284 #ifdef CONFIG_SYS_DPAA_QBMAN
 285         setup_portals();
 286 #endif
 287         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 288         board_mux_lane_to_slot();
 289         board_retimer_ds125df111_init();
 290
 291         /* Increase IO drive strength to address FCS error on RGMII */
 292         out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_IODSECR1_ADDR, 0xbfdb7800);
 293
 294         return 0;
 295 }
 296
 297 unsigned long get_board_sys_clk(void)
 298 {
 299         u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
 300
 301         switch (sysclk_conf & 0x0F) {
 302         case QIXIS_SYSCLK_64:
 303                 return 64000000;
 304         case QIXIS_SYSCLK_83:
 305                 return 83333333;
 306         case QIXIS_SYSCLK_100:
 307                 return 100000000;
 308         case QIXIS_SYSCLK_125:
 309                 return 125000000;
 310         case QIXIS_SYSCLK_133:
 311                 return 133333333;
 312         case QIXIS_SYSCLK_150:
 313                 return 150000000;
 314         case QIXIS_SYSCLK_160:
 315                 return 160000000;
 316         case QIXIS_SYSCLK_166:
 317                 return 166666666;
 318         }
 319         return 66666666;
 320 }
 321
 322 unsigned long get_board_ddr_clk(void)
 323 {
 324         u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
 325
 326         switch ((ddrclk_conf & 0x30) >> 4) {
 327         case QIXIS_DDRCLK_100:
 328                 return 100000000;
 329         case QIXIS_DDRCLK_125:
 330                 return 125000000;
 331         case QIXIS_DDRCLK_133:
 332                 return 133333333;
 333         }
 334         return 66666666;
 335 }
 336
 337 #define NUM_SRDS_PLL    2
 338 int misc_init_r(void)
 339 {
 340 #ifdef CONFIG_PPC_T1024
 341         board_mux_setup();
 342 #endif
 343         return 0;
 344 }
 345
 346 void fdt_fixup_spi_mux(void *blob)
 347 {
 348         int nodeoff = 0;
 349
 350         if (hwconfig_arg_cmp("pin_mux", "tdm")) {
 351                 while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
 352                         "eon,en25s64")) >= 0) {
 353                         fdt_del_node(blob, nodeoff);
 354                 }
 355         } else {
 356                 /* remove tdm node */
 357                 while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
 358                         "maxim,ds26522")) >= 0) {
 359                         fdt_del_node(blob, nodeoff);
 360                 }
 361         }
 362 }
 363
 364 int ft_board_setup(void *blob, bd_t *bd)
 365 {
 366         phys_addr_t base;
 367         phys_size_t size;
 368
 369         ft_cpu_setup(blob, bd);
 370
 371         base = getenv_bootm_low();
 372         size = getenv_bootm_size();
 373
 374         fdt_fixup_memory(blob, (u64)base, (u64)size);
 375
 376 #ifdef CONFIG_PCI
 377         pci_of_setup(blob, bd);
 378 #endif
 379
 380         fdt_fixup_liodn(blob);
 381
 382 #ifdef CONFIG_HAS_FSL_DR_USB
 383         fdt_fixup_dr_usb(blob, bd);
 384 #endif
 385
 386 #ifdef CONFIG_SYS_DPAA_FMAN
 387         fdt_fixup_fman_ethernet(blob);
 388         fdt_fixup_board_enet(blob);
 389 #endif
 390         fdt_fixup_spi_mux(blob);
 391
 392         return 0;
 393 }
 394
 395 void qixis_dump_switch(void)
 396 {
 397         int i, nr_of_cfgsw;
 398
 399         QIXIS_WRITE(cms[0], 0x00);
 400         nr_of_cfgsw = QIXIS_READ(cms[1]);
 401
 402         puts("DIP switch settings dump:\n");
 403         for (i = 1; i <= nr_of_cfgsw; i++) {
 404                 QIXIS_WRITE(cms[0], i);
 405                 printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
 406         }
 407 }