arch/arm/mach-stm32mp/bsec.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
   4  */
   5
   6 #define LOG_CATEGORY UCLASS_MISC
   7
   8 #include <common.h>
   9 #include <clk.h>
  10 #include <dm.h>
  11 #include <log.h>
  12 #include <misc.h>
  13 #include <asm/io.h>
  14 #include <asm/arch/bsec.h>
  15 #include <asm/arch/stm32mp1_smc.h>
  16 #include <dm/device_compat.h>
  17 #include <linux/arm-smccc.h>
  18 #include <linux/iopoll.h>
  19
  20 #define BSEC_OTP_MAX_VALUE              95
  21 #define BSEC_OTP_UPPER_START            32
  22 #define BSEC_TIMEOUT_US                 10000
  23
  24 /* BSEC REGISTER OFFSET (base relative) */
  25 #define BSEC_OTP_CONF_OFF               0x000
  26 #define BSEC_OTP_CTRL_OFF               0x004
  27 #define BSEC_OTP_WRDATA_OFF             0x008
  28 #define BSEC_OTP_STATUS_OFF             0x00C
  29 #define BSEC_OTP_LOCK_OFF               0x010
  30 #define BSEC_DENABLE_OFF                0x014
  31 #define BSEC_DISTURBED_OFF              0x01C
  32 #define BSEC_ERROR_OFF                  0x034
  33 #define BSEC_WRLOCK_OFF                 0x04C /* OTP write permananet lock */
  34 #define BSEC_SPLOCK_OFF                 0x064 /* OTP write sticky lock */
  35 #define BSEC_SWLOCK_OFF                 0x07C /* shadow write sticky lock */
  36 #define BSEC_SRLOCK_OFF                 0x094 /* shadow read sticky lock */
  37 #define BSEC_OTP_DATA_OFF               0x200
  38
  39 /* BSEC_CONFIGURATION Register MASK */
  40 #define BSEC_CONF_POWER_UP              0x001
  41
  42 /* BSEC_CONTROL Register */
  43 #define BSEC_READ                       0x000
  44 #define BSEC_WRITE                      0x100
  45 #define BSEC_LOCK                       0x200
  46
  47 /* LOCK Register */
  48 #define OTP_LOCK_MASK                   0x1F
  49 #define OTP_LOCK_BANK_SHIFT             0x05
  50 #define OTP_LOCK_BIT_MASK               0x01
  51
  52 /* STATUS Register */
  53 #define BSEC_MODE_BUSY_MASK             0x08
  54 #define BSEC_MODE_PROGFAIL_MASK         0x10
  55 #define BSEC_MODE_PWR_MASK              0x20
  56
  57 /* DENABLE Register */
  58 #define BSEC_DENABLE_DBGSWENABLE        BIT(10)
  59
  60 /*
  61  * OTP Lock services definition
  62  * Value must corresponding to the bit number in the register
  63  */
  64 #define BSEC_LOCK_PROGRAM               0x04
  65
  66 /*
  67  * OTP status: bit 0 permanent lock
  68  */
  69 #define BSEC_LOCK_PERM                  BIT(0)
  70
  71 /**
  72  * bsec_lock() - manage lock for each type SR/SP/SW
  73  * @address: address of bsec IP register
  74  * @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
  75  * Return: true if locked else false
  76  */
  77 static bool bsec_read_lock(u32 address, u32 otp)
  78 {
  79         u32 bit;
  80         u32 bank;
  81
  82         bit = 1 << (otp & OTP_LOCK_MASK);
  83         bank = ((otp >> OTP_LOCK_BANK_SHIFT) & OTP_LOCK_MASK) * sizeof(u32);
  84
  85         return !!(readl(address + bank) & bit);
  86 }
  87
  88 /**
  89  * bsec_check_error() - Check status of one otp
  90  * @base: base address of bsec IP
  91  * @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
  92  * Return: 0 if no error, -EAGAIN or -ENOTSUPP
  93  */
  94 static u32 bsec_check_error(u32 base, u32 otp)
  95 {
  96         u32 bit;
  97         u32 bank;
  98
  99         bit = 1 << (otp & OTP_LOCK_MASK);
 100         bank = ((otp >> OTP_LOCK_BANK_SHIFT) & OTP_LOCK_MASK) * sizeof(u32);
 101
 102         if (readl(base + BSEC_DISTURBED_OFF + bank) & bit)
 103                 return -EAGAIN;
 104         else if (readl(base + BSEC_ERROR_OFF + bank) & bit)
 105                 return -ENOTSUPP;
 106
 107         return 0;
 108 }
 109
 110 /**
 111  * bsec_read_SR_lock() - read SR lock (Shadowing)
 112  * @base: base address of bsec IP
 113  * @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
 114  * Return: true if locked else false
 115  */
 116 static bool bsec_read_SR_lock(u32 base, u32 otp)
 117 {
 118         return bsec_read_lock(base + BSEC_SRLOCK_OFF, otp);
 119 }
 120
 121 /**
 122  * bsec_read_SP_lock() - read SP lock (program Lock)
 123  * @base: base address of bsec IP
 124  * @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
 125  * Return: true if locked else false
 126  */
 127 static bool bsec_read_SP_lock(u32 base, u32 otp)
 128 {
 129         return bsec_read_lock(base + BSEC_SPLOCK_OFF, otp);
 130 }
 131
 132 /**
 133  * bsec_SW_lock() - manage SW lock (Write in Shadow)
 134  * @base: base address of bsec IP
 135  * @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
 136  * Return: true if locked else false
 137  */
 138 static bool bsec_read_SW_lock(u32 base, u32 otp)
 139 {
 140         return bsec_read_lock(base + BSEC_SWLOCK_OFF, otp);
 141 }
 142
 143 /**
 144  * bsec_power_safmem() - Activate or deactivate safmem power
 145  * @base: base address of bsec IP
 146  * @power: true to power up , false to power down
 147  * Return: 0 if succeed
 148  */
 149 static int bsec_power_safmem(u32 base, bool power)
 150 {
 151         u32 val;
 152         u32 mask;
 153
 154         if (power) {
 155                 setbits_le32(base + BSEC_OTP_CONF_OFF, BSEC_CONF_POWER_UP);
 156                 mask = BSEC_MODE_PWR_MASK;
 157         } else {
 158                 clrbits_le32(base + BSEC_OTP_CONF_OFF, BSEC_CONF_POWER_UP);
 159                 mask = 0;
 160         }
 161
 162         /* waiting loop */
 163         return readl_poll_timeout(base + BSEC_OTP_STATUS_OFF,
 164                                   val, (val & BSEC_MODE_PWR_MASK) == mask,
 165                                   BSEC_TIMEOUT_US);
 166 }
 167
 168 /**
 169  * bsec_shadow_register() - copy safmen otp to bsec data
 170  * @dev: bsec IP device
 171  * @base: base address of bsec IP
 172  * @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
 173  * Return: 0 if no error
 174  */
 175 static int bsec_shadow_register(struct udevice *dev, u32 base, u32 otp)
 176 {
 177         u32 val;
 178         int ret;
 179         bool power_up = false;
 180
 181         /* check if shadowing of otp is locked */
 182         if (bsec_read_SR_lock(base, otp))
 183                 dev_dbg(dev, "OTP %d is locked and refreshed with 0\n",
 184                         otp);
 185
 186         /* check if safemem is power up */
 187         val = readl(base + BSEC_OTP_STATUS_OFF);
 188         if (!(val & BSEC_MODE_PWR_MASK)) {
 189                 ret = bsec_power_safmem(base, true);
 190                 if (ret)
 191                         return ret;
 192                 power_up = true;
 193         }
 194         /* set BSEC_OTP_CTRL_OFF with the otp value*/
 195         writel(otp | BSEC_READ, base + BSEC_OTP_CTRL_OFF);
 196
 197         /* check otp status*/
 198         ret = readl_poll_timeout(base + BSEC_OTP_STATUS_OFF,
 199                                  val, (val & BSEC_MODE_BUSY_MASK) == 0,
 200                                  BSEC_TIMEOUT_US);
 201         if (ret)
 202                 return ret;
 203
 204         ret = bsec_check_error(base, otp);
 205
 206         if (power_up)
 207                 bsec_power_safmem(base, false);
 208
 209         return ret;
 210 }
 211
 212 /**
 213  * bsec_read_shadow() - read an otp data value from shadow
 214  * @dev: bsec IP device
 215  * @base: base address of bsec IP
 216  * @val: read value
 217  * @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
 218  * Return: 0 if no error
 219  */
 220 static int bsec_read_shadow(struct udevice *dev, u32 base, u32 *val, u32 otp)
 221 {
 222         *val = readl(base + BSEC_OTP_DATA_OFF + otp * sizeof(u32));
 223
 224         return bsec_check_error(base, otp);
 225 }
 226
 227 /**
 228  * bsec_write_shadow() - write value in BSEC data register in shadow
 229  * @dev: bsec IP device
 230  * @base: base address of bsec IP
 231  * @val: value to write
 232  * @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
 233  * Return: 0 if no error
 234  */
 235 static int bsec_write_shadow(struct udevice *dev, u32 base, u32 val, u32 otp)
 236 {
 237         /* check if programming of otp is locked */
 238         if (bsec_read_SW_lock(base, otp))
 239                 dev_dbg(dev, "OTP %d is lock, write will be ignore\n", otp);
 240
 241         writel(val, base + BSEC_OTP_DATA_OFF + otp * sizeof(u32));
 242
 243         return bsec_check_error(base, otp);
 244 }
 245
 246 /**
 247  * bsec_program_otp() - program a bit in SAFMEM
 248  * @dev: bsec IP device
 249  * @base: base address of bsec IP
 250  * @val: value to program
 251  * @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
 252  * after the function the otp data is not refreshed in shadow
 253  * Return: 0 if no error
 254  */
 255 static int bsec_program_otp(struct udevice *dev, long base, u32 val, u32 otp)
 256 {
 257         u32 ret;
 258         bool power_up = false;
 259
 260         if (bsec_read_SP_lock(base, otp))
 261                 dev_dbg(dev, "OTP %d locked, prog will be ignore\n", otp);
 262
 263         if (readl(base + BSEC_OTP_LOCK_OFF) & (1 << BSEC_LOCK_PROGRAM))
 264                 dev_dbg(dev, "Global lock, prog will be ignore\n");
 265
 266         /* check if safemem is power up */
 267         if (!(readl(base + BSEC_OTP_STATUS_OFF) & BSEC_MODE_PWR_MASK)) {
 268                 ret = bsec_power_safmem(base, true);
 269                 if (ret)
 270                         return ret;
 271
 272                 power_up = true;
 273         }
 274         /* set value in write register*/
 275         writel(val, base + BSEC_OTP_WRDATA_OFF);
 276
 277         /* set BSEC_OTP_CTRL_OFF with the otp value */
 278         writel(otp | BSEC_WRITE, base + BSEC_OTP_CTRL_OFF);
 279
 280         /* check otp status*/
 281         ret = readl_poll_timeout(base + BSEC_OTP_STATUS_OFF,
 282                                  val, (val & BSEC_MODE_BUSY_MASK) == 0,
 283                                  BSEC_TIMEOUT_US);
 284         if (ret)
 285                 return ret;
 286
 287         if (val & BSEC_MODE_PROGFAIL_MASK)
 288                 ret = -EACCES;
 289         else
 290                 ret = bsec_check_error(base, otp);
 291
 292         if (power_up)
 293                 bsec_power_safmem(base, false);
 294
 295         return ret;
 296 }
 297
 298 /**
 299  * bsec_permanent_lock_otp() - permanent lock of OTP in SAFMEM
 300  * @dev: bsec IP device
 301  * @base: base address of bsec IP
 302  * @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
 303  * Return: 0 if no error
 304  */
 305 static int bsec_permanent_lock_otp(struct udevice *dev, long base, uint32_t otp)
 306 {
 307         int ret;
 308         bool power_up = false;
 309         u32 val, addr;
 310
 311         /* check if safemem is power up */
 312         if (!(readl(base + BSEC_OTP_STATUS_OFF) & BSEC_MODE_PWR_MASK)) {
 313                 ret = bsec_power_safmem(base, true);
 314                 if (ret)
 315                         return ret;
 316
 317                 power_up = true;
 318         }
 319
 320         /*
 321          * low OTPs = 2 bits word for low OTPs, 1 bits per word for upper OTP
 322          * and only 16 bits used in WRDATA
 323          */
 324         if (otp < BSEC_OTP_UPPER_START) {
 325                 addr = otp / 8;
 326                 val = 0x03 << ((otp * 2) & 0xF);
 327         } else {
 328                 addr = BSEC_OTP_UPPER_START / 8 +
 329                        ((otp - BSEC_OTP_UPPER_START) / 16);
 330                 val = 0x01 << (otp & 0xF);
 331         }
 332
 333         /* set value in write register*/
 334         writel(val, base + BSEC_OTP_WRDATA_OFF);
 335
 336         /* set BSEC_OTP_CTRL_OFF with the otp addr and lock request*/
 337         writel(addr | BSEC_WRITE | BSEC_LOCK, base + BSEC_OTP_CTRL_OFF);
 338
 339         /* check otp status*/
 340         ret = readl_poll_timeout(base + BSEC_OTP_STATUS_OFF,
 341                                  val, (val & BSEC_MODE_BUSY_MASK) == 0,
 342                                  BSEC_TIMEOUT_US);
 343         if (ret)
 344                 return ret;
 345
 346         if (val & BSEC_MODE_PROGFAIL_MASK)
 347                 ret = -EACCES;
 348         else
 349                 ret = bsec_check_error(base, otp);
 350
 351         if (power_up)
 352                 bsec_power_safmem(base, false);
 353
 354         return ret;
 355 }
 356
 357 /* BSEC MISC driver *******************************************************/
 358 struct stm32mp_bsec_plat {
 359         u32 base;
 360 };
 361
 362 static int stm32mp_bsec_read_otp(struct udevice *dev, u32 *val, u32 otp)
 363 {
 364         struct stm32mp_bsec_plat *plat;
 365         u32 tmp_data = 0;
 366         int ret;
 367
 368         if (IS_ENABLED(CONFIG_ARM_SMCCC) && !IS_ENABLED(CONFIG_SPL_BUILD))
 369                 return stm32_smc(STM32_SMC_BSEC,
 370                                  STM32_SMC_READ_OTP,
 371                                  otp, 0, val);
 372
 373         plat = dev_get_plat(dev);
 374
 375         /* read current shadow value */
 376         ret = bsec_read_shadow(dev, plat->base, &tmp_data, otp);
 377         if (ret)
 378                 return ret;
 379
 380         /* copy otp in shadow */
 381         ret = bsec_shadow_register(dev, plat->base, otp);
 382         if (ret)
 383                 return ret;
 384
 385         ret = bsec_read_shadow(dev, plat->base, val, otp);
 386         if (ret)
 387                 return ret;
 388
 389         /* restore shadow value */
 390         ret = bsec_write_shadow(dev, plat->base, tmp_data, otp);
 391
 392         return ret;
 393 }
 394
 395 static int stm32mp_bsec_read_shadow(struct udevice *dev, u32 *val, u32 otp)
 396 {
 397         struct stm32mp_bsec_plat *plat;
 398
 399         if (IS_ENABLED(CONFIG_ARM_SMCCC) && !IS_ENABLED(CONFIG_SPL_BUILD))
 400                 return stm32_smc(STM32_SMC_BSEC,
 401                                  STM32_SMC_READ_SHADOW,
 402                                  otp, 0, val);
 403
 404         plat = dev_get_plat(dev);
 405
 406         return bsec_read_shadow(dev, plat->base, val, otp);
 407 }
 408
 409 static int stm32mp_bsec_read_lock(struct udevice *dev, u32 *val, u32 otp)
 410 {
 411         struct stm32mp_bsec_plat *plat = dev_get_plat(dev);
 412         u32 wrlock;
 413
 414         /* return OTP permanent write lock status */
 415         wrlock = bsec_read_lock(plat->base + BSEC_WRLOCK_OFF, otp);
 416
 417         *val = 0;
 418         if (wrlock)
 419                 *val = BSEC_LOCK_PERM;
 420
 421         return 0;
 422 }
 423
 424 static int stm32mp_bsec_write_otp(struct udevice *dev, u32 val, u32 otp)
 425 {
 426         struct stm32mp_bsec_plat *plat;
 427
 428         if (IS_ENABLED(CONFIG_ARM_SMCCC) && !IS_ENABLED(CONFIG_SPL_BUILD))
 429                 return stm32_smc_exec(STM32_SMC_BSEC,
 430                                       STM32_SMC_PROG_OTP,
 431                                       otp, val);
 432
 433         plat = dev_get_plat(dev);
 434
 435         return bsec_program_otp(dev, plat->base, val, otp);
 436
 437 }
 438
 439 static int stm32mp_bsec_write_shadow(struct udevice *dev, u32 val, u32 otp)
 440 {
 441         struct stm32mp_bsec_plat *plat;
 442
 443         if (IS_ENABLED(CONFIG_ARM_SMCCC) && !IS_ENABLED(CONFIG_SPL_BUILD))
 444                 return stm32_smc_exec(STM32_SMC_BSEC,
 445                                       STM32_SMC_WRITE_SHADOW,
 446                                       otp, val);
 447
 448         plat = dev_get_plat(dev);
 449
 450         return bsec_write_shadow(dev, plat->base, val, otp);
 451 }
 452
 453 static int stm32mp_bsec_write_lock(struct udevice *dev, u32 val, u32 otp)
 454 {
 455         struct stm32mp_bsec_plat *plat;
 456
 457         /* only permanent write lock is supported in U-Boot */
 458         if (!(val & BSEC_LOCK_PERM)) {
 459                 dev_dbg(dev, "lock option without BSEC_LOCK_PERM: %x\n", val);
 460                 return 0; /* nothing to do */
 461         }
 462
 463         if (IS_ENABLED(CONFIG_ARM_SMCCC) && !IS_ENABLED(CONFIG_SPL_BUILD))
 464                 return stm32_smc_exec(STM32_SMC_BSEC,
 465                                       STM32_SMC_WRLOCK_OTP,
 466                                       otp, 0);
 467
 468         plat = dev_get_plat(dev);
 469
 470         return bsec_permanent_lock_otp(dev, plat->base, otp);
 471
 472         return -EINVAL;
 473 }
 474
 475 static int stm32mp_bsec_read(struct udevice *dev, int offset,
 476                              void *buf, int size)
 477 {
 478         int ret;
 479         int i;
 480         bool shadow = true, lock = false;
 481         int nb_otp = size / sizeof(u32);
 482         int otp;
 483         unsigned int offs = offset;
 484
 485         if (offs >= STM32_BSEC_LOCK_OFFSET) {
 486                 offs -= STM32_BSEC_LOCK_OFFSET;
 487                 lock = true;
 488         } else if (offs >= STM32_BSEC_OTP_OFFSET) {
 489                 offs -= STM32_BSEC_OTP_OFFSET;
 490                 shadow = false;
 491         }
 492
 493         if ((offs % 4) || (size % 4))
 494                 return -EINVAL;
 495
 496         otp = offs / sizeof(u32);
 497
 498         for (i = otp; i < (otp + nb_otp) && i <= BSEC_OTP_MAX_VALUE; i++) {
 499                 u32 *addr = &((u32 *)buf)[i - otp];
 500
 501                 if (lock)
 502                         ret = stm32mp_bsec_read_lock(dev, addr, i);
 503                 else if (shadow)
 504                         ret = stm32mp_bsec_read_shadow(dev, addr, i);
 505                 else
 506                         ret = stm32mp_bsec_read_otp(dev, addr, i);
 507
 508                 if (ret)
 509                         break;
 510         }
 511         if (ret)
 512                 return ret;
 513         else
 514                 return (i - otp) * 4;
 515 }
 516
 517 static int stm32mp_bsec_write(struct udevice *dev, int offset,
 518                               const void *buf, int size)
 519 {
 520         int ret = 0;
 521         int i;
 522         bool shadow = true, lock = false;
 523         int nb_otp = size / sizeof(u32);
 524         int otp;
 525         unsigned int offs = offset;
 526
 527         if (offs >= STM32_BSEC_LOCK_OFFSET) {
 528                 offs -= STM32_BSEC_LOCK_OFFSET;
 529                 lock = true;
 530         } else if (offs >= STM32_BSEC_OTP_OFFSET) {
 531                 offs -= STM32_BSEC_OTP_OFFSET;
 532                 shadow = false;
 533         }
 534
 535         if ((offs % 4) || (size % 4))
 536                 return -EINVAL;
 537
 538         otp = offs / sizeof(u32);
 539
 540         for (i = otp; i < otp + nb_otp && i <= BSEC_OTP_MAX_VALUE; i++) {
 541                 u32 *val = &((u32 *)buf)[i - otp];
 542
 543                 if (lock)
 544                         ret = stm32mp_bsec_write_lock(dev, *val, i);
 545                 else if (shadow)
 546                         ret = stm32mp_bsec_write_shadow(dev, *val, i);
 547                 else
 548                         ret = stm32mp_bsec_write_otp(dev, *val, i);
 549                 if (ret)
 550                         break;
 551         }
 552         if (ret)
 553                 return ret;
 554         else
 555                 return (i - otp) * 4;
 556 }
 557
 558 static const struct misc_ops stm32mp_bsec_ops = {
 559         .read = stm32mp_bsec_read,
 560         .write = stm32mp_bsec_write,
 561 };
 562
 563 static int stm32mp_bsec_of_to_plat(struct udevice *dev)
 564 {
 565         struct stm32mp_bsec_plat *plat = dev_get_plat(dev);
 566
 567         plat->base = (u32)dev_read_addr_ptr(dev);
 568
 569         return 0;
 570 }
 571
 572 static int stm32mp_bsec_probe(struct udevice *dev)
 573 {
 574         int otp;
 575         struct stm32mp_bsec_plat *plat;
 576         struct clk_bulk clk_bulk;
 577         int ret;
 578
 579         ret = clk_get_bulk(dev, &clk_bulk);
 580         if (!ret) {
 581                 ret = clk_enable_bulk(&clk_bulk);
 582                 if (ret)
 583                         return ret;
 584         }
 585
 586         /*
 587          * update unlocked shadow for OTP cleared by the rom code
 588          * only executed in SPL, it is done in TF-A for TFABOOT
 589          */
 590         if (IS_ENABLED(CONFIG_SPL_BUILD)) {
 591                 plat = dev_get_plat(dev);
 592
 593                 for (otp = 57; otp <= BSEC_OTP_MAX_VALUE; otp++)
 594                         if (!bsec_read_SR_lock(plat->base, otp))
 595                                 bsec_shadow_register(dev, plat->base, otp);
 596         }
 597
 598         return 0;
 599 }
 600
 601 static const struct udevice_id stm32mp_bsec_ids[] = {
 602         { .compatible = "st,stm32mp15-bsec" },
 603         {}
 604 };
 605
 606 U_BOOT_DRIVER(stm32mp_bsec) = {
 607         .name = "stm32mp_bsec",
 608         .id = UCLASS_MISC,
 609         .of_match = stm32mp_bsec_ids,
 610         .of_to_plat = stm32mp_bsec_of_to_plat,
 611         .plat_auto      = sizeof(struct stm32mp_bsec_plat),
 612         .ops = &stm32mp_bsec_ops,
 613         .probe = stm32mp_bsec_probe,
 614 };
 615
 616 bool bsec_dbgswenable(void)
 617 {
 618         struct udevice *dev;
 619         struct stm32mp_bsec_plat *plat;
 620         int ret;
 621
 622         ret = uclass_get_device_by_driver(UCLASS_MISC,
 623                                           DM_DRIVER_GET(stm32mp_bsec), &dev);
 624         if (ret || !dev) {
 625                 log_debug("bsec driver not available\n");
 626                 return false;
 627         }
 628
 629         plat = dev_get_plat(dev);
 630         if (readl(plat->base + BSEC_DENABLE_OFF) & BSEC_DENABLE_DBGSWENABLE)
 631                 return true;
 632
 633         return false;
 634 }