1 // SPDX-License-Identifier: GPL-2.0
3 * Xilinx pinctrl driver for ZynqMP
8 * Copyright (C) 2021 Xilinx, Inc. All rights reserved.
15 #include <zynqmp_firmware.h>
16 #include <asm/arch/sys_proto.h>
18 #include <dm/device_compat.h>
19 #include <dm/pinctrl.h>
20 #include <linux/compat.h>
21 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
23 #define PINCTRL_GET_FUNC_GROUPS_RESP_LEN 12
24 #define PINCTRL_GET_PIN_GROUPS_RESP_LEN 12
25 #define NUM_GROUPS_PER_RESP 6
27 #define RESERVED_GROUP -2
28 #define MAX_GROUP_PIN 50
29 #define MAX_PIN_GROUPS 50
30 #define MAX_GROUP_NAME_LEN 32
31 #define MAX_FUNC_NAME_LEN 16
33 #define DRIVE_STRENGTH_2MA 2
34 #define DRIVE_STRENGTH_4MA 4
35 #define DRIVE_STRENGTH_8MA 8
36 #define DRIVE_STRENGTH_12MA 12
39 * This driver works with very simple configuration that has the same name
40 * for group and function. This way it is compatible with the Linux Kernel
43 struct zynqmp_pinctrl_priv {
47 struct zynqmp_pmux_function *funcs;
48 struct zynqmp_pctrl_group *groups;
52 * struct zynqmp_pinctrl_config - pinconfig parameters
53 * @slew: Slew rate slow or fast
54 * @bias: Bias enabled or disabled
55 * @pull_ctrl: Pull control pull up or pull down
56 * @input_type: CMOS or Schmitt
57 * @drive_strength: Drive strength 2mA/4mA/8mA/12mA
58 * @volt_sts: Voltage status 1.8V or 3.3V
59 * @tri_state: Tristate enabled or disabled
61 * This structure holds information about pin control config
62 * option that can be set for each pin.
64 struct zynqmp_pinctrl_config {
75 * enum zynqmp_pin_config_param - possible pin configuration parameters
76 * @PIN_CFG_IOSTANDARD: if the pin can select an IO standard,
77 * the argument to this parameter (on a
78 * custom format) tells the driver which
79 * alternative IO standard to use
80 * @PIN_CONFIG_SCHMITTCMOS: this parameter (on a custom format) allows
81 * to select schmitt or cmos input for MIO pins
83 enum zynqmp_pin_config_param {
84 PIN_CFG_IOSTANDARD = PIN_CONFIG_END + 1,
85 PIN_CONFIG_SCHMITTCMOS,
89 * struct zynqmp_pmux_function - a pinmux function
90 * @name: Name of the pinmux function
91 * @groups: List of pingroups for this function
92 * @ngroups: Number of entries in @groups
94 * This structure holds information about pin control function
95 * and function group names supporting that function.
97 struct zynqmp_pmux_function {
98 char name[MAX_FUNC_NAME_LEN];
99 const char * const *groups;
100 unsigned int ngroups;
104 * struct zynqmp_pctrl_group - Pin control group info
106 * @pins: Group pin numbers
107 * @npins: Number of pins in group
109 struct zynqmp_pctrl_group {
111 unsigned int pins[MAX_GROUP_PIN];
115 static char pin_name[PINNAME_SIZE];
118 * zynqmp_pm_query_data() - Get query data from firmware
119 * @qid: Value of enum pm_query_id
122 * @out: Returned output value
124 * Return: Returns status, either success or error+reason
126 static int zynqmp_pm_query_data(enum pm_query_id qid, u32 arg1, u32 arg2, u32 *out)
129 u32 ret_payload[PAYLOAD_ARG_CNT];
131 ret = xilinx_pm_request(PM_QUERY_DATA, qid, arg1, arg2, 0, ret_payload);
135 *out = ret_payload[1];
140 static int zynqmp_pm_pinctrl_get_config(const u32 pin, const u32 param, u32 *value)
143 u32 ret_payload[PAYLOAD_ARG_CNT];
145 /* Get config for the pin */
146 ret = xilinx_pm_request(PM_PINCTRL_CONFIG_PARAM_GET, pin, param, 0, 0, ret_payload);
148 printf("%s failed\n", __func__);
152 *value = ret_payload[1];
157 static int zynqmp_pm_pinctrl_set_config(const u32 pin, const u32 param, u32 value)
161 /* Request the pin first */
162 ret = xilinx_pm_request(PM_PINCTRL_REQUEST, pin, 0, 0, 0, NULL);
164 printf("%s: pin request failed\n", __func__);
168 /* Set config for the pin */
169 ret = xilinx_pm_request(PM_PINCTRL_CONFIG_PARAM_SET, pin, param, value, 0, NULL);
171 printf("%s failed\n", __func__);
178 static int zynqmp_pinctrl_get_function_groups(u32 fid, u32 index, u16 *groups)
181 u32 ret_payload[PAYLOAD_ARG_CNT];
183 ret = xilinx_pm_request(PM_QUERY_DATA, PM_QID_PINCTRL_GET_FUNCTION_GROUPS,
184 fid, index, 0, ret_payload);
186 printf("%s failed\n", __func__);
190 memcpy(groups, &ret_payload[1], PINCTRL_GET_FUNC_GROUPS_RESP_LEN);
195 static int zynqmp_pinctrl_prepare_func_groups(u32 fid,
196 struct zynqmp_pmux_function *func,
197 struct zynqmp_pctrl_group *groups)
199 const char **fgroups;
200 char name[MAX_GROUP_NAME_LEN];
201 u16 resp[NUM_GROUPS_PER_RESP] = {0};
204 fgroups = kcalloc(func->ngroups, sizeof(*fgroups), GFP_KERNEL);
208 for (index = 0; index < func->ngroups; index += NUM_GROUPS_PER_RESP) {
209 ret = zynqmp_pinctrl_get_function_groups(fid, index, resp);
213 for (i = 0; i < NUM_GROUPS_PER_RESP; i++) {
214 if (resp[i] == (u16)NA_GROUP)
216 if (resp[i] == (u16)RESERVED_GROUP)
219 snprintf(name, MAX_GROUP_NAME_LEN, "%s_%d_grp",
220 func->name, index + i);
221 fgroups[index + i] = strdup(name);
223 snprintf(name, MAX_GROUP_NAME_LEN, "%s_%d_grp",
224 func->name, index + i);
225 groups[resp[i]].name = strdup(name);
229 func->groups = fgroups;
234 static int zynqmp_pinctrl_get_pin_groups(u32 pin, u32 index, u16 *groups)
237 u32 ret_payload[PAYLOAD_ARG_CNT];
239 ret = xilinx_pm_request(PM_QUERY_DATA, PM_QID_PINCTRL_GET_PIN_GROUPS,
240 pin, index, 0, ret_payload);
242 printf("%s failed to get pin groups\n", __func__);
246 memcpy(groups, &ret_payload[1], PINCTRL_GET_PIN_GROUPS_RESP_LEN);
251 static void zynqmp_pinctrl_group_add_pin(struct zynqmp_pctrl_group *group,
254 group->pins[group->npins++] = pin;
257 static int zynqmp_pinctrl_create_pin_groups(struct zynqmp_pctrl_group *groups,
260 u16 resp[NUM_GROUPS_PER_RESP] = {0};
261 int ret, i, index = 0;
264 ret = zynqmp_pinctrl_get_pin_groups(pin, index, resp);
268 for (i = 0; i < NUM_GROUPS_PER_RESP; i++) {
269 if (resp[i] == (u16)NA_GROUP)
271 if (resp[i] == (u16)RESERVED_GROUP)
273 zynqmp_pinctrl_group_add_pin(&groups[resp[i]], pin);
275 index += NUM_GROUPS_PER_RESP;
276 } while (index <= MAX_PIN_GROUPS);
282 static int zynqmp_pinctrl_probe(struct udevice *dev)
284 struct zynqmp_pinctrl_priv *priv = dev_get_priv(dev);
287 u32 ret_payload[PAYLOAD_ARG_CNT];
289 /* Get number of pins first */
290 ret = zynqmp_pm_query_data(PM_QID_PINCTRL_GET_NUM_PINS, 0, 0, &priv->npins);
292 printf("%s failed to get no of pins\n", __func__);
296 /* Get number of functions available */
297 ret = zynqmp_pm_query_data(PM_QID_PINCTRL_GET_NUM_FUNCTIONS, 0, 0, &priv->nfuncs);
299 printf("%s failed to get no of functions\n", __func__);
303 /* Allocating structures for functions and its groups */
304 priv->funcs = kzalloc(sizeof(*priv->funcs) * priv->nfuncs, GFP_KERNEL);
308 for (i = 0; i < priv->nfuncs; i++) {
309 /* Get function name for the function and fill */
310 xilinx_pm_request(PM_QUERY_DATA, PM_QID_PINCTRL_GET_FUNCTION_NAME,
311 i, 0, 0, ret_payload);
313 memcpy((void *)priv->funcs[i].name, ret_payload, MAX_FUNC_NAME_LEN);
315 /* And fill number of groups available for certain function */
316 xilinx_pm_request(PM_QUERY_DATA, PM_QID_PINCTRL_GET_NUM_FUNCTION_GROUPS,
317 i, 0, 0, ret_payload);
319 priv->funcs[i].ngroups = ret_payload[1];
320 priv->ngroups += priv->funcs[i].ngroups;
323 /* Prepare all groups */
324 priv->groups = kzalloc(sizeof(*priv->groups) * priv->ngroups,
329 for (i = 0; i < priv->nfuncs; i++) {
330 ret = zynqmp_pinctrl_prepare_func_groups(i, &priv->funcs[i],
333 printf("Failed to prepare_func_groups\n");
338 for (pin = 0; pin < priv->npins; pin++) {
339 ret = zynqmp_pinctrl_create_pin_groups(priv->groups, pin);
347 static int zynqmp_pinctrl_get_functions_count(struct udevice *dev)
349 struct zynqmp_pinctrl_priv *priv = dev_get_priv(dev);
354 static const char *zynqmp_pinctrl_get_function_name(struct udevice *dev,
355 unsigned int selector)
357 struct zynqmp_pinctrl_priv *priv = dev_get_priv(dev);
359 return priv->funcs[selector].name;
362 static int zynqmp_pinmux_set(struct udevice *dev, unsigned int selector,
363 unsigned int func_selector)
367 /* Request the pin first */
368 ret = xilinx_pm_request(PM_PINCTRL_REQUEST, selector, 0, 0, 0, NULL);
370 printf("%s: pin request failed\n", __func__);
374 /* Set the pin function */
375 ret = xilinx_pm_request(PM_PINCTRL_SET_FUNCTION, selector, func_selector,
378 printf("%s: Failed to set pinmux function\n", __func__);
385 static int zynqmp_pinmux_group_set(struct udevice *dev, unsigned int selector,
386 unsigned int func_selector)
389 struct zynqmp_pinctrl_priv *priv = dev_get_priv(dev);
390 const struct zynqmp_pctrl_group *pgrp = &priv->groups[selector];
392 for (i = 0; i < pgrp->npins; i++)
393 zynqmp_pinmux_set(dev, pgrp->pins[i], func_selector);
398 static int zynqmp_pinconf_set(struct udevice *dev, unsigned int pin,
399 unsigned int param, unsigned int arg)
405 case PIN_CONFIG_SLEW_RATE:
406 param = PM_PINCTRL_CONFIG_SLEW_RATE;
407 ret = zynqmp_pm_pinctrl_set_config(pin, param, arg);
409 case PIN_CONFIG_BIAS_PULL_UP:
410 param = PM_PINCTRL_CONFIG_PULL_CTRL;
411 arg = PM_PINCTRL_BIAS_PULL_UP;
412 ret = zynqmp_pm_pinctrl_set_config(pin, param, arg);
414 case PIN_CONFIG_BIAS_PULL_DOWN:
415 param = PM_PINCTRL_CONFIG_PULL_CTRL;
416 arg = PM_PINCTRL_BIAS_PULL_DOWN;
417 ret = zynqmp_pm_pinctrl_set_config(pin, param, arg);
419 case PIN_CONFIG_BIAS_DISABLE:
420 param = PM_PINCTRL_CONFIG_BIAS_STATUS;
421 arg = PM_PINCTRL_BIAS_DISABLE;
422 ret = zynqmp_pm_pinctrl_set_config(pin, param, arg);
424 case PIN_CONFIG_SCHMITTCMOS:
425 param = PM_PINCTRL_CONFIG_SCHMITT_CMOS;
426 ret = zynqmp_pm_pinctrl_set_config(pin, param, arg);
428 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
429 param = PM_PINCTRL_CONFIG_SCHMITT_CMOS;
430 ret = zynqmp_pm_pinctrl_set_config(pin, param, arg);
432 case PIN_CONFIG_DRIVE_STRENGTH:
434 case DRIVE_STRENGTH_2MA:
435 value = PM_PINCTRL_DRIVE_STRENGTH_2MA;
437 case DRIVE_STRENGTH_4MA:
438 value = PM_PINCTRL_DRIVE_STRENGTH_4MA;
440 case DRIVE_STRENGTH_8MA:
441 value = PM_PINCTRL_DRIVE_STRENGTH_8MA;
443 case DRIVE_STRENGTH_12MA:
444 value = PM_PINCTRL_DRIVE_STRENGTH_12MA;
447 /* Invalid drive strength */
448 dev_warn(dev, "Invalid drive strength for pin %d\n", pin);
452 param = PM_PINCTRL_CONFIG_DRIVE_STRENGTH;
453 ret = zynqmp_pm_pinctrl_set_config(pin, param, value);
455 case PIN_CFG_IOSTANDARD:
456 param = PM_PINCTRL_CONFIG_VOLTAGE_STATUS;
457 ret = zynqmp_pm_pinctrl_get_config(pin, param, &value);
459 dev_warn(dev, "Invalid IO Standard requested for pin %d\n",
462 case PIN_CONFIG_POWER_SOURCE:
463 param = PM_PINCTRL_CONFIG_VOLTAGE_STATUS;
464 ret = zynqmp_pm_pinctrl_get_config(pin, param, &value);
466 dev_warn(dev, "Invalid IO Standard requested for pin %d\n",
469 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
470 case PIN_CONFIG_LOW_POWER_MODE:
472 * This cases are mentioned in dts but configurable
473 * registers are unknown. So falling through to ignore
474 * boot time warnings as of now.
479 dev_warn(dev, "unsupported configuration parameter '%u'\n",
488 static int zynqmp_pinconf_group_set(struct udevice *dev,
489 unsigned int group_selector,
490 unsigned int param, unsigned int arg)
493 struct zynqmp_pinctrl_priv *priv = dev_get_priv(dev);
494 const struct zynqmp_pctrl_group *pgrp = &priv->groups[group_selector];
496 for (i = 0; i < pgrp->npins; i++)
497 zynqmp_pinconf_set(dev, pgrp->pins[i], param, arg);
502 static int zynqmp_pinctrl_get_pins_count(struct udevice *dev)
504 struct zynqmp_pinctrl_priv *priv = dev_get_priv(dev);
509 static const char *zynqmp_pinctrl_get_pin_name(struct udevice *dev,
510 unsigned int selector)
512 snprintf(pin_name, PINNAME_SIZE, "MIO%d", selector);
517 static int zynqmp_pinctrl_get_pin_muxing(struct udevice *dev,
518 unsigned int selector,
522 struct zynqmp_pinctrl_config pinmux;
524 zynqmp_pm_pinctrl_get_config(selector, PM_PINCTRL_CONFIG_SLEW_RATE,
526 zynqmp_pm_pinctrl_get_config(selector, PM_PINCTRL_CONFIG_BIAS_STATUS,
528 zynqmp_pm_pinctrl_get_config(selector, PM_PINCTRL_CONFIG_PULL_CTRL,
530 zynqmp_pm_pinctrl_get_config(selector, PM_PINCTRL_CONFIG_SCHMITT_CMOS,
532 zynqmp_pm_pinctrl_get_config(selector, PM_PINCTRL_CONFIG_DRIVE_STRENGTH,
533 &pinmux.drive_strength);
534 zynqmp_pm_pinctrl_get_config(selector, PM_PINCTRL_CONFIG_VOLTAGE_STATUS,
537 switch (pinmux.drive_strength) {
538 case PM_PINCTRL_DRIVE_STRENGTH_2MA:
539 pinmux.drive_strength = DRIVE_STRENGTH_2MA;
541 case PM_PINCTRL_DRIVE_STRENGTH_4MA:
542 pinmux.drive_strength = DRIVE_STRENGTH_4MA;
544 case PM_PINCTRL_DRIVE_STRENGTH_8MA:
545 pinmux.drive_strength = DRIVE_STRENGTH_8MA;
547 case PM_PINCTRL_DRIVE_STRENGTH_12MA:
548 pinmux.drive_strength = DRIVE_STRENGTH_12MA;
551 /* Invalid drive strength */
552 dev_warn(dev, "Invalid drive strength\n");
556 snprintf(buf, size, "slew:%s\tbias:%s\tpull:%s\tinput:%s\tdrive:%dmA\tvolt:%s",
557 pinmux.slew ? "slow" : "fast",
558 pinmux.bias ? "enabled" : "disabled",
559 pinmux.pull_ctrl ? "up" : "down",
560 pinmux.input_type ? "schmitt" : "cmos",
561 pinmux.drive_strength,
562 pinmux.volt_sts ? "1.8" : "3.3");
567 static int zynqmp_pinctrl_get_groups_count(struct udevice *dev)
569 struct zynqmp_pinctrl_priv *priv = dev_get_priv(dev);
571 return priv->ngroups;
574 static const char *zynqmp_pinctrl_get_group_name(struct udevice *dev,
575 unsigned int selector)
577 struct zynqmp_pinctrl_priv *priv = dev_get_priv(dev);
579 return priv->groups[selector].name;
582 static const struct pinconf_param zynqmp_conf_params[] = {
583 { "bias-bus-hold", PIN_CONFIG_BIAS_BUS_HOLD, 0 },
584 { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 },
585 { "bias-high-impedance", PIN_CONFIG_BIAS_HIGH_IMPEDANCE, 0 },
586 { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 },
587 { "bias-pull-pin-default", PIN_CONFIG_BIAS_PULL_PIN_DEFAULT, 1 },
588 { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 },
589 { "drive-open-drain", PIN_CONFIG_DRIVE_OPEN_DRAIN, 0 },
590 { "drive-open-source", PIN_CONFIG_DRIVE_OPEN_SOURCE, 0 },
591 { "drive-push-pull", PIN_CONFIG_DRIVE_PUSH_PULL, 0 },
592 { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 },
593 { "drive-strength-microamp", PIN_CONFIG_DRIVE_STRENGTH_UA, 0 },
594 { "input-debounce", PIN_CONFIG_INPUT_DEBOUNCE, 0 },
595 { "input-disable", PIN_CONFIG_INPUT_ENABLE, 0 },
596 { "input-enable", PIN_CONFIG_INPUT_ENABLE, 1 },
597 { "input-schmitt", PIN_CONFIG_INPUT_SCHMITT, 0 },
598 { "input-schmitt-disable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 0 },
599 { "input-schmitt-enable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 1 },
600 { "low-power-disable", PIN_CONFIG_LOW_POWER_MODE, 0 },
601 { "low-power-enable", PIN_CONFIG_LOW_POWER_MODE, 1 },
602 { "output-disable", PIN_CONFIG_OUTPUT_ENABLE, 0 },
603 { "output-enable", PIN_CONFIG_OUTPUT_ENABLE, 1 },
604 { "output-high", PIN_CONFIG_OUTPUT, 1, },
605 { "output-low", PIN_CONFIG_OUTPUT, 0, },
606 { "power-source", PIN_CONFIG_POWER_SOURCE, 0 },
607 { "sleep-hardware-state", PIN_CONFIG_SLEEP_HARDWARE_STATE, 0 },
608 { "slew-rate", PIN_CONFIG_SLEW_RATE, 0 },
609 { "skew-delay", PIN_CONFIG_SKEW_DELAY, 0 },
610 /* zynqmp specific */
611 {"io-standard", PIN_CFG_IOSTANDARD, IO_STANDARD_LVCMOS18},
612 {"schmitt-cmos", PIN_CONFIG_SCHMITTCMOS, PM_PINCTRL_INPUT_TYPE_SCHMITT},
615 static struct pinctrl_ops zynqmp_pinctrl_ops = {
616 .get_pins_count = zynqmp_pinctrl_get_pins_count,
617 .get_pin_name = zynqmp_pinctrl_get_pin_name,
618 .get_pin_muxing = zynqmp_pinctrl_get_pin_muxing,
619 .set_state = pinctrl_generic_set_state,
620 .get_groups_count = zynqmp_pinctrl_get_groups_count,
621 .get_group_name = zynqmp_pinctrl_get_group_name,
622 .get_functions_count = zynqmp_pinctrl_get_functions_count,
623 .get_function_name = zynqmp_pinctrl_get_function_name,
624 .pinmux_group_set = zynqmp_pinmux_group_set,
625 .pinmux_set = zynqmp_pinmux_set,
626 .pinconf_params = zynqmp_conf_params,
627 .pinconf_group_set = zynqmp_pinconf_group_set,
628 .pinconf_set = zynqmp_pinconf_set,
629 .pinconf_num_params = ARRAY_SIZE(zynqmp_conf_params),
632 static const struct udevice_id zynqmp_pinctrl_ids[] = {
633 { .compatible = "xlnx,zynqmp-pinctrl" },
637 U_BOOT_DRIVER(pinctrl_zynqmp) = {
638 .name = "zynqmp-pinctrl",
639 .id = UCLASS_PINCTRL,
640 .of_match = zynqmp_pinctrl_ids,
641 .priv_auto = sizeof(struct zynqmp_pinctrl_priv),
642 .ops = &zynqmp_pinctrl_ops,
643 .probe = zynqmp_pinctrl_probe,