1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
10 #include <asm/arch/stm32mp1_smc.h>
11 #include <linux/arm-smccc.h>
12 #include <linux/iopoll.h>
14 #define BSEC_OTP_MAX_VALUE 95
15 #define BSEC_TIMEOUT_US 10000
17 /* BSEC REGISTER OFFSET (base relative) */
18 #define BSEC_OTP_CONF_OFF 0x000
19 #define BSEC_OTP_CTRL_OFF 0x004
20 #define BSEC_OTP_WRDATA_OFF 0x008
21 #define BSEC_OTP_STATUS_OFF 0x00C
22 #define BSEC_OTP_LOCK_OFF 0x010
23 #define BSEC_DISTURBED_OFF 0x01C
24 #define BSEC_ERROR_OFF 0x034
25 #define BSEC_WRLOCK_OFF 0x04C /* OTP write permananet lock */
26 #define BSEC_SPLOCK_OFF 0x064 /* OTP write sticky lock */
27 #define BSEC_SWLOCK_OFF 0x07C /* shadow write sticky lock */
28 #define BSEC_SRLOCK_OFF 0x094 /* shadow read sticky lock */
29 #define BSEC_OTP_DATA_OFF 0x200
31 /* BSEC_CONFIGURATION Register MASK */
32 #define BSEC_CONF_POWER_UP 0x001
34 /* BSEC_CONTROL Register */
35 #define BSEC_READ 0x000
36 #define BSEC_WRITE 0x100
39 #define OTP_LOCK_MASK 0x1F
40 #define OTP_LOCK_BANK_SHIFT 0x05
41 #define OTP_LOCK_BIT_MASK 0x01
44 #define BSEC_MODE_BUSY_MASK 0x08
45 #define BSEC_MODE_PROGFAIL_MASK 0x10
46 #define BSEC_MODE_PWR_MASK 0x20
49 * OTP Lock services definition
50 * Value must corresponding to the bit number in the register
52 #define BSEC_LOCK_PROGRAM 0x04
55 * bsec_lock() - manage lock for each type SR/SP/SW
56 * @address: address of bsec IP register
57 * @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
58 * Return: true if locked else false
60 static bool bsec_read_lock(u32 address, u32 otp)
65 bit = 1 << (otp & OTP_LOCK_MASK);
66 bank = ((otp >> OTP_LOCK_BANK_SHIFT) & OTP_LOCK_MASK) * sizeof(u32);
68 return !!(readl(address + bank) & bit);
71 #ifndef CONFIG_TFABOOT
73 * bsec_check_error() - Check status of one otp
74 * @base: base address of bsec IP
75 * @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
76 * Return: 0 if no error, -EAGAIN or -ENOTSUPP
78 static u32 bsec_check_error(u32 base, u32 otp)
83 bit = 1 << (otp & OTP_LOCK_MASK);
84 bank = ((otp >> OTP_LOCK_BANK_SHIFT) & OTP_LOCK_MASK) * sizeof(u32);
86 if (readl(base + BSEC_DISTURBED_OFF + bank) & bit)
88 else if (readl(base + BSEC_ERROR_OFF + bank) & bit)
95 * bsec_read_SR_lock() - read SR lock (Shadowing)
96 * @base: base address of bsec IP
97 * @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
98 * Return: true if locked else false
100 static bool bsec_read_SR_lock(u32 base, u32 otp)
102 return bsec_read_lock(base + BSEC_SRLOCK_OFF, otp);
106 * bsec_read_SP_lock() - read SP lock (program Lock)
107 * @base: base address of bsec IP
108 * @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
109 * Return: true if locked else false
111 static bool bsec_read_SP_lock(u32 base, u32 otp)
113 return bsec_read_lock(base + BSEC_SPLOCK_OFF, otp);
117 * bsec_SW_lock() - manage SW lock (Write in Shadow)
118 * @base: base address of bsec IP
119 * @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
120 * Return: true if locked else false
122 static bool bsec_read_SW_lock(u32 base, u32 otp)
124 return bsec_read_lock(base + BSEC_SWLOCK_OFF, otp);
128 * bsec_power_safmem() - Activate or deactivate safmem power
129 * @base: base address of bsec IP
130 * @power: true to power up , false to power down
131 * Return: 0 if succeed
133 static int bsec_power_safmem(u32 base, bool power)
139 setbits_le32(base + BSEC_OTP_CONF_OFF, BSEC_CONF_POWER_UP);
140 mask = BSEC_MODE_PWR_MASK;
142 clrbits_le32(base + BSEC_OTP_CONF_OFF, BSEC_CONF_POWER_UP);
147 return readl_poll_timeout(base + BSEC_OTP_STATUS_OFF,
148 val, (val & BSEC_MODE_PWR_MASK) == mask,
153 * bsec_shadow_register() - copy safmen otp to bsec data
154 * @base: base address of bsec IP
155 * @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
156 * Return: 0 if no error
158 static int bsec_shadow_register(u32 base, u32 otp)
162 bool power_up = false;
164 /* check if shadowing of otp is locked */
165 if (bsec_read_SR_lock(base, otp))
166 pr_debug("bsec : OTP %d is locked and refreshed with 0\n", otp);
168 /* check if safemem is power up */
169 val = readl(base + BSEC_OTP_STATUS_OFF);
170 if (!(val & BSEC_MODE_PWR_MASK)) {
171 ret = bsec_power_safmem(base, true);
176 /* set BSEC_OTP_CTRL_OFF with the otp value*/
177 writel(otp | BSEC_READ, base + BSEC_OTP_CTRL_OFF);
179 /* check otp status*/
180 ret = readl_poll_timeout(base + BSEC_OTP_STATUS_OFF,
181 val, (val & BSEC_MODE_BUSY_MASK) == 0,
186 ret = bsec_check_error(base, otp);
189 bsec_power_safmem(base, false);
195 * bsec_read_shadow() - read an otp data value from shadow
196 * @base: base address of bsec IP
198 * @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
199 * Return: 0 if no error
201 static int bsec_read_shadow(u32 base, u32 *val, u32 otp)
203 *val = readl(base + BSEC_OTP_DATA_OFF + otp * sizeof(u32));
205 return bsec_check_error(base, otp);
209 * bsec_write_shadow() - write value in BSEC data register in shadow
210 * @base: base address of bsec IP
211 * @val: value to write
212 * @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
213 * Return: 0 if no error
215 static int bsec_write_shadow(u32 base, u32 val, u32 otp)
217 /* check if programming of otp is locked */
218 if (bsec_read_SW_lock(base, otp))
219 pr_debug("bsec : OTP %d is lock, write will be ignore\n", otp);
221 writel(val, base + BSEC_OTP_DATA_OFF + otp * sizeof(u32));
223 return bsec_check_error(base, otp);
227 * bsec_program_otp() - program a bit in SAFMEM
228 * @base: base address of bsec IP
229 * @val: value to program
230 * @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
231 * after the function the otp data is not refreshed in shadow
232 * Return: 0 if no error
234 static int bsec_program_otp(long base, u32 val, u32 otp)
237 bool power_up = false;
239 if (bsec_read_SP_lock(base, otp))
240 pr_debug("bsec : OTP %d locked, prog will be ignore\n", otp);
242 if (readl(base + BSEC_OTP_LOCK_OFF) & (1 << BSEC_LOCK_PROGRAM))
243 pr_debug("bsec : Global lock, prog will be ignore\n");
245 /* check if safemem is power up */
246 if (!(readl(base + BSEC_OTP_STATUS_OFF) & BSEC_MODE_PWR_MASK)) {
247 ret = bsec_power_safmem(base, true);
253 /* set value in write register*/
254 writel(val, base + BSEC_OTP_WRDATA_OFF);
256 /* set BSEC_OTP_CTRL_OFF with the otp value */
257 writel(otp | BSEC_WRITE, base + BSEC_OTP_CTRL_OFF);
259 /* check otp status*/
260 ret = readl_poll_timeout(base + BSEC_OTP_STATUS_OFF,
261 val, (val & BSEC_MODE_BUSY_MASK) == 0,
266 if (val & BSEC_MODE_PROGFAIL_MASK)
269 ret = bsec_check_error(base, otp);
272 bsec_power_safmem(base, false);
276 #endif /* CONFIG_TFABOOT */
278 /* BSEC MISC driver *******************************************************/
279 struct stm32mp_bsec_platdata {
283 static int stm32mp_bsec_read_otp(struct udevice *dev, u32 *val, u32 otp)
285 #ifdef CONFIG_TFABOOT
286 return stm32_smc(STM32_SMC_BSEC,
290 struct stm32mp_bsec_platdata *plat = dev_get_platdata(dev);
294 /* read current shadow value */
295 ret = bsec_read_shadow(plat->base, &tmp_data, otp);
299 /* copy otp in shadow */
300 ret = bsec_shadow_register(plat->base, otp);
304 ret = bsec_read_shadow(plat->base, val, otp);
308 /* restore shadow value */
309 ret = bsec_write_shadow(plat->base, tmp_data, otp);
314 static int stm32mp_bsec_read_shadow(struct udevice *dev, u32 *val, u32 otp)
316 #ifdef CONFIG_TFABOOT
317 return stm32_smc(STM32_SMC_BSEC,
318 STM32_SMC_READ_SHADOW,
321 struct stm32mp_bsec_platdata *plat = dev_get_platdata(dev);
323 return bsec_read_shadow(plat->base, val, otp);
327 static int stm32mp_bsec_read_lock(struct udevice *dev, u32 *val, u32 otp)
329 struct stm32mp_bsec_platdata *plat = dev_get_platdata(dev);
331 /* return OTP permanent write lock status */
332 *val = bsec_read_lock(plat->base + BSEC_WRLOCK_OFF, otp);
337 static int stm32mp_bsec_write_otp(struct udevice *dev, u32 val, u32 otp)
339 #ifdef CONFIG_TFABOOT
340 return stm32_smc_exec(STM32_SMC_BSEC,
344 struct stm32mp_bsec_platdata *plat = dev_get_platdata(dev);
346 return bsec_program_otp(plat->base, val, otp);
350 static int stm32mp_bsec_write_shadow(struct udevice *dev, u32 val, u32 otp)
352 #ifdef CONFIG_TFABOOT
353 return stm32_smc_exec(STM32_SMC_BSEC,
354 STM32_SMC_WRITE_SHADOW,
357 struct stm32mp_bsec_platdata *plat = dev_get_platdata(dev);
359 return bsec_write_shadow(plat->base, val, otp);
363 static int stm32mp_bsec_write_lock(struct udevice *dev, u32 val, u32 otp)
365 #ifdef CONFIG_TFABOOT
367 return stm32_smc_exec(STM32_SMC_BSEC,
368 STM32_SMC_WRLOCK_OTP,
371 return 0; /* nothing to do */
379 static int stm32mp_bsec_read(struct udevice *dev, int offset,
384 bool shadow = true, lock = false;
385 int nb_otp = size / sizeof(u32);
387 unsigned int offs = offset;
389 if (offs >= STM32_BSEC_LOCK_OFFSET) {
390 offs -= STM32_BSEC_LOCK_OFFSET;
392 } else if (offs >= STM32_BSEC_OTP_OFFSET) {
393 offs -= STM32_BSEC_OTP_OFFSET;
397 if ((offs % 4) || (size % 4))
400 otp = offs / sizeof(u32);
402 for (i = otp; i < (otp + nb_otp) && i <= BSEC_OTP_MAX_VALUE; i++) {
403 u32 *addr = &((u32 *)buf)[i - otp];
406 ret = stm32mp_bsec_read_lock(dev, addr, i);
408 ret = stm32mp_bsec_read_shadow(dev, addr, i);
410 ret = stm32mp_bsec_read_otp(dev, addr, i);
418 return (i - otp) * 4;
421 static int stm32mp_bsec_write(struct udevice *dev, int offset,
422 const void *buf, int size)
426 bool shadow = true, lock = false;
427 int nb_otp = size / sizeof(u32);
429 unsigned int offs = offset;
431 if (offs >= STM32_BSEC_LOCK_OFFSET) {
432 offs -= STM32_BSEC_LOCK_OFFSET;
434 } else if (offs >= STM32_BSEC_OTP_OFFSET) {
435 offs -= STM32_BSEC_OTP_OFFSET;
439 if ((offs % 4) || (size % 4))
442 otp = offs / sizeof(u32);
444 for (i = otp; i < otp + nb_otp && i <= BSEC_OTP_MAX_VALUE; i++) {
445 u32 *val = &((u32 *)buf)[i - otp];
448 ret = stm32mp_bsec_write_lock(dev, *val, i);
450 ret = stm32mp_bsec_write_shadow(dev, *val, i);
452 ret = stm32mp_bsec_write_otp(dev, *val, i);
459 return (i - otp) * 4;
462 static const struct misc_ops stm32mp_bsec_ops = {
463 .read = stm32mp_bsec_read,
464 .write = stm32mp_bsec_write,
467 static int stm32mp_bsec_ofdata_to_platdata(struct udevice *dev)
469 struct stm32mp_bsec_platdata *plat = dev_get_platdata(dev);
471 plat->base = (u32)dev_read_addr_ptr(dev);
476 #ifndef CONFIG_TFABOOT
477 static int stm32mp_bsec_probe(struct udevice *dev)
480 struct stm32mp_bsec_platdata *plat = dev_get_platdata(dev);
482 /* update unlocked shadow for OTP cleared by the rom code */
483 for (otp = 57; otp <= BSEC_OTP_MAX_VALUE; otp++)
484 if (!bsec_read_SR_lock(plat->base, otp))
485 bsec_shadow_register(plat->base, otp);
491 static const struct udevice_id stm32mp_bsec_ids[] = {
492 { .compatible = "st,stm32mp15-bsec" },
496 U_BOOT_DRIVER(stm32mp_bsec) = {
497 .name = "stm32mp_bsec",
499 .of_match = stm32mp_bsec_ids,
500 .ofdata_to_platdata = stm32mp_bsec_ofdata_to_platdata,
501 .platdata_auto_alloc_size = sizeof(struct stm32mp_bsec_platdata),
502 .ops = &stm32mp_bsec_ops,
503 #ifndef CONFIG_TFABOOT
504 .probe = stm32mp_bsec_probe,