drivers/spi/zynqmp_gqspi.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2018 Xilinx
   4  *
   5  * Xilinx ZynqMP Generic Quad-SPI(QSPI) controller driver(master mode only)
   6  */
   7
   8 #include <common.h>
   9 #include <cpu_func.h>
  10 #include <asm/arch/sys_proto.h>
  11 #include <asm/io.h>
  12 #include <clk.h>
  13 #include <dm.h>
  14 #include <malloc.h>
  15 #include <memalign.h>
  16 #include <spi.h>
  17 #include <ubi_uboot.h>
  18 #include <wait_bit.h>
  19
  20 #define GQSPI_GFIFO_STRT_MODE_MASK      BIT(29)
  21 #define GQSPI_CONFIG_MODE_EN_MASK       (3 << 30)
  22 #define GQSPI_CONFIG_DMA_MODE           (2 << 30)
  23 #define GQSPI_CONFIG_CPHA_MASK          BIT(2)
  24 #define GQSPI_CONFIG_CPOL_MASK          BIT(1)
  25
  26 /*
  27  * QSPI Interrupt Registers bit Masks
  28  *
  29  * All the four interrupt registers (Status/Mask/Enable/Disable) have the same
  30  * bit definitions.
  31  */
  32 #define GQSPI_IXR_TXNFULL_MASK          0x00000004 /* QSPI TX FIFO Overflow */
  33 #define GQSPI_IXR_TXFULL_MASK           0x00000008 /* QSPI TX FIFO is full */
  34 #define GQSPI_IXR_RXNEMTY_MASK          0x00000010 /* QSPI RX FIFO Not Empty */
  35 #define GQSPI_IXR_GFEMTY_MASK           0x00000080 /* QSPI Generic FIFO Empty */
  36 #define GQSPI_IXR_ALL_MASK              (GQSPI_IXR_TXNFULL_MASK | \
  37                                          GQSPI_IXR_RXNEMTY_MASK)
  38
  39 /*
  40  * QSPI Enable Register bit Masks
  41  *
  42  * This register is used to enable or disable the QSPI controller
  43  */
  44 #define GQSPI_ENABLE_ENABLE_MASK        0x00000001 /* QSPI Enable Bit Mask */
  45
  46 #define GQSPI_GFIFO_LOW_BUS             BIT(14)
  47 #define GQSPI_GFIFO_CS_LOWER            BIT(12)
  48 #define GQSPI_GFIFO_UP_BUS              BIT(15)
  49 #define GQSPI_GFIFO_CS_UPPER            BIT(13)
  50 #define GQSPI_SPI_MODE_QSPI             (3 << 10)
  51 #define GQSPI_SPI_MODE_SPI              BIT(10)
  52 #define GQSPI_SPI_MODE_DUAL_SPI         (2 << 10)
  53 #define GQSPI_IMD_DATA_CS_ASSERT        5
  54 #define GQSPI_IMD_DATA_CS_DEASSERT      5
  55 #define GQSPI_GFIFO_TX                  BIT(16)
  56 #define GQSPI_GFIFO_RX                  BIT(17)
  57 #define GQSPI_GFIFO_STRIPE_MASK         BIT(18)
  58 #define GQSPI_GFIFO_IMD_MASK            0xFF
  59 #define GQSPI_GFIFO_EXP_MASK            BIT(9)
  60 #define GQSPI_GFIFO_DATA_XFR_MASK       BIT(8)
  61 #define GQSPI_STRT_GEN_FIFO             BIT(28)
  62 #define GQSPI_GEN_FIFO_STRT_MOD         BIT(29)
  63 #define GQSPI_GFIFO_WP_HOLD             BIT(19)
  64 #define GQSPI_BAUD_DIV_MASK             (7 << 3)
  65 #define GQSPI_DFLT_BAUD_RATE_DIV        BIT(3)
  66 #define GQSPI_GFIFO_ALL_INT_MASK        0xFBE
  67 #define GQSPI_DMA_DST_I_STS_DONE        BIT(1)
  68 #define GQSPI_DMA_DST_I_STS_MASK        0xFE
  69 #define MODEBITS                        0x6
  70
  71 #define GQSPI_GFIFO_SELECT              BIT(0)
  72 #define GQSPI_FIFO_THRESHOLD            1
  73
  74 #define SPI_XFER_ON_BOTH                0
  75 #define SPI_XFER_ON_LOWER               1
  76 #define SPI_XFER_ON_UPPER               2
  77
  78 #define GQSPI_DMA_ALIGN                 0x4
  79 #define GQSPI_MAX_BAUD_RATE_VAL         7
  80 #define GQSPI_DFLT_BAUD_RATE_VAL        2
  81
  82 #define GQSPI_TIMEOUT                   100000000
  83
  84 #define GQSPI_BAUD_DIV_SHIFT            2
  85 #define GQSPI_LPBK_DLY_ADJ_LPBK_SHIFT   5
  86 #define GQSPI_LPBK_DLY_ADJ_DLY_1        0x2
  87 #define GQSPI_LPBK_DLY_ADJ_DLY_1_SHIFT  3
  88 #define GQSPI_LPBK_DLY_ADJ_DLY_0        0x3
  89 #define GQSPI_USE_DATA_DLY              0x1
  90 #define GQSPI_USE_DATA_DLY_SHIFT        31
  91 #define GQSPI_DATA_DLY_ADJ_VALUE        0x2
  92 #define GQSPI_DATA_DLY_ADJ_SHIFT        28
  93 #define TAP_DLY_BYPASS_LQSPI_RX_VALUE   0x1
  94 #define TAP_DLY_BYPASS_LQSPI_RX_SHIFT   2
  95 #define GQSPI_DATA_DLY_ADJ_OFST         0x000001F8
  96 #define IOU_TAPDLY_BYPASS_OFST          0xFF180390
  97 #define GQSPI_LPBK_DLY_ADJ_LPBK_MASK    0x00000020
  98 #define GQSPI_FREQ_40MHZ                40000000
  99 #define GQSPI_FREQ_100MHZ               100000000
 100 #define GQSPI_FREQ_150MHZ               150000000
 101 #define IOU_TAPDLY_BYPASS_MASK          0x7
 102
 103 #define GQSPI_REG_OFFSET                0x100
 104 #define GQSPI_DMA_REG_OFFSET            0x800
 105
 106 /* QSPI register offsets */
 107 struct zynqmp_qspi_regs {
 108         u32 confr;      /* 0x00 */
 109         u32 isr;        /* 0x04 */
 110         u32 ier;        /* 0x08 */
 111         u32 idisr;      /* 0x0C */
 112         u32 imaskr;     /* 0x10 */
 113         u32 enbr;       /* 0x14 */
 114         u32 dr;         /* 0x18 */
 115         u32 txd0r;      /* 0x1C */
 116         u32 drxr;       /* 0x20 */
 117         u32 sicr;       /* 0x24 */
 118         u32 txftr;      /* 0x28 */
 119         u32 rxftr;      /* 0x2C */
 120         u32 gpior;      /* 0x30 */
 121         u32 reserved0;  /* 0x34 */
 122         u32 lpbkdly;    /* 0x38 */
 123         u32 reserved1;  /* 0x3C */
 124         u32 genfifo;    /* 0x40 */
 125         u32 gqspisel;   /* 0x44 */
 126         u32 reserved2;  /* 0x48 */
 127         u32 gqfifoctrl; /* 0x4C */
 128         u32 gqfthr;     /* 0x50 */
 129         u32 gqpollcfg;  /* 0x54 */
 130         u32 gqpollto;   /* 0x58 */
 131         u32 gqxfersts;  /* 0x5C */
 132         u32 gqfifosnap; /* 0x60 */
 133         u32 gqrxcpy;    /* 0x64 */
 134         u32 reserved3[36];      /* 0x68 */
 135         u32 gqspidlyadj;        /* 0xF8 */
 136 };
 137
 138 struct zynqmp_qspi_dma_regs {
 139         u32 dmadst;     /* 0x00 */
 140         u32 dmasize;    /* 0x04 */
 141         u32 dmasts;     /* 0x08 */
 142         u32 dmactrl;    /* 0x0C */
 143         u32 reserved0;  /* 0x10 */
 144         u32 dmaisr;     /* 0x14 */
 145         u32 dmaier;     /* 0x18 */
 146         u32 dmaidr;     /* 0x1C */
 147         u32 dmaimr;     /* 0x20 */
 148         u32 dmactrl2;   /* 0x24 */
 149         u32 dmadstmsb;  /* 0x28 */
 150 };
 151
 152 DECLARE_GLOBAL_DATA_PTR;
 153
 154 struct zynqmp_qspi_platdata {
 155         struct zynqmp_qspi_regs *regs;
 156         struct zynqmp_qspi_dma_regs *dma_regs;
 157         u32 frequency;
 158         u32 speed_hz;
 159 };
 160
 161 struct zynqmp_qspi_priv {
 162         struct zynqmp_qspi_regs *regs;
 163         struct zynqmp_qspi_dma_regs *dma_regs;
 164         const void *tx_buf;
 165         void *rx_buf;
 166         unsigned int len;
 167         int bytes_to_transfer;
 168         int bytes_to_receive;
 169         unsigned int is_inst;
 170         unsigned int cs_change:1;
 171 };
 172
 173 static int zynqmp_qspi_ofdata_to_platdata(struct udevice *bus)
 174 {
 175         struct zynqmp_qspi_platdata *plat = bus->platdata;
 176
 177         debug("%s\n", __func__);
 178
 179         plat->regs = (struct zynqmp_qspi_regs *)(devfdt_get_addr(bus) +
 180                                                  GQSPI_REG_OFFSET);
 181         plat->dma_regs = (struct zynqmp_qspi_dma_regs *)
 182                           (devfdt_get_addr(bus) + GQSPI_DMA_REG_OFFSET);
 183
 184         return 0;
 185 }
 186
 187 static void zynqmp_qspi_init_hw(struct zynqmp_qspi_priv *priv)
 188 {
 189         u32 config_reg;
 190         struct zynqmp_qspi_regs *regs = priv->regs;
 191
 192         writel(GQSPI_GFIFO_SELECT, &regs->gqspisel);
 193         writel(GQSPI_GFIFO_ALL_INT_MASK, &regs->idisr);
 194         writel(GQSPI_FIFO_THRESHOLD, &regs->txftr);
 195         writel(GQSPI_FIFO_THRESHOLD, &regs->rxftr);
 196         writel(GQSPI_GFIFO_ALL_INT_MASK, &regs->isr);
 197
 198         config_reg = readl(&regs->confr);
 199         config_reg &= ~(GQSPI_GFIFO_STRT_MODE_MASK |
 200                         GQSPI_CONFIG_MODE_EN_MASK);
 201         config_reg |= GQSPI_CONFIG_DMA_MODE |
 202                       GQSPI_GFIFO_WP_HOLD |
 203                       GQSPI_DFLT_BAUD_RATE_DIV;
 204         writel(config_reg, &regs->confr);
 205
 206         writel(GQSPI_ENABLE_ENABLE_MASK, &regs->enbr);
 207 }
 208
 209 static u32 zynqmp_qspi_bus_select(struct zynqmp_qspi_priv *priv)
 210 {
 211         u32 gqspi_fifo_reg = 0;
 212
 213         gqspi_fifo_reg = GQSPI_GFIFO_LOW_BUS |
 214                          GQSPI_GFIFO_CS_LOWER;
 215
 216         return gqspi_fifo_reg;
 217 }
 218
 219 static void zynqmp_qspi_fill_gen_fifo(struct zynqmp_qspi_priv *priv,
 220                                       u32 gqspi_fifo_reg)
 221 {
 222         struct zynqmp_qspi_regs *regs = priv->regs;
 223         int ret = 0;
 224
 225         ret = wait_for_bit_le32(&regs->isr, GQSPI_IXR_GFEMTY_MASK, 1,
 226                                 GQSPI_TIMEOUT, 1);
 227         if (ret)
 228                 printf("%s Timeout\n", __func__);
 229
 230         writel(gqspi_fifo_reg, &regs->genfifo);
 231 }
 232
 233 static void zynqmp_qspi_chipselect(struct zynqmp_qspi_priv *priv, int is_on)
 234 {
 235         u32 gqspi_fifo_reg = 0;
 236
 237         if (is_on) {
 238                 gqspi_fifo_reg = zynqmp_qspi_bus_select(priv);
 239                 gqspi_fifo_reg |= GQSPI_SPI_MODE_SPI |
 240                                   GQSPI_IMD_DATA_CS_ASSERT;
 241         } else {
 242                 gqspi_fifo_reg = GQSPI_GFIFO_LOW_BUS;
 243                 gqspi_fifo_reg |= GQSPI_IMD_DATA_CS_DEASSERT;
 244         }
 245
 246         debug("GFIFO_CMD_CS: 0x%x\n", gqspi_fifo_reg);
 247
 248         zynqmp_qspi_fill_gen_fifo(priv, gqspi_fifo_reg);
 249 }
 250
 251 void zynqmp_qspi_set_tapdelay(struct udevice *bus, u32 baudrateval)
 252 {
 253         struct zynqmp_qspi_platdata *plat = bus->platdata;
 254         struct zynqmp_qspi_priv *priv = dev_get_priv(bus);
 255         struct zynqmp_qspi_regs *regs = priv->regs;
 256         u32 tapdlybypass = 0, lpbkdlyadj = 0, datadlyadj = 0, clk_rate;
 257         u32 reqhz = 0;
 258
 259         clk_rate = plat->frequency;
 260         reqhz = (clk_rate / (GQSPI_BAUD_DIV_SHIFT << baudrateval));
 261
 262         debug("%s, req_hz:%d, clk_rate:%d, baudrateval:%d\n",
 263               __func__, reqhz, clk_rate, baudrateval);
 264
 265         if (reqhz < GQSPI_FREQ_40MHZ) {
 266                 zynqmp_mmio_read(IOU_TAPDLY_BYPASS_OFST, &tapdlybypass);
 267                 tapdlybypass |= (TAP_DLY_BYPASS_LQSPI_RX_VALUE <<
 268                                 TAP_DLY_BYPASS_LQSPI_RX_SHIFT);
 269         } else if (reqhz <= GQSPI_FREQ_100MHZ) {
 270                 zynqmp_mmio_read(IOU_TAPDLY_BYPASS_OFST, &tapdlybypass);
 271                 tapdlybypass |= (TAP_DLY_BYPASS_LQSPI_RX_VALUE <<
 272                                 TAP_DLY_BYPASS_LQSPI_RX_SHIFT);
 273                 lpbkdlyadj = readl(&regs->lpbkdly);
 274                 lpbkdlyadj |= (GQSPI_LPBK_DLY_ADJ_LPBK_MASK);
 275                 datadlyadj = readl(&regs->gqspidlyadj);
 276                 datadlyadj |= ((GQSPI_USE_DATA_DLY << GQSPI_USE_DATA_DLY_SHIFT)
 277                                 | (GQSPI_DATA_DLY_ADJ_VALUE <<
 278                                         GQSPI_DATA_DLY_ADJ_SHIFT));
 279         } else if (reqhz <= GQSPI_FREQ_150MHZ) {
 280                 lpbkdlyadj = readl(&regs->lpbkdly);
 281                 lpbkdlyadj |= ((GQSPI_LPBK_DLY_ADJ_LPBK_MASK) |
 282                                 GQSPI_LPBK_DLY_ADJ_DLY_0);
 283         }
 284
 285         zynqmp_mmio_write(IOU_TAPDLY_BYPASS_OFST, IOU_TAPDLY_BYPASS_MASK,
 286                           tapdlybypass);
 287         writel(lpbkdlyadj, &regs->lpbkdly);
 288         writel(datadlyadj, &regs->gqspidlyadj);
 289 }
 290
 291 static int zynqmp_qspi_set_speed(struct udevice *bus, uint speed)
 292 {
 293         struct zynqmp_qspi_platdata *plat = bus->platdata;
 294         struct zynqmp_qspi_priv *priv = dev_get_priv(bus);
 295         struct zynqmp_qspi_regs *regs = priv->regs;
 296         u32 confr;
 297         u8 baud_rate_val = 0;
 298
 299         debug("%s\n", __func__);
 300         if (speed > plat->frequency)
 301                 speed = plat->frequency;
 302
 303         /* Set the clock frequency */
 304         confr = readl(&regs->confr);
 305         if (speed == 0) {
 306                 /* Set baudrate x8, if the freq is 0 */
 307                 baud_rate_val = GQSPI_DFLT_BAUD_RATE_VAL;
 308         } else if (plat->speed_hz != speed) {
 309                 while ((baud_rate_val < 8) &&
 310                        ((plat->frequency /
 311                        (2 << baud_rate_val)) > speed))
 312                         baud_rate_val++;
 313
 314                 if (baud_rate_val > GQSPI_MAX_BAUD_RATE_VAL)
 315                         baud_rate_val = GQSPI_DFLT_BAUD_RATE_VAL;
 316
 317                 plat->speed_hz = plat->frequency / (2 << baud_rate_val);
 318         }
 319         confr &= ~GQSPI_BAUD_DIV_MASK;
 320         confr |= (baud_rate_val << 3);
 321         writel(confr, &regs->confr);
 322
 323         zynqmp_qspi_set_tapdelay(bus, baud_rate_val);
 324         debug("regs=%p, speed=%d\n", priv->regs, plat->speed_hz);
 325
 326         return 0;
 327 }
 328
 329 static int zynqmp_qspi_probe(struct udevice *bus)
 330 {
 331         struct zynqmp_qspi_platdata *plat = dev_get_platdata(bus);
 332         struct zynqmp_qspi_priv *priv = dev_get_priv(bus);
 333         struct clk clk;
 334         unsigned long clock;
 335         int ret;
 336
 337         debug("%s: bus:%p, priv:%p\n", __func__, bus, priv);
 338
 339         priv->regs = plat->regs;
 340         priv->dma_regs = plat->dma_regs;
 341
 342         ret = clk_get_by_index(bus, 0, &clk);
 343         if (ret < 0) {
 344                 dev_err(dev, "failed to get clock\n");
 345                 return ret;
 346         }
 347
 348         clock = clk_get_rate(&clk);
 349         if (IS_ERR_VALUE(clock)) {
 350                 dev_err(dev, "failed to get rate\n");
 351                 return clock;
 352         }
 353         debug("%s: CLK %ld\n", __func__, clock);
 354
 355         ret = clk_enable(&clk);
 356         if (ret && ret != -ENOSYS) {
 357                 dev_err(dev, "failed to enable clock\n");
 358                 return ret;
 359         }
 360         plat->frequency = clock;
 361         plat->speed_hz = plat->frequency / 2;
 362
 363         /* init the zynq spi hw */
 364         zynqmp_qspi_init_hw(priv);
 365
 366         return 0;
 367 }
 368
 369 static int zynqmp_qspi_set_mode(struct udevice *bus, uint mode)
 370 {
 371         struct zynqmp_qspi_priv *priv = dev_get_priv(bus);
 372         struct zynqmp_qspi_regs *regs = priv->regs;
 373         u32 confr;
 374
 375         debug("%s\n", __func__);
 376         /* Set the SPI Clock phase and polarities */
 377         confr = readl(&regs->confr);
 378         confr &= ~(GQSPI_CONFIG_CPHA_MASK |
 379                    GQSPI_CONFIG_CPOL_MASK);
 380
 381         if (mode & SPI_CPHA)
 382                 confr |= GQSPI_CONFIG_CPHA_MASK;
 383         if (mode & SPI_CPOL)
 384                 confr |= GQSPI_CONFIG_CPOL_MASK;
 385
 386         writel(confr, &regs->confr);
 387
 388         return 0;
 389 }
 390
 391 static int zynqmp_qspi_fill_tx_fifo(struct zynqmp_qspi_priv *priv, u32 size)
 392 {
 393         u32 data;
 394         int ret = 0;
 395         struct zynqmp_qspi_regs *regs = priv->regs;
 396         u32 *buf = (u32 *)priv->tx_buf;
 397         u32 len = size;
 398
 399         debug("TxFIFO: 0x%x, size: 0x%x\n", readl(&regs->isr),
 400               size);
 401
 402         while (size) {
 403                 ret = wait_for_bit_le32(&regs->isr, GQSPI_IXR_TXNFULL_MASK, 1,
 404                                         GQSPI_TIMEOUT, 1);
 405                 if (ret) {
 406                         printf("%s: Timeout\n", __func__);
 407                         return ret;
 408                 }
 409
 410                 if (size >= 4) {
 411                         writel(*buf, &regs->txd0r);
 412                         buf++;
 413                         size -= 4;
 414                 } else {
 415                         switch (size) {
 416                         case 1:
 417                                 data = *((u8 *)buf);
 418                                 buf += 1;
 419                                 data |= GENMASK(31, 8);
 420                                 break;
 421                         case 2:
 422                                 data = *((u16 *)buf);
 423                                 buf += 2;
 424                                 data |= GENMASK(31, 16);
 425                                 break;
 426                         case 3:
 427                                 data = *((u16 *)buf);
 428                                 buf += 2;
 429                                 data |= (*((u8 *)buf) << 16);
 430                                 buf += 1;
 431                                 data |= GENMASK(31, 24);
 432                                 break;
 433                         }
 434                         writel(data, &regs->txd0r);
 435                         size = 0;
 436                 }
 437         }
 438
 439         priv->tx_buf += len;
 440         return 0;
 441 }
 442
 443 static void zynqmp_qspi_genfifo_cmd(struct zynqmp_qspi_priv *priv)
 444 {
 445         u32 gen_fifo_cmd;
 446         u32 bytecount = 0;
 447
 448         while (priv->len) {
 449                 gen_fifo_cmd = zynqmp_qspi_bus_select(priv);
 450                 gen_fifo_cmd |= GQSPI_GFIFO_TX | GQSPI_SPI_MODE_SPI;
 451                 gen_fifo_cmd |= *(u8 *)priv->tx_buf;
 452                 bytecount++;
 453                 priv->len--;
 454                 priv->tx_buf = (u8 *)priv->tx_buf + 1;
 455
 456                 debug("GFIFO_CMD_Cmd = 0x%x\n", gen_fifo_cmd);
 457
 458                 zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd);
 459         }
 460 }
 461
 462 static u32 zynqmp_qspi_calc_exp(struct zynqmp_qspi_priv *priv,
 463                                 u32 *gen_fifo_cmd)
 464 {
 465         u32 expval = 8;
 466         u32 len;
 467
 468         while (1) {
 469                 if (priv->len > 255) {
 470                         if (priv->len & (1 << expval)) {
 471                                 *gen_fifo_cmd &= ~GQSPI_GFIFO_IMD_MASK;
 472                                 *gen_fifo_cmd |= GQSPI_GFIFO_EXP_MASK;
 473                                 *gen_fifo_cmd |= expval;
 474                                 priv->len -= (1 << expval);
 475                                 return expval;
 476                         }
 477                         expval++;
 478                 } else {
 479                         *gen_fifo_cmd &= ~(GQSPI_GFIFO_IMD_MASK |
 480                                           GQSPI_GFIFO_EXP_MASK);
 481                         *gen_fifo_cmd |= (u8)priv->len;
 482                         len = (u8)priv->len;
 483                         priv->len  = 0;
 484                         return len;
 485                 }
 486         }
 487 }
 488
 489 static int zynqmp_qspi_genfifo_fill_tx(struct zynqmp_qspi_priv *priv)
 490 {
 491         u32 gen_fifo_cmd;
 492         u32 len;
 493         int ret = 0;
 494
 495         gen_fifo_cmd = zynqmp_qspi_bus_select(priv);
 496         gen_fifo_cmd |= GQSPI_GFIFO_TX |
 497                         GQSPI_GFIFO_DATA_XFR_MASK;
 498
 499         gen_fifo_cmd |= GQSPI_SPI_MODE_SPI;
 500
 501         while (priv->len) {
 502                 len = zynqmp_qspi_calc_exp(priv, &gen_fifo_cmd);
 503                 zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd);
 504
 505                 debug("GFIFO_CMD_TX:0x%x\n", gen_fifo_cmd);
 506
 507                 if (gen_fifo_cmd & GQSPI_GFIFO_EXP_MASK)
 508                         ret = zynqmp_qspi_fill_tx_fifo(priv,
 509                                                        1 << len);
 510                 else
 511                         ret = zynqmp_qspi_fill_tx_fifo(priv,
 512                                                        len);
 513
 514                 if (ret)
 515                         return ret;
 516         }
 517         return ret;
 518 }
 519
 520 static int zynqmp_qspi_start_dma(struct zynqmp_qspi_priv *priv,
 521                                  u32 gen_fifo_cmd, u32 *buf)
 522 {
 523         u32 addr;
 524         u32 size, len;
 525         u32 actuallen = priv->len;
 526         int ret = 0;
 527         struct zynqmp_qspi_dma_regs *dma_regs = priv->dma_regs;
 528
 529         writel((unsigned long)buf, &dma_regs->dmadst);
 530         writel(roundup(priv->len, ARCH_DMA_MINALIGN), &dma_regs->dmasize);
 531         writel(GQSPI_DMA_DST_I_STS_MASK, &dma_regs->dmaier);
 532         addr = (unsigned long)buf;
 533         size = roundup(priv->len, ARCH_DMA_MINALIGN);
 534         flush_dcache_range(addr, addr + size);
 535
 536         while (priv->len) {
 537                 len = zynqmp_qspi_calc_exp(priv, &gen_fifo_cmd);
 538                 if (!(gen_fifo_cmd & GQSPI_GFIFO_EXP_MASK) &&
 539                     (len % ARCH_DMA_MINALIGN)) {
 540                         gen_fifo_cmd &= ~GENMASK(7, 0);
 541                         gen_fifo_cmd |= roundup(len, ARCH_DMA_MINALIGN);
 542                 }
 543                 zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd);
 544
 545                 debug("GFIFO_CMD_RX:0x%x\n", gen_fifo_cmd);
 546         }
 547
 548         ret = wait_for_bit_le32(&dma_regs->dmaisr, GQSPI_DMA_DST_I_STS_DONE,
 549                                 1, GQSPI_TIMEOUT, 1);
 550         if (ret) {
 551                 printf("DMA Timeout:0x%x\n", readl(&dma_regs->dmaisr));
 552                 return -ETIMEDOUT;
 553         }
 554
 555         writel(GQSPI_DMA_DST_I_STS_DONE, &dma_regs->dmaisr);
 556
 557         debug("buf:0x%lx, rxbuf:0x%lx, *buf:0x%x len: 0x%x\n",
 558               (unsigned long)buf, (unsigned long)priv->rx_buf, *buf,
 559               actuallen);
 560
 561         if (buf != priv->rx_buf)
 562                 memcpy(priv->rx_buf, buf, actuallen);
 563
 564         return 0;
 565 }
 566
 567 static int zynqmp_qspi_genfifo_fill_rx(struct zynqmp_qspi_priv *priv)
 568 {
 569         u32 gen_fifo_cmd;
 570         u32 *buf;
 571         u32 actuallen = priv->len;
 572
 573         gen_fifo_cmd = zynqmp_qspi_bus_select(priv);
 574         gen_fifo_cmd |= GQSPI_GFIFO_RX |
 575                         GQSPI_GFIFO_DATA_XFR_MASK;
 576
 577         gen_fifo_cmd |= GQSPI_SPI_MODE_SPI;
 578
 579         /*
 580          * Check if receive buffer is aligned to 4 byte and length
 581          * is multiples of four byte as we are using dma to receive.
 582          */
 583         if (!((unsigned long)priv->rx_buf & (GQSPI_DMA_ALIGN - 1)) &&
 584             !(actuallen % GQSPI_DMA_ALIGN)) {
 585                 buf = (u32 *)priv->rx_buf;
 586                 return zynqmp_qspi_start_dma(priv, gen_fifo_cmd, buf);
 587         }
 588
 589         ALLOC_CACHE_ALIGN_BUFFER(u8, tmp, roundup(priv->len,
 590                                                   GQSPI_DMA_ALIGN));
 591         buf = (u32 *)tmp;
 592         return zynqmp_qspi_start_dma(priv, gen_fifo_cmd, buf);
 593 }
 594
 595 static int zynqmp_qspi_start_transfer(struct zynqmp_qspi_priv *priv)
 596 {
 597         int ret = 0;
 598
 599         if (priv->is_inst) {
 600                 if (priv->tx_buf)
 601                         zynqmp_qspi_genfifo_cmd(priv);
 602                 else
 603                         return -EINVAL;
 604         } else {
 605                 if (priv->tx_buf)
 606                         ret = zynqmp_qspi_genfifo_fill_tx(priv);
 607                 else if (priv->rx_buf)
 608                         ret = zynqmp_qspi_genfifo_fill_rx(priv);
 609                 else
 610                         return -EINVAL;
 611         }
 612         return ret;
 613 }
 614
 615 static int zynqmp_qspi_transfer(struct zynqmp_qspi_priv *priv)
 616 {
 617         static unsigned int cs_change = 1;
 618         int status = 0;
 619
 620         debug("%s\n", __func__);
 621
 622         while (1) {
 623                 /* Select the chip if required */
 624                 if (cs_change)
 625                         zynqmp_qspi_chipselect(priv, 1);
 626
 627                 cs_change = priv->cs_change;
 628
 629                 if (!priv->tx_buf && !priv->rx_buf && priv->len) {
 630                         status = -EINVAL;
 631                         break;
 632                 }
 633
 634                 /* Request the transfer */
 635                 if (priv->len) {
 636                         status = zynqmp_qspi_start_transfer(priv);
 637                         priv->is_inst = 0;
 638                         if (status < 0)
 639                                 break;
 640                 }
 641
 642                 if (cs_change)
 643                         /* Deselect the chip */
 644                         zynqmp_qspi_chipselect(priv, 0);
 645                 break;
 646         }
 647
 648         return status;
 649 }
 650
 651 static int zynqmp_qspi_claim_bus(struct udevice *dev)
 652 {
 653         struct udevice *bus = dev->parent;
 654         struct zynqmp_qspi_priv *priv = dev_get_priv(bus);
 655         struct zynqmp_qspi_regs *regs = priv->regs;
 656
 657         writel(GQSPI_ENABLE_ENABLE_MASK, &regs->enbr);
 658
 659         return 0;
 660 }
 661
 662 static int zynqmp_qspi_release_bus(struct udevice *dev)
 663 {
 664         struct udevice *bus = dev->parent;
 665         struct zynqmp_qspi_priv *priv = dev_get_priv(bus);
 666         struct zynqmp_qspi_regs *regs = priv->regs;
 667
 668         writel(~GQSPI_ENABLE_ENABLE_MASK, &regs->enbr);
 669
 670         return 0;
 671 }
 672
 673 int zynqmp_qspi_xfer(struct udevice *dev, unsigned int bitlen, const void *dout,
 674                      void *din, unsigned long flags)
 675 {
 676         struct udevice *bus = dev->parent;
 677         struct zynqmp_qspi_priv *priv = dev_get_priv(bus);
 678
 679         debug("%s: priv: 0x%08lx bitlen: %d dout: 0x%08lx ", __func__,
 680               (unsigned long)priv, bitlen, (unsigned long)dout);
 681         debug("din: 0x%08lx flags: 0x%lx\n", (unsigned long)din, flags);
 682
 683         priv->tx_buf = dout;
 684         priv->rx_buf = din;
 685         priv->len = bitlen / 8;
 686
 687         /*
 688          * Assume that the beginning of a transfer with bits to
 689          * transmit must contain a device command.
 690          */
 691         if (dout && flags & SPI_XFER_BEGIN)
 692                 priv->is_inst = 1;
 693         else
 694                 priv->is_inst = 0;
 695
 696         if (flags & SPI_XFER_END)
 697                 priv->cs_change = 1;
 698         else
 699                 priv->cs_change = 0;
 700
 701         zynqmp_qspi_transfer(priv);
 702
 703         return 0;
 704 }
 705
 706 static const struct dm_spi_ops zynqmp_qspi_ops = {
 707         .claim_bus      = zynqmp_qspi_claim_bus,
 708         .release_bus    = zynqmp_qspi_release_bus,
 709         .xfer           = zynqmp_qspi_xfer,
 710         .set_speed      = zynqmp_qspi_set_speed,
 711         .set_mode       = zynqmp_qspi_set_mode,
 712 };
 713
 714 static const struct udevice_id zynqmp_qspi_ids[] = {
 715         { .compatible = "xlnx,zynqmp-qspi-1.0" },
 716         { .compatible = "xlnx,versal-qspi-1.0" },
 717         { }
 718 };
 719
 720 U_BOOT_DRIVER(zynqmp_qspi) = {
 721         .name   = "zynqmp_qspi",
 722         .id     = UCLASS_SPI,
 723         .of_match = zynqmp_qspi_ids,
 724         .ops    = &zynqmp_qspi_ops,
 725         .ofdata_to_platdata = zynqmp_qspi_ofdata_to_platdata,
 726         .platdata_auto_alloc_size = sizeof(struct zynqmp_qspi_platdata),
 727         .priv_auto_alloc_size = sizeof(struct zynqmp_qspi_priv),
 728         .probe  = zynqmp_qspi_probe,
 729 };