board/freescale/imx8mm_evk/spl.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2019 NXP
   4  */
   5
   6 #include <common.h>
   7 #include <cpu_func.h>
   8 #include <hang.h>
   9 #include <spl.h>
  10 #include <asm/io.h>
  11 #include <asm/mach-imx/iomux-v3.h>
  12 #include <asm/arch/clock.h>
  13 #include <asm/arch/imx8mm_pins.h>
  14 #include <asm/arch/sys_proto.h>
  15 #include <asm/mach-imx/boot_mode.h>
  16 #include <asm/arch/ddr.h>
  17
  18 #include <dm/uclass.h>
  19 #include <dm/device.h>
  20 #include <dm/uclass-internal.h>
  21 #include <dm/device-internal.h>
  22
  23 #include <power/pmic.h>
  24 #include <power/bd71837.h>
  25
  26 DECLARE_GLOBAL_DATA_PTR;
  27
  28 int spl_board_boot_device(enum boot_device boot_dev_spl)
  29 {
  30         switch (boot_dev_spl) {
  31         case SD2_BOOT:
  32         case MMC2_BOOT:
  33                 return BOOT_DEVICE_MMC1;
  34         case SD3_BOOT:
  35         case MMC3_BOOT:
  36                 return BOOT_DEVICE_MMC2;
  37         default:
  38                 return BOOT_DEVICE_NONE;
  39         }
  40 }
  41
  42 void spl_dram_init(void)
  43 {
  44         ddr_init(&dram_timing);
  45 }
  46
  47 void spl_board_init(void)
  48 {
  49         puts("Normal Boot\n");
  50 }
  51
  52 #ifdef CONFIG_SPL_LOAD_FIT
  53 int board_fit_config_name_match(const char *name)
  54 {
  55         /* Just empty function now - can't decide what to choose */
  56         debug("%s: %s\n", __func__, name);
  57
  58         return 0;
  59 }
  60 #endif
  61
  62 #define UART_PAD_CTRL   (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
  63 #define WDOG_PAD_CTRL   (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
  64
  65 static iomux_v3_cfg_t const uart_pads[] = {
  66         IMX8MM_PAD_UART2_RXD_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  67         IMX8MM_PAD_UART2_TXD_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  68 };
  69
  70 static iomux_v3_cfg_t const wdog_pads[] = {
  71         IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B  | MUX_PAD_CTRL(WDOG_PAD_CTRL),
  72 };
  73
  74 int board_early_init_f(void)
  75 {
  76         struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
  77
  78         imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
  79
  80         set_wdog_reset(wdog);
  81
  82         imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
  83
  84         return 0;
  85 }
  86
  87 int power_init_board(void)
  88 {
  89         struct udevice *dev;
  90         int ret;
  91
  92         ret = pmic_get("pmic@4b", &dev);
  93         if (ret == -ENODEV) {
  94                 puts("No pmic\n");
  95                 return 0;
  96         }
  97         if (ret != 0)
  98                 return ret;
  99
 100         /* decrease RESET key long push time from the default 10s to 10ms */
 101         pmic_reg_write(dev, BD718XX_PWRONCONFIG1, 0x0);
 102
 103         /* unlock the PMIC regs */
 104         pmic_reg_write(dev, BD718XX_REGLOCK, 0x1);
 105
 106         /* increase VDD_SOC to typical value 0.85v before first DRAM access */
 107         pmic_reg_write(dev, BD718XX_BUCK1_VOLT_RUN, 0x0f);
 108
 109         /* increase VDD_DRAM to 0.975v for 3Ghz DDR */
 110         pmic_reg_write(dev, BD718XX_1ST_NODVS_BUCK_VOLT, 0x83);
 111
 112 #ifndef CONFIG_IMX8M_LPDDR4
 113         /* increase NVCC_DRAM_1V2 to 1.2v for DDR4 */
 114         pmic_reg_write(dev, BD718XX_4TH_NODVS_BUCK_VOLT, 0x28);
 115 #endif
 116
 117         /* lock the PMIC regs */
 118         pmic_reg_write(dev, BD718XX_REGLOCK, 0x11);
 119
 120         return 0;
 121 }
 122
 123 void board_init_f(ulong dummy)
 124 {
 125         struct udevice *dev;
 126         int ret;
 127
 128         arch_cpu_init();
 129
 130         init_uart_clk(1);
 131
 132         board_early_init_f();
 133
 134         timer_init();
 135
 136         preloader_console_init();
 137
 138         /* Clear the BSS. */
 139         memset(__bss_start, 0, __bss_end - __bss_start);
 140
 141         ret = spl_early_init();
 142         if (ret) {
 143                 debug("spl_early_init() failed: %d\n", ret);
 144                 hang();
 145         }
 146
 147         ret = uclass_get_device_by_name(UCLASS_CLK,
 148                                         "clock-controller@30380000",
 149                                         &dev);
 150         if (ret < 0) {
 151                 printf("Failed to find clock node. Check device tree\n");
 152                 hang();
 153         }
 154
 155         enable_tzc380();
 156
 157         power_init_board();
 158
 159         /* DDR initialization */
 160         spl_dram_init();
 161
 162         board_init_r(NULL, 0);
 163 }
 164
 165 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 166 {
 167         puts ("resetting ...\n");
 168
 169         reset_cpu(WDOG1_BASE_ADDR);
 170
 171         return 0;
 172 }