arch/arm/mach-tegra/arm64-mmu.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2014 - 2015 Xilinx, Inc.
   4  * Michal Simek <[email protected]>
   5  * (This file derived from arch/arm/mach-zynqmp/cpu.c)
   6  *
   7  * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
   8  */
   9
  10 #include <asm/system.h>
  11 #include <asm/armv8/mmu.h>
  12
  13 /* size: IO + NR_DRAM_BANKS + terminator */
  14 struct mm_region tegra_mem_map[1 + CONFIG_NR_DRAM_BANKS + 1] = {
  15         {
  16                 .virt = 0x0UL,
  17                 .phys = 0x0UL,
  18                 .size = 0x80000000UL,
  19                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  20                          PTE_BLOCK_NON_SHARE |
  21                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
  22         }, {
  23                 .virt = 0x80000000UL,
  24                 .phys = 0x80000000UL,
  25                 .size = 0x80000000UL,
  26                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  27                          PTE_BLOCK_INNER_SHARE
  28         }, {
  29                 /* List terminator */
  30                 0,
  31         }
  32 };
  33
  34 struct mm_region *mem_map = tegra_mem_map;