include/power/stpmic1.h

   1 /* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
   2 /*
   3  * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
   4  */
   5
   6 #ifndef __PMIC_STPMU1_H_
   7 #define __PMIC_STPMU1_H_
   8
   9 #define STPMU1_MASK_RESET_BUCK          0x18
  10 #define STPMU1_BUCKX_CTRL_REG(buck)     (0x20 + (buck))
  11 #define STPMU1_VREF_CTRL_REG            0x24
  12 #define STPMU1_LDOX_CTRL_REG(ldo)       (0x25 + (ldo))
  13 #define STPMU1_USB_CTRL_REG             0x40
  14 #define STPMU1_NVM_USER_STATUS_REG      0xb8
  15 #define STPMU1_NVM_USER_CONTROL_REG     0xb9
  16
  17 #define STPMU1_MASK_RESET_BUCK3         BIT(2)
  18
  19 #define STPMU1_BUCK_EN                  BIT(0)
  20 #define STPMU1_BUCK_MODE                BIT(1)
  21 #define STPMU1_BUCK_OUTPUT_MASK         GENMASK(7, 2)
  22 #define STPMU1_BUCK_OUTPUT_SHIFT        2
  23 #define STPMU1_BUCK2_1200000V           (24 << STPMU1_BUCK_OUTPUT_SHIFT)
  24 #define STPMU1_BUCK2_1350000V           (30 << STPMU1_BUCK_OUTPUT_SHIFT)
  25 #define STPMU1_BUCK3_1800000V           (39 << STPMU1_BUCK_OUTPUT_SHIFT)
  26
  27 #define STPMU1_VREF_EN                  BIT(0)
  28
  29 #define STPMU1_LDO_EN                   BIT(0)
  30 #define STPMU1_LDO12356_OUTPUT_MASK     GENMASK(6, 2)
  31 #define STPMU1_LDO12356_OUTPUT_SHIFT    2
  32 #define STPMU1_LDO3_MODE                BIT(7)
  33 #define STPMU1_LDO3_DDR_SEL             31
  34 #define STPMU1_LDO3_1800000             (9 << STPMU1_LDO12356_OUTPUT_SHIFT)
  35 #define STPMU1_LDO4_UV                  3300000
  36
  37 #define STPMU1_USB_BOOST_EN             BIT(0)
  38 #define STPMU1_USB_PWR_SW_EN            GENMASK(2, 1)
  39
  40 #define STPMU1_NVM_USER_CONTROL_PROGRAM BIT(0)
  41 #define STPMU1_NVM_USER_CONTROL_READ    BIT(1)
  42
  43 #define STPMU1_NVM_USER_STATUS_BUSY     BIT(0)
  44 #define STPMU1_NVM_USER_STATUS_ERROR    BIT(1)
  45
  46 #define STPMU1_DEFAULT_START_UP_DELAY_MS        1
  47 #define STPMU1_DEFAULT_STOP_DELAY_MS            5
  48 #define STPMU1_USB_BOOST_START_UP_DELAY_MS      10
  49
  50 enum {
  51         STPMU1_BUCK1,
  52         STPMU1_BUCK2,
  53         STPMU1_BUCK3,
  54         STPMU1_BUCK4,
  55         STPMU1_MAX_BUCK,
  56 };
  57
  58 enum {
  59         STPMU1_BUCK_MODE_HP,
  60         STPMU1_BUCK_MODE_LP,
  61 };
  62
  63 enum {
  64         STPMU1_LDO1,
  65         STPMU1_LDO2,
  66         STPMU1_LDO3,
  67         STPMU1_LDO4,
  68         STPMU1_LDO5,
  69         STPMU1_LDO6,
  70         STPMU1_MAX_LDO,
  71 };
  72
  73 enum {
  74         STPMU1_LDO_MODE_NORMAL,
  75         STPMU1_LDO_MODE_BYPASS,
  76         STPMU1_LDO_MODE_SINK_SOURCE,
  77 };
  78
  79 enum {
  80         STPMU1_PWR_SW1,
  81         STPMU1_PWR_SW2,
  82         STPMU1_MAX_PWR_SW,
  83 };
  84
  85 #endif