drivers/net/ti/cpsw.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * CPSW Ethernet Switch Driver
   4  *
   5  * Copyright (C) 2010-2018 Texas Instruments Incorporated - http://www.ti.com/
   6  */
   7
   8 #include <common.h>
   9 #include <command.h>
  10 #include <cpu_func.h>
  11 #include <log.h>
  12 #include <net.h>
  13 #include <miiphy.h>
  14 #include <malloc.h>
  15 #include <net.h>
  16 #include <netdev.h>
  17 #include <cpsw.h>
  18 #include <dm/device_compat.h>
  19 #include <linux/bitops.h>
  20 #include <linux/compiler.h>
  21 #include <linux/errno.h>
  22 #include <asm/gpio.h>
  23 #include <asm/io.h>
  24 #include <phy.h>
  25 #include <asm/arch/cpu.h>
  26 #include <dm.h>
  27
  28 #include "cpsw_mdio.h"
  29
  30 #define BITMASK(bits)           (BIT(bits) - 1)
  31 #define NUM_DESCS               (PKTBUFSRX * 2)
  32 #define PKT_MIN                 60
  33 #define PKT_MAX                 (1500 + 14 + 4 + 4)
  34 #define CLEAR_BIT               1
  35 #define GIGABITEN               BIT(7)
  36 #define FULLDUPLEXEN            BIT(0)
  37 #define MIIEN                   BIT(15)
  38 #define CTL_EXT_EN              BIT(18)
  39 /* DMA Registers */
  40 #define CPDMA_TXCONTROL         0x004
  41 #define CPDMA_RXCONTROL         0x014
  42 #define CPDMA_SOFTRESET         0x01c
  43 #define CPDMA_RXFREE            0x0e0
  44 #define CPDMA_TXHDP_VER1        0x100
  45 #define CPDMA_TXHDP_VER2        0x200
  46 #define CPDMA_RXHDP_VER1        0x120
  47 #define CPDMA_RXHDP_VER2        0x220
  48 #define CPDMA_TXCP_VER1         0x140
  49 #define CPDMA_TXCP_VER2         0x240
  50 #define CPDMA_RXCP_VER1         0x160
  51 #define CPDMA_RXCP_VER2         0x260
  52
  53 /* Descriptor mode bits */
  54 #define CPDMA_DESC_SOP          BIT(31)
  55 #define CPDMA_DESC_EOP          BIT(30)
  56 #define CPDMA_DESC_OWNER        BIT(29)
  57 #define CPDMA_DESC_EOQ          BIT(28)
  58
  59 /*
  60  * This timeout definition is a worst-case ultra defensive measure against
  61  * unexpected controller lock ups.  Ideally, we should never ever hit this
  62  * scenario in practice.
  63  */
  64 #define CPDMA_TIMEOUT           100 /* msecs */
  65
  66 struct cpsw_regs {
  67         u32     id_ver;
  68         u32     control;
  69         u32     soft_reset;
  70         u32     stat_port_en;
  71         u32     ptype;
  72 };
  73
  74 struct cpsw_slave_regs {
  75         u32     max_blks;
  76         u32     blk_cnt;
  77         u32     flow_thresh;
  78         u32     port_vlan;
  79         u32     tx_pri_map;
  80 #ifdef CONFIG_AM33XX
  81         u32     gap_thresh;
  82 #elif defined(CONFIG_TI814X)
  83         u32     ts_ctl;
  84         u32     ts_seq_ltype;
  85         u32     ts_vlan;
  86 #endif
  87         u32     sa_lo;
  88         u32     sa_hi;
  89 };
  90
  91 struct cpsw_host_regs {
  92         u32     max_blks;
  93         u32     blk_cnt;
  94         u32     flow_thresh;
  95         u32     port_vlan;
  96         u32     tx_pri_map;
  97         u32     cpdma_tx_pri_map;
  98         u32     cpdma_rx_chan_map;
  99 };
 100
 101 struct cpsw_sliver_regs {
 102         u32     id_ver;
 103         u32     mac_control;
 104         u32     mac_status;
 105         u32     soft_reset;
 106         u32     rx_maxlen;
 107         u32     __reserved_0;
 108         u32     rx_pause;
 109         u32     tx_pause;
 110         u32     __reserved_1;
 111         u32     rx_pri_map;
 112 };
 113
 114 #define ALE_ENTRY_BITS          68
 115 #define ALE_ENTRY_WORDS         DIV_ROUND_UP(ALE_ENTRY_BITS, 32)
 116
 117 /* ALE Registers */
 118 #define ALE_CONTROL             0x08
 119 #define ALE_UNKNOWNVLAN         0x18
 120 #define ALE_TABLE_CONTROL       0x20
 121 #define ALE_TABLE               0x34
 122 #define ALE_PORTCTL             0x40
 123
 124 #define ALE_TABLE_WRITE         BIT(31)
 125
 126 #define ALE_TYPE_FREE                   0
 127 #define ALE_TYPE_ADDR                   1
 128 #define ALE_TYPE_VLAN                   2
 129 #define ALE_TYPE_VLAN_ADDR              3
 130
 131 #define ALE_UCAST_PERSISTANT            0
 132 #define ALE_UCAST_UNTOUCHED             1
 133 #define ALE_UCAST_OUI                   2
 134 #define ALE_UCAST_TOUCHED               3
 135
 136 #define ALE_MCAST_FWD                   0
 137 #define ALE_MCAST_BLOCK_LEARN_FWD       1
 138 #define ALE_MCAST_FWD_LEARN             2
 139 #define ALE_MCAST_FWD_2                 3
 140
 141 enum cpsw_ale_port_state {
 142         ALE_PORT_STATE_DISABLE  = 0x00,
 143         ALE_PORT_STATE_BLOCK    = 0x01,
 144         ALE_PORT_STATE_LEARN    = 0x02,
 145         ALE_PORT_STATE_FORWARD  = 0x03,
 146 };
 147
 148 /* ALE unicast entry flags - passed into cpsw_ale_add_ucast() */
 149 #define ALE_SECURE      1
 150 #define ALE_BLOCKED     2
 151
 152 struct cpsw_slave {
 153         struct cpsw_slave_regs          *regs;
 154         struct cpsw_sliver_regs         *sliver;
 155         int                             slave_num;
 156         u32                             mac_control;
 157         struct cpsw_slave_data          *data;
 158 };
 159
 160 struct cpdma_desc {
 161         /* hardware fields */
 162         u32                     hw_next;
 163         u32                     hw_buffer;
 164         u32                     hw_len;
 165         u32                     hw_mode;
 166         /* software fields */
 167         u32                     sw_buffer;
 168         u32                     sw_len;
 169 };
 170
 171 struct cpdma_chan {
 172         struct cpdma_desc       *head, *tail;
 173         void                    *hdp, *cp, *rxfree;
 174 };
 175
 176 /* AM33xx SoC specific definitions for the CONTROL port */
 177 #define AM33XX_GMII_SEL_MODE_MII        0
 178 #define AM33XX_GMII_SEL_MODE_RMII       1
 179 #define AM33XX_GMII_SEL_MODE_RGMII      2
 180
 181 #define AM33XX_GMII_SEL_RGMII1_IDMODE   BIT(4)
 182 #define AM33XX_GMII_SEL_RGMII2_IDMODE   BIT(5)
 183 #define AM33XX_GMII_SEL_RMII1_IO_CLK_EN BIT(6)
 184 #define AM33XX_GMII_SEL_RMII2_IO_CLK_EN BIT(7)
 185
 186 #define GMII_SEL_MODE_MASK              0x3
 187
 188 #define desc_write(desc, fld, val)      __raw_writel((u32)(val), &(desc)->fld)
 189 #define desc_read(desc, fld)            __raw_readl(&(desc)->fld)
 190 #define desc_read_ptr(desc, fld)        ((void *)__raw_readl(&(desc)->fld))
 191
 192 #define chan_write(chan, fld, val)      __raw_writel((u32)(val), (chan)->fld)
 193 #define chan_read(chan, fld)            __raw_readl((chan)->fld)
 194 #define chan_read_ptr(chan, fld)        ((void *)__raw_readl((chan)->fld))
 195
 196 #define for_active_slave(slave, priv) \
 197         slave = (priv)->slaves + ((priv)->data)->active_slave; if (slave)
 198 #define for_each_slave(slave, priv) \
 199         for (slave = (priv)->slaves; slave != (priv)->slaves + \
 200                                 ((priv)->data)->slaves; slave++)
 201
 202 struct cpsw_priv {
 203 #ifdef CONFIG_DM_ETH
 204         struct udevice                  *dev;
 205 #else
 206         struct eth_device               *dev;
 207 #endif
 208         struct cpsw_platform_data       *data;
 209         int                             host_port;
 210
 211         struct cpsw_regs                *regs;
 212         void                            *dma_regs;
 213         struct cpsw_host_regs           *host_port_regs;
 214         void                            *ale_regs;
 215
 216         struct cpdma_desc               *descs;
 217         struct cpdma_desc               *desc_free;
 218         struct cpdma_chan               rx_chan, tx_chan;
 219
 220         struct cpsw_slave               *slaves;
 221         struct phy_device               *phydev;
 222         struct mii_dev                  *bus;
 223
 224         u32                             phy_mask;
 225 };
 226
 227 static inline int cpsw_ale_get_field(u32 *ale_entry, u32 start, u32 bits)
 228 {
 229         int idx;
 230
 231         idx    = start / 32;
 232         start -= idx * 32;
 233         idx    = 2 - idx; /* flip */
 234         return (ale_entry[idx] >> start) & BITMASK(bits);
 235 }
 236
 237 static inline void cpsw_ale_set_field(u32 *ale_entry, u32 start, u32 bits,
 238                                       u32 value)
 239 {
 240         int idx;
 241
 242         value &= BITMASK(bits);
 243         idx    = start / 32;
 244         start -= idx * 32;
 245         idx    = 2 - idx; /* flip */
 246         ale_entry[idx] &= ~(BITMASK(bits) << start);
 247         ale_entry[idx] |=  (value << start);
 248 }
 249
 250 #define DEFINE_ALE_FIELD(name, start, bits)                             \
 251 static inline int __maybe_unused cpsw_ale_get_##name(u32 *ale_entry)    \
 252 {                                                                       \
 253         return cpsw_ale_get_field(ale_entry, start, bits);              \
 254 }                                                                       \
 255 static inline void __maybe_unused cpsw_ale_set_##name(u32 *ale_entry, u32 value)        \
 256 {                                                                       \
 257         cpsw_ale_set_field(ale_entry, start, bits, value);              \
 258 }
 259
 260 DEFINE_ALE_FIELD(entry_type,            60,     2)
 261 DEFINE_ALE_FIELD(mcast_state,           62,     2)
 262 DEFINE_ALE_FIELD(port_mask,             66,     3)
 263 DEFINE_ALE_FIELD(ucast_type,            62,     2)
 264 DEFINE_ALE_FIELD(port_num,              66,     2)
 265 DEFINE_ALE_FIELD(blocked,               65,     1)
 266 DEFINE_ALE_FIELD(secure,                64,     1)
 267 DEFINE_ALE_FIELD(mcast,                 40,     1)
 268
 269 /* The MAC address field in the ALE entry cannot be macroized as above */
 270 static inline void cpsw_ale_get_addr(u32 *ale_entry, u8 *addr)
 271 {
 272         int i;
 273
 274         for (i = 0; i < 6; i++)
 275                 addr[i] = cpsw_ale_get_field(ale_entry, 40 - 8*i, 8);
 276 }
 277
 278 static inline void cpsw_ale_set_addr(u32 *ale_entry, const u8 *addr)
 279 {
 280         int i;
 281
 282         for (i = 0; i < 6; i++)
 283                 cpsw_ale_set_field(ale_entry, 40 - 8*i, 8, addr[i]);
 284 }
 285
 286 static int cpsw_ale_read(struct cpsw_priv *priv, int idx, u32 *ale_entry)
 287 {
 288         int i;
 289
 290         __raw_writel(idx, priv->ale_regs + ALE_TABLE_CONTROL);
 291
 292         for (i = 0; i < ALE_ENTRY_WORDS; i++)
 293                 ale_entry[i] = __raw_readl(priv->ale_regs + ALE_TABLE + 4 * i);
 294
 295         return idx;
 296 }
 297
 298 static int cpsw_ale_write(struct cpsw_priv *priv, int idx, u32 *ale_entry)
 299 {
 300         int i;
 301
 302         for (i = 0; i < ALE_ENTRY_WORDS; i++)
 303                 __raw_writel(ale_entry[i], priv->ale_regs + ALE_TABLE + 4 * i);
 304
 305         __raw_writel(idx | ALE_TABLE_WRITE, priv->ale_regs + ALE_TABLE_CONTROL);
 306
 307         return idx;
 308 }
 309
 310 static int cpsw_ale_match_addr(struct cpsw_priv *priv, const u8 *addr)
 311 {
 312         u32 ale_entry[ALE_ENTRY_WORDS];
 313         int type, idx;
 314
 315         for (idx = 0; idx < priv->data->ale_entries; idx++) {
 316                 u8 entry_addr[6];
 317
 318                 cpsw_ale_read(priv, idx, ale_entry);
 319                 type = cpsw_ale_get_entry_type(ale_entry);
 320                 if (type != ALE_TYPE_ADDR && type != ALE_TYPE_VLAN_ADDR)
 321                         continue;
 322                 cpsw_ale_get_addr(ale_entry, entry_addr);
 323                 if (memcmp(entry_addr, addr, 6) == 0)
 324                         return idx;
 325         }
 326         return -ENOENT;
 327 }
 328
 329 static int cpsw_ale_match_free(struct cpsw_priv *priv)
 330 {
 331         u32 ale_entry[ALE_ENTRY_WORDS];
 332         int type, idx;
 333
 334         for (idx = 0; idx < priv->data->ale_entries; idx++) {
 335                 cpsw_ale_read(priv, idx, ale_entry);
 336                 type = cpsw_ale_get_entry_type(ale_entry);
 337                 if (type == ALE_TYPE_FREE)
 338                         return idx;
 339         }
 340         return -ENOENT;
 341 }
 342
 343 static int cpsw_ale_find_ageable(struct cpsw_priv *priv)
 344 {
 345         u32 ale_entry[ALE_ENTRY_WORDS];
 346         int type, idx;
 347
 348         for (idx = 0; idx < priv->data->ale_entries; idx++) {
 349                 cpsw_ale_read(priv, idx, ale_entry);
 350                 type = cpsw_ale_get_entry_type(ale_entry);
 351                 if (type != ALE_TYPE_ADDR && type != ALE_TYPE_VLAN_ADDR)
 352                         continue;
 353                 if (cpsw_ale_get_mcast(ale_entry))
 354                         continue;
 355                 type = cpsw_ale_get_ucast_type(ale_entry);
 356                 if (type != ALE_UCAST_PERSISTANT &&
 357                     type != ALE_UCAST_OUI)
 358                         return idx;
 359         }
 360         return -ENOENT;
 361 }
 362
 363 static int cpsw_ale_add_ucast(struct cpsw_priv *priv, const u8 *addr,
 364                               int port, int flags)
 365 {
 366         u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
 367         int idx;
 368
 369         cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_ADDR);
 370         cpsw_ale_set_addr(ale_entry, addr);
 371         cpsw_ale_set_ucast_type(ale_entry, ALE_UCAST_PERSISTANT);
 372         cpsw_ale_set_secure(ale_entry, (flags & ALE_SECURE) ? 1 : 0);
 373         cpsw_ale_set_blocked(ale_entry, (flags & ALE_BLOCKED) ? 1 : 0);
 374         cpsw_ale_set_port_num(ale_entry, port);
 375
 376         idx = cpsw_ale_match_addr(priv, addr);
 377         if (idx < 0)
 378                 idx = cpsw_ale_match_free(priv);
 379         if (idx < 0)
 380                 idx = cpsw_ale_find_ageable(priv);
 381         if (idx < 0)
 382                 return -ENOMEM;
 383
 384         cpsw_ale_write(priv, idx, ale_entry);
 385         return 0;
 386 }
 387
 388 static int cpsw_ale_add_mcast(struct cpsw_priv *priv, const u8 *addr,
 389                               int port_mask)
 390 {
 391         u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
 392         int idx, mask;
 393
 394         idx = cpsw_ale_match_addr(priv, addr);
 395         if (idx >= 0)
 396                 cpsw_ale_read(priv, idx, ale_entry);
 397
 398         cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_ADDR);
 399         cpsw_ale_set_addr(ale_entry, addr);
 400         cpsw_ale_set_mcast_state(ale_entry, ALE_MCAST_FWD_2);
 401
 402         mask = cpsw_ale_get_port_mask(ale_entry);
 403         port_mask |= mask;
 404         cpsw_ale_set_port_mask(ale_entry, port_mask);
 405
 406         if (idx < 0)
 407                 idx = cpsw_ale_match_free(priv);
 408         if (idx < 0)
 409                 idx = cpsw_ale_find_ageable(priv);
 410         if (idx < 0)
 411                 return -ENOMEM;
 412
 413         cpsw_ale_write(priv, idx, ale_entry);
 414         return 0;
 415 }
 416
 417 static inline void cpsw_ale_control(struct cpsw_priv *priv, int bit, int val)
 418 {
 419         u32 tmp, mask = BIT(bit);
 420
 421         tmp  = __raw_readl(priv->ale_regs + ALE_CONTROL);
 422         tmp &= ~mask;
 423         tmp |= val ? mask : 0;
 424         __raw_writel(tmp, priv->ale_regs + ALE_CONTROL);
 425 }
 426
 427 #define cpsw_ale_enable(priv, val)      cpsw_ale_control(priv, 31, val)
 428 #define cpsw_ale_clear(priv, val)       cpsw_ale_control(priv, 30, val)
 429 #define cpsw_ale_vlan_aware(priv, val)  cpsw_ale_control(priv,  2, val)
 430
 431 static inline void cpsw_ale_port_state(struct cpsw_priv *priv, int port,
 432                                        int val)
 433 {
 434         int offset = ALE_PORTCTL + 4 * port;
 435         u32 tmp, mask = 0x3;
 436
 437         tmp  = __raw_readl(priv->ale_regs + offset);
 438         tmp &= ~mask;
 439         tmp |= val & mask;
 440         __raw_writel(tmp, priv->ale_regs + offset);
 441 }
 442
 443 /* Set a self-clearing bit in a register, and wait for it to clear */
 444 static inline void setbit_and_wait_for_clear32(void *addr)
 445 {
 446         __raw_writel(CLEAR_BIT, addr);
 447         while (__raw_readl(addr) & CLEAR_BIT)
 448                 ;
 449 }
 450
 451 #define mac_hi(mac)     (((mac)[0] << 0) | ((mac)[1] << 8) |    \
 452                          ((mac)[2] << 16) | ((mac)[3] << 24))
 453 #define mac_lo(mac)     (((mac)[4] << 0) | ((mac)[5] << 8))
 454
 455 static void cpsw_set_slave_mac(struct cpsw_slave *slave,
 456                                struct cpsw_priv *priv)
 457 {
 458 #ifdef CONFIG_DM_ETH
 459         struct eth_pdata *pdata = dev_get_plat(priv->dev);
 460
 461         writel(mac_hi(pdata->enetaddr), &slave->regs->sa_hi);
 462         writel(mac_lo(pdata->enetaddr), &slave->regs->sa_lo);
 463 #else
 464         __raw_writel(mac_hi(priv->dev->enetaddr), &slave->regs->sa_hi);
 465         __raw_writel(mac_lo(priv->dev->enetaddr), &slave->regs->sa_lo);
 466 #endif
 467 }
 468
 469 static int cpsw_slave_update_link(struct cpsw_slave *slave,
 470                                    struct cpsw_priv *priv, int *link)
 471 {
 472         struct phy_device *phy;
 473         u32 mac_control = 0;
 474         int ret = -ENODEV;
 475
 476         phy = priv->phydev;
 477         if (!phy)
 478                 goto out;
 479
 480         ret = phy_startup(phy);
 481         if (ret)
 482                 goto out;
 483
 484         if (link)
 485                 *link = phy->link;
 486
 487         if (phy->link) { /* link up */
 488                 mac_control = priv->data->mac_control;
 489                 if (phy->speed == 1000)
 490                         mac_control |= GIGABITEN;
 491                 if (phy->duplex == DUPLEX_FULL)
 492                         mac_control |= FULLDUPLEXEN;
 493                 if (phy->speed == 100)
 494                         mac_control |= MIIEN;
 495                 if (phy->speed == 10 && phy_interface_is_rgmii(phy))
 496                         mac_control |= CTL_EXT_EN;
 497         }
 498
 499         if (mac_control == slave->mac_control)
 500                 goto out;
 501
 502         if (mac_control) {
 503                 printf("link up on port %d, speed %d, %s duplex\n",
 504                                 slave->slave_num, phy->speed,
 505                                 (phy->duplex == DUPLEX_FULL) ? "full" : "half");
 506         } else {
 507                 printf("link down on port %d\n", slave->slave_num);
 508         }
 509
 510         __raw_writel(mac_control, &slave->sliver->mac_control);
 511         slave->mac_control = mac_control;
 512
 513 out:
 514         return ret;
 515 }
 516
 517 static int cpsw_update_link(struct cpsw_priv *priv)
 518 {
 519         int ret = -ENODEV;
 520         struct cpsw_slave *slave;
 521
 522         for_active_slave(slave, priv)
 523                 ret = cpsw_slave_update_link(slave, priv, NULL);
 524
 525         return ret;
 526 }
 527
 528 static inline u32  cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num)
 529 {
 530         if (priv->host_port == 0)
 531                 return slave_num + 1;
 532         else
 533                 return slave_num;
 534 }
 535
 536 static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv)
 537 {
 538         u32     slave_port;
 539
 540         setbit_and_wait_for_clear32(&slave->sliver->soft_reset);
 541
 542         /* setup priority mapping */
 543         __raw_writel(0x76543210, &slave->sliver->rx_pri_map);
 544         __raw_writel(0x33221100, &slave->regs->tx_pri_map);
 545
 546         /* setup max packet size, and mac address */
 547         __raw_writel(PKT_MAX, &slave->sliver->rx_maxlen);
 548         cpsw_set_slave_mac(slave, priv);
 549
 550         slave->mac_control = 0; /* no link yet */
 551
 552         /* enable forwarding */
 553         slave_port = cpsw_get_slave_port(priv, slave->slave_num);
 554         cpsw_ale_port_state(priv, slave_port, ALE_PORT_STATE_FORWARD);
 555
 556         cpsw_ale_add_mcast(priv, net_bcast_ethaddr, 1 << slave_port);
 557
 558         priv->phy_mask |= 1 << slave->data->phy_addr;
 559 }
 560
 561 static struct cpdma_desc *cpdma_desc_alloc(struct cpsw_priv *priv)
 562 {
 563         struct cpdma_desc *desc = priv->desc_free;
 564
 565         if (desc)
 566                 priv->desc_free = desc_read_ptr(desc, hw_next);
 567         return desc;
 568 }
 569
 570 static void cpdma_desc_free(struct cpsw_priv *priv, struct cpdma_desc *desc)
 571 {
 572         if (desc) {
 573                 desc_write(desc, hw_next, priv->desc_free);
 574                 priv->desc_free = desc;
 575         }
 576 }
 577
 578 static int cpdma_submit(struct cpsw_priv *priv, struct cpdma_chan *chan,
 579                         void *buffer, int len)
 580 {
 581         struct cpdma_desc *desc, *prev;
 582         u32 mode;
 583
 584         desc = cpdma_desc_alloc(priv);
 585         if (!desc)
 586                 return -ENOMEM;
 587
 588         if (len < PKT_MIN)
 589                 len = PKT_MIN;
 590
 591         mode = CPDMA_DESC_OWNER | CPDMA_DESC_SOP | CPDMA_DESC_EOP;
 592
 593         desc_write(desc, hw_next,   0);
 594         desc_write(desc, hw_buffer, buffer);
 595         desc_write(desc, hw_len,    len);
 596         desc_write(desc, hw_mode,   mode | len);
 597         desc_write(desc, sw_buffer, buffer);
 598         desc_write(desc, sw_len,    len);
 599
 600         if (!chan->head) {
 601                 /* simple case - first packet enqueued */
 602                 chan->head = desc;
 603                 chan->tail = desc;
 604                 chan_write(chan, hdp, desc);
 605                 goto done;
 606         }
 607
 608         /* not the first packet - enqueue at the tail */
 609         prev = chan->tail;
 610         desc_write(prev, hw_next, desc);
 611         chan->tail = desc;
 612
 613         /* next check if EOQ has been triggered already */
 614         if (desc_read(prev, hw_mode) & CPDMA_DESC_EOQ)
 615                 chan_write(chan, hdp, desc);
 616
 617 done:
 618         if (chan->rxfree)
 619                 chan_write(chan, rxfree, 1);
 620         return 0;
 621 }
 622
 623 static int cpdma_process(struct cpsw_priv *priv, struct cpdma_chan *chan,
 624                          void **buffer, int *len)
 625 {
 626         struct cpdma_desc *desc = chan->head;
 627         u32 status;
 628
 629         if (!desc)
 630                 return -ENOENT;
 631
 632         status = desc_read(desc, hw_mode);
 633
 634         if (len)
 635                 *len = status & 0x7ff;
 636
 637         if (buffer)
 638                 *buffer = desc_read_ptr(desc, sw_buffer);
 639
 640         if (status & CPDMA_DESC_OWNER) {
 641                 if (chan_read(chan, hdp) == 0) {
 642                         if (desc_read(desc, hw_mode) & CPDMA_DESC_OWNER)
 643                                 chan_write(chan, hdp, desc);
 644                 }
 645
 646                 return -EBUSY;
 647         }
 648
 649         chan->head = desc_read_ptr(desc, hw_next);
 650         chan_write(chan, cp, desc);
 651
 652         cpdma_desc_free(priv, desc);
 653         return 0;
 654 }
 655
 656 static int _cpsw_init(struct cpsw_priv *priv, u8 *enetaddr)
 657 {
 658         struct cpsw_slave       *slave;
 659         int i, ret;
 660
 661         /* soft reset the controller and initialize priv */
 662         setbit_and_wait_for_clear32(&priv->regs->soft_reset);
 663
 664         /* initialize and reset the address lookup engine */
 665         cpsw_ale_enable(priv, 1);
 666         cpsw_ale_clear(priv, 1);
 667         cpsw_ale_vlan_aware(priv, 0); /* vlan unaware mode */
 668
 669         /* setup host port priority mapping */
 670         __raw_writel(0x76543210, &priv->host_port_regs->cpdma_tx_pri_map);
 671         __raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map);
 672
 673         /* disable priority elevation and enable statistics on all ports */
 674         __raw_writel(0, &priv->regs->ptype);
 675
 676         /* enable statistics collection only on the host port */
 677         __raw_writel(BIT(priv->host_port), &priv->regs->stat_port_en);
 678         __raw_writel(0x7, &priv->regs->stat_port_en);
 679
 680         cpsw_ale_port_state(priv, priv->host_port, ALE_PORT_STATE_FORWARD);
 681
 682         cpsw_ale_add_ucast(priv, enetaddr, priv->host_port, ALE_SECURE);
 683         cpsw_ale_add_mcast(priv, net_bcast_ethaddr, 1 << priv->host_port);
 684
 685         for_active_slave(slave, priv)
 686                 cpsw_slave_init(slave, priv);
 687
 688         ret = cpsw_update_link(priv);
 689         if (ret)
 690                 goto out;
 691
 692         /* init descriptor pool */
 693         for (i = 0; i < NUM_DESCS; i++) {
 694                 desc_write(&priv->descs[i], hw_next,
 695                            (i == (NUM_DESCS - 1)) ? 0 : &priv->descs[i+1]);
 696         }
 697         priv->desc_free = &priv->descs[0];
 698
 699         /* initialize channels */
 700         if (priv->data->version == CPSW_CTRL_VERSION_2) {
 701                 memset(&priv->rx_chan, 0, sizeof(struct cpdma_chan));
 702                 priv->rx_chan.hdp       = priv->dma_regs + CPDMA_RXHDP_VER2;
 703                 priv->rx_chan.cp        = priv->dma_regs + CPDMA_RXCP_VER2;
 704                 priv->rx_chan.rxfree    = priv->dma_regs + CPDMA_RXFREE;
 705
 706                 memset(&priv->tx_chan, 0, sizeof(struct cpdma_chan));
 707                 priv->tx_chan.hdp       = priv->dma_regs + CPDMA_TXHDP_VER2;
 708                 priv->tx_chan.cp        = priv->dma_regs + CPDMA_TXCP_VER2;
 709         } else {
 710                 memset(&priv->rx_chan, 0, sizeof(struct cpdma_chan));
 711                 priv->rx_chan.hdp       = priv->dma_regs + CPDMA_RXHDP_VER1;
 712                 priv->rx_chan.cp        = priv->dma_regs + CPDMA_RXCP_VER1;
 713                 priv->rx_chan.rxfree    = priv->dma_regs + CPDMA_RXFREE;
 714
 715                 memset(&priv->tx_chan, 0, sizeof(struct cpdma_chan));
 716                 priv->tx_chan.hdp       = priv->dma_regs + CPDMA_TXHDP_VER1;
 717                 priv->tx_chan.cp        = priv->dma_regs + CPDMA_TXCP_VER1;
 718         }
 719
 720         /* clear dma state */
 721         setbit_and_wait_for_clear32(priv->dma_regs + CPDMA_SOFTRESET);
 722
 723         if (priv->data->version == CPSW_CTRL_VERSION_2) {
 724                 for (i = 0; i < priv->data->channels; i++) {
 725                         __raw_writel(0, priv->dma_regs + CPDMA_RXHDP_VER2 + 4
 726                                         * i);
 727                         __raw_writel(0, priv->dma_regs + CPDMA_RXFREE + 4
 728                                         * i);
 729                         __raw_writel(0, priv->dma_regs + CPDMA_RXCP_VER2 + 4
 730                                         * i);
 731                         __raw_writel(0, priv->dma_regs + CPDMA_TXHDP_VER2 + 4
 732                                         * i);
 733                         __raw_writel(0, priv->dma_regs + CPDMA_TXCP_VER2 + 4
 734                                         * i);
 735                 }
 736         } else {
 737                 for (i = 0; i < priv->data->channels; i++) {
 738                         __raw_writel(0, priv->dma_regs + CPDMA_RXHDP_VER1 + 4
 739                                         * i);
 740                         __raw_writel(0, priv->dma_regs + CPDMA_RXFREE + 4
 741                                         * i);
 742                         __raw_writel(0, priv->dma_regs + CPDMA_RXCP_VER1 + 4
 743                                         * i);
 744                         __raw_writel(0, priv->dma_regs + CPDMA_TXHDP_VER1 + 4
 745                                         * i);
 746                         __raw_writel(0, priv->dma_regs + CPDMA_TXCP_VER1 + 4
 747                                         * i);
 748
 749                 }
 750         }
 751
 752         __raw_writel(1, priv->dma_regs + CPDMA_TXCONTROL);
 753         __raw_writel(1, priv->dma_regs + CPDMA_RXCONTROL);
 754
 755         /* submit rx descs */
 756         for (i = 0; i < PKTBUFSRX; i++) {
 757                 ret = cpdma_submit(priv, &priv->rx_chan, net_rx_packets[i],
 758                                    PKTSIZE);
 759                 if (ret < 0) {
 760                         printf("error %d submitting rx desc\n", ret);
 761                         break;
 762                 }
 763         }
 764
 765 out:
 766         return ret;
 767 }
 768
 769 static int cpsw_reap_completed_packets(struct cpsw_priv *priv)
 770 {
 771         int timeout = CPDMA_TIMEOUT;
 772
 773         /* reap completed packets */
 774         while (timeout-- &&
 775                (cpdma_process(priv, &priv->tx_chan, NULL, NULL) >= 0))
 776                 ;
 777
 778         return timeout;
 779 }
 780
 781 static void _cpsw_halt(struct cpsw_priv *priv)
 782 {
 783         cpsw_reap_completed_packets(priv);
 784
 785         writel(0, priv->dma_regs + CPDMA_TXCONTROL);
 786         writel(0, priv->dma_regs + CPDMA_RXCONTROL);
 787
 788         /* soft reset the controller and initialize priv */
 789         setbit_and_wait_for_clear32(&priv->regs->soft_reset);
 790
 791         /* clear dma state */
 792         setbit_and_wait_for_clear32(priv->dma_regs + CPDMA_SOFTRESET);
 793
 794 }
 795
 796 static int _cpsw_send(struct cpsw_priv *priv, void *packet, int length)
 797 {
 798         int timeout;
 799
 800         flush_dcache_range((unsigned long)packet,
 801                            (unsigned long)packet + ALIGN(length, PKTALIGN));
 802
 803         timeout = cpsw_reap_completed_packets(priv);
 804         if (timeout == -1) {
 805                 printf("cpdma_process timeout\n");
 806                 return -ETIMEDOUT;
 807         }
 808
 809         return cpdma_submit(priv, &priv->tx_chan, packet, length);
 810 }
 811
 812 static int _cpsw_recv(struct cpsw_priv *priv, uchar **pkt)
 813 {
 814         void *buffer;
 815         int len;
 816         int ret;
 817
 818         ret = cpdma_process(priv, &priv->rx_chan, &buffer, &len);
 819         if (ret < 0)
 820                 return ret;
 821
 822         invalidate_dcache_range((unsigned long)buffer,
 823                                 (unsigned long)buffer + PKTSIZE_ALIGN);
 824         *pkt = buffer;
 825
 826         return len;
 827 }
 828
 829 static void cpsw_slave_setup(struct cpsw_slave *slave, int slave_num,
 830                             struct cpsw_priv *priv)
 831 {
 832         void                    *regs = priv->regs;
 833         struct cpsw_slave_data  *data = priv->data->slave_data + slave_num;
 834         slave->slave_num = slave_num;
 835         slave->data     = data;
 836         slave->regs     = regs + data->slave_reg_ofs;
 837         slave->sliver   = regs + data->sliver_reg_ofs;
 838 }
 839
 840 static int cpsw_phy_init(struct cpsw_priv *priv, struct cpsw_slave *slave)
 841 {
 842         struct phy_device *phydev;
 843         u32 supported = PHY_GBIT_FEATURES;
 844         int ret;
 845
 846         phydev = phy_connect(priv->bus,
 847                         slave->data->phy_addr,
 848                         priv->dev,
 849                         slave->data->phy_if);
 850
 851         if (!phydev)
 852                 return -1;
 853
 854         phydev->supported &= supported;
 855         if (slave->data->max_speed) {
 856                 ret = phy_set_supported(phydev, slave->data->max_speed);
 857                 if (ret)
 858                         return ret;
 859 #if CONFIG_IS_ENABLED(DM_ETH)
 860                 dev_dbg(priv->dev, "Port %u speed forced to %uMbit\n",
 861                         slave->slave_num + 1, slave->data->max_speed);
 862 #else
 863                 log_debug("%s: Port %u speed forced to %uMbit\n",
 864                           priv->dev->name, slave->slave_num + 1,
 865                           slave->data->max_speed);
 866 #endif
 867         }
 868         phydev->advertising = phydev->supported;
 869
 870 #ifdef CONFIG_DM_ETH
 871         if (ofnode_valid(slave->data->phy_of_handle))
 872                 phydev->node = slave->data->phy_of_handle;
 873 #endif
 874
 875         priv->phydev = phydev;
 876         phy_config(phydev);
 877
 878         return 1;
 879 }
 880
 881 static void cpsw_phy_addr_update(struct cpsw_priv *priv)
 882 {
 883         struct cpsw_platform_data *data = priv->data;
 884         u16 alive = cpsw_mdio_get_alive(priv->bus);
 885         int active = data->active_slave;
 886         int new_addr = ffs(alive) - 1;
 887
 888         /*
 889          * If there is only one phy alive and its address does not match
 890          * that of active slave, then phy address can safely be updated.
 891          */
 892         if (hweight16(alive) == 1 &&
 893             data->slave_data[active].phy_addr != new_addr) {
 894                 printf("Updated phy address for CPSW#%d, old: %d, new: %d\n",
 895                        active, data->slave_data[active].phy_addr, new_addr);
 896                 data->slave_data[active].phy_addr = new_addr;
 897         }
 898 }
 899
 900 int _cpsw_register(struct cpsw_priv *priv)
 901 {
 902         struct cpsw_slave       *slave;
 903         struct cpsw_platform_data *data = priv->data;
 904         void                    *regs = (void *)data->cpsw_base;
 905
 906         priv->slaves = malloc(sizeof(struct cpsw_slave) * data->slaves);
 907         if (!priv->slaves) {
 908                 return -ENOMEM;
 909         }
 910
 911         priv->host_port         = data->host_port_num;
 912         priv->regs              = regs;
 913         priv->host_port_regs    = regs + data->host_port_reg_ofs;
 914         priv->dma_regs          = regs + data->cpdma_reg_ofs;
 915         priv->ale_regs          = regs + data->ale_reg_ofs;
 916         priv->descs             = (void *)regs + data->bd_ram_ofs;
 917
 918         int idx = 0;
 919
 920         for_each_slave(slave, priv) {
 921                 cpsw_slave_setup(slave, idx, priv);
 922                 idx = idx + 1;
 923         }
 924
 925         priv->bus = cpsw_mdio_init(priv->dev->name, data->mdio_base, 0, 0);
 926         if (!priv->bus)
 927                 return -EFAULT;
 928
 929         cpsw_phy_addr_update(priv);
 930
 931         for_active_slave(slave, priv)
 932                 cpsw_phy_init(priv, slave);
 933
 934         return 0;
 935 }
 936
 937 #ifndef CONFIG_DM_ETH
 938 static int cpsw_init(struct eth_device *dev, struct bd_info *bis)
 939 {
 940         struct cpsw_priv        *priv = dev->priv;
 941
 942         return _cpsw_init(priv, dev->enetaddr);
 943 }
 944
 945 static void cpsw_halt(struct eth_device *dev)
 946 {
 947         struct cpsw_priv *priv = dev->priv;
 948
 949         return _cpsw_halt(priv);
 950 }
 951
 952 static int cpsw_send(struct eth_device *dev, void *packet, int length)
 953 {
 954         struct cpsw_priv        *priv = dev->priv;
 955
 956         return _cpsw_send(priv, packet, length);
 957 }
 958
 959 static int cpsw_recv(struct eth_device *dev)
 960 {
 961         struct cpsw_priv *priv = dev->priv;
 962         uchar *pkt = NULL;
 963         int len;
 964
 965         len = _cpsw_recv(priv, &pkt);
 966
 967         if (len > 0) {
 968                 net_process_received_packet(pkt, len);
 969                 cpdma_submit(priv, &priv->rx_chan, pkt, PKTSIZE);
 970         }
 971
 972         return len;
 973 }
 974
 975 int cpsw_register(struct cpsw_platform_data *data)
 976 {
 977         struct cpsw_priv        *priv;
 978         struct eth_device       *dev;
 979         int ret;
 980
 981         dev = calloc(sizeof(*dev), 1);
 982         if (!dev)
 983                 return -ENOMEM;
 984
 985         priv = calloc(sizeof(*priv), 1);
 986         if (!priv) {
 987                 free(dev);
 988                 return -ENOMEM;
 989         }
 990
 991         priv->dev = dev;
 992         priv->data = data;
 993
 994         strcpy(dev->name, "cpsw");
 995         dev->iobase     = 0;
 996         dev->init       = cpsw_init;
 997         dev->halt       = cpsw_halt;
 998         dev->send       = cpsw_send;
 999         dev->recv       = cpsw_recv;
1000         dev->priv       = priv;
1001
1002         eth_register(dev);
1003
1004         ret = _cpsw_register(priv);
1005         if (ret < 0) {
1006                 eth_unregister(dev);
1007                 free(dev);
1008                 free(priv);
1009                 return ret;
1010         }
1011
1012         return 1;
1013 }
1014 #else
1015 static int cpsw_eth_start(struct udevice *dev)
1016 {
1017         struct eth_pdata *pdata = dev_get_plat(dev);
1018         struct cpsw_priv *priv = dev_get_priv(dev);
1019
1020         return _cpsw_init(priv, pdata->enetaddr);
1021 }
1022
1023 static int cpsw_eth_send(struct udevice *dev, void *packet, int length)
1024 {
1025         struct cpsw_priv *priv = dev_get_priv(dev);
1026
1027         return _cpsw_send(priv, packet, length);
1028 }
1029
1030 static int cpsw_eth_recv(struct udevice *dev, int flags, uchar **packetp)
1031 {
1032         struct cpsw_priv *priv = dev_get_priv(dev);
1033
1034         return _cpsw_recv(priv, packetp);
1035 }
1036
1037 static int cpsw_eth_free_pkt(struct udevice *dev, uchar *packet,
1038                                    int length)
1039 {
1040         struct cpsw_priv *priv = dev_get_priv(dev);
1041
1042         return cpdma_submit(priv, &priv->rx_chan, packet, PKTSIZE);
1043 }
1044
1045 static void cpsw_eth_stop(struct udevice *dev)
1046 {
1047         struct cpsw_priv *priv = dev_get_priv(dev);
1048
1049         return _cpsw_halt(priv);
1050 }
1051
1052 static const struct eth_ops cpsw_eth_ops = {
1053         .start          = cpsw_eth_start,
1054         .send           = cpsw_eth_send,
1055         .recv           = cpsw_eth_recv,
1056         .free_pkt       = cpsw_eth_free_pkt,
1057         .stop           = cpsw_eth_stop,
1058 };
1059
1060 static void cpsw_gmii_sel_am3352(struct cpsw_priv *priv,
1061                                  phy_interface_t phy_mode)
1062 {
1063         u32 reg;
1064         u32 mask;
1065         u32 mode = 0;
1066         bool rgmii_id = false;
1067         int slave = priv->data->active_slave;
1068
1069         reg = readl(priv->data->gmii_sel);
1070
1071         switch (phy_mode) {
1072         case PHY_INTERFACE_MODE_RMII:
1073                 mode = AM33XX_GMII_SEL_MODE_RMII;
1074                 break;
1075
1076         case PHY_INTERFACE_MODE_RGMII:
1077         case PHY_INTERFACE_MODE_RGMII_RXID:
1078                 mode = AM33XX_GMII_SEL_MODE_RGMII;
1079                 break;
1080         case PHY_INTERFACE_MODE_RGMII_ID:
1081         case PHY_INTERFACE_MODE_RGMII_TXID:
1082                 mode = AM33XX_GMII_SEL_MODE_RGMII;
1083                 rgmii_id = true;
1084                 break;
1085
1086         case PHY_INTERFACE_MODE_MII:
1087         default:
1088                 mode = AM33XX_GMII_SEL_MODE_MII;
1089                 break;
1090         };
1091
1092         mask = GMII_SEL_MODE_MASK << (slave * 2) | BIT(slave + 6);
1093         mode <<= slave * 2;
1094
1095         if (priv->data->rmii_clock_external) {
1096                 if (slave == 0)
1097                         mode |= AM33XX_GMII_SEL_RMII1_IO_CLK_EN;
1098                 else
1099                         mode |= AM33XX_GMII_SEL_RMII2_IO_CLK_EN;
1100         }
1101
1102         if (rgmii_id) {
1103                 if (slave == 0)
1104                         mode |= AM33XX_GMII_SEL_RGMII1_IDMODE;
1105                 else
1106                         mode |= AM33XX_GMII_SEL_RGMII2_IDMODE;
1107         }
1108
1109         reg &= ~mask;
1110         reg |= mode;
1111
1112         writel(reg, priv->data->gmii_sel);
1113 }
1114
1115 static void cpsw_gmii_sel_dra7xx(struct cpsw_priv *priv,
1116                                  phy_interface_t phy_mode)
1117 {
1118         u32 reg;
1119         u32 mask;
1120         u32 mode = 0;
1121         int slave = priv->data->active_slave;
1122
1123         reg = readl(priv->data->gmii_sel);
1124
1125         switch (phy_mode) {
1126         case PHY_INTERFACE_MODE_RMII:
1127                 mode = AM33XX_GMII_SEL_MODE_RMII;
1128                 break;
1129
1130         case PHY_INTERFACE_MODE_RGMII:
1131         case PHY_INTERFACE_MODE_RGMII_ID:
1132         case PHY_INTERFACE_MODE_RGMII_RXID:
1133         case PHY_INTERFACE_MODE_RGMII_TXID:
1134                 mode = AM33XX_GMII_SEL_MODE_RGMII;
1135                 break;
1136
1137         case PHY_INTERFACE_MODE_MII:
1138         default:
1139                 mode = AM33XX_GMII_SEL_MODE_MII;
1140                 break;
1141         };
1142
1143         switch (slave) {
1144         case 0:
1145                 mask = GMII_SEL_MODE_MASK;
1146                 break;
1147         case 1:
1148                 mask = GMII_SEL_MODE_MASK << 4;
1149                 mode <<= 4;
1150                 break;
1151         default:
1152                 dev_err(priv->dev, "invalid slave number...\n");
1153                 return;
1154         }
1155
1156         if (priv->data->rmii_clock_external)
1157                 dev_err(priv->dev, "RMII External clock is not supported\n");
1158
1159         reg &= ~mask;
1160         reg |= mode;
1161
1162         writel(reg, priv->data->gmii_sel);
1163 }
1164
1165 static void cpsw_phy_sel(struct cpsw_priv *priv, const char *compat,
1166                          phy_interface_t phy_mode)
1167 {
1168         if (!strcmp(compat, "ti,am3352-cpsw-phy-sel"))
1169                 cpsw_gmii_sel_am3352(priv, phy_mode);
1170         if (!strcmp(compat, "ti,am43xx-cpsw-phy-sel"))
1171                 cpsw_gmii_sel_am3352(priv, phy_mode);
1172         else if (!strcmp(compat, "ti,dra7xx-cpsw-phy-sel"))
1173                 cpsw_gmii_sel_dra7xx(priv, phy_mode);
1174 }
1175
1176 static int cpsw_eth_probe(struct udevice *dev)
1177 {
1178         struct cpsw_priv *priv = dev_get_priv(dev);
1179         struct eth_pdata *pdata = dev_get_plat(dev);
1180
1181         priv->dev = dev;
1182         priv->data = pdata->priv_pdata;
1183         ti_cm_get_macid(dev, priv->data, pdata->enetaddr);
1184         /* Select phy interface in control module */
1185         cpsw_phy_sel(priv, priv->data->phy_sel_compat,
1186                      pdata->phy_interface);
1187
1188         return _cpsw_register(priv);
1189 }
1190
1191 #if CONFIG_IS_ENABLED(OF_CONTROL)
1192 static void cpsw_eth_of_parse_slave(struct cpsw_platform_data *data,
1193                                     int slave_index, ofnode subnode)
1194 {
1195         struct ofnode_phandle_args out_args;
1196         struct cpsw_slave_data *slave_data;
1197         const char *phy_mode;
1198         u32 phy_id[2];
1199         int ret;
1200
1201         slave_data = &data->slave_data[slave_index];
1202
1203         phy_mode = ofnode_read_string(subnode, "phy-mode");
1204         if (phy_mode)
1205                 slave_data->phy_if = phy_get_interface_by_name(phy_mode);
1206
1207         ret = ofnode_parse_phandle_with_args(subnode, "phy-handle",
1208                                              NULL, 0, 0, &out_args);
1209         if (!ret) {
1210                 slave_data->phy_of_handle = out_args.node;
1211
1212                 ret = ofnode_read_s32(slave_data->phy_of_handle, "reg",
1213                                       &slave_data->phy_addr);
1214                 if (ret)
1215                         printf("error: phy addr not found in dt\n");
1216         } else {
1217                 ret = ofnode_read_u32_array(subnode, "phy_id", phy_id, 2);
1218                 if (ret)
1219                         printf("error: phy_id read failed\n");
1220         }
1221
1222         slave_data->max_speed = ofnode_read_s32_default(subnode,
1223                                                         "max-speed", 0);
1224 }
1225
1226 static int cpsw_eth_of_to_plat(struct udevice *dev)
1227 {
1228         struct eth_pdata *pdata = dev_get_plat(dev);
1229         struct cpsw_platform_data *data;
1230         struct gpio_desc *mode_gpios;
1231         int slave_index = 0;
1232         int num_mode_gpios;
1233         ofnode subnode;
1234         int ret;
1235
1236         data = calloc(1, sizeof(struct cpsw_platform_data));
1237         if (!data)
1238                 return -ENOMEM;
1239
1240         pdata->priv_pdata = data;
1241         pdata->iobase = dev_read_addr(dev);
1242         data->version = CPSW_CTRL_VERSION_2;
1243         data->bd_ram_ofs = CPSW_BD_OFFSET;
1244         data->ale_reg_ofs = CPSW_ALE_OFFSET;
1245         data->cpdma_reg_ofs = CPSW_CPDMA_OFFSET;
1246         data->mdio_div = CPSW_MDIO_DIV;
1247         data->host_port_reg_ofs = CPSW_HOST_PORT_OFFSET,
1248
1249         pdata->phy_interface = -1;
1250
1251         data->cpsw_base = pdata->iobase;
1252
1253         ret = dev_read_s32(dev, "cpdma_channels", &data->channels);
1254         if (ret) {
1255                 printf("error: cpdma_channels not found in dt\n");
1256                 return ret;
1257         }
1258
1259         ret = dev_read_s32(dev, "slaves", &data->slaves);
1260         if (ret) {
1261                 printf("error: slaves not found in dt\n");
1262                 return ret;
1263         }
1264         data->slave_data = malloc(sizeof(struct cpsw_slave_data) *
1265                                        data->slaves);
1266
1267         ret = dev_read_s32(dev, "ale_entries", &data->ale_entries);
1268         if (ret) {
1269                 printf("error: ale_entries not found in dt\n");
1270                 return ret;
1271         }
1272
1273         ret = dev_read_u32(dev, "bd_ram_size", &data->bd_ram_ofs);
1274         if (ret) {
1275                 printf("error: bd_ram_size not found in dt\n");
1276                 return ret;
1277         }
1278
1279         ret = dev_read_u32(dev, "mac_control", &data->mac_control);
1280         if (ret) {
1281                 printf("error: ale_entries not found in dt\n");
1282                 return ret;
1283         }
1284
1285         num_mode_gpios = gpio_get_list_count(dev, "mode-gpios");
1286         if (num_mode_gpios > 0) {
1287                 mode_gpios = malloc(sizeof(struct gpio_desc) *
1288                                     num_mode_gpios);
1289                 gpio_request_list_by_name(dev, "mode-gpios", mode_gpios,
1290                                           num_mode_gpios, GPIOD_IS_OUT);
1291                 free(mode_gpios);
1292         }
1293
1294         data->active_slave = dev_read_u32_default(dev, "active_slave", 0);
1295
1296         ofnode_for_each_subnode(subnode, dev_ofnode(dev)) {
1297                 const char *name;
1298
1299                 name = ofnode_get_name(subnode);
1300                 if (!strncmp(name, "mdio", 4)) {
1301                         data->mdio_base = ofnode_get_addr(subnode);
1302                         if (data->mdio_base == FDT_ADDR_T_NONE) {
1303                                 pr_err("Not able to get MDIO address space\n");
1304                                 return -ENOENT;
1305                         }
1306                 }
1307
1308                 if (!strncmp(name, "slave", 5)) {
1309                         if (slave_index >= data->slaves)
1310                                 continue;
1311
1312                         cpsw_eth_of_parse_slave(data, slave_index, subnode);
1313                         slave_index++;
1314                 }
1315
1316                 if (!strncmp(name, "cpsw-phy-sel", 12)) {
1317                         data->gmii_sel = ofnode_get_addr(subnode);
1318
1319                         if (data->gmii_sel == FDT_ADDR_T_NONE) {
1320                                 pr_err("Not able to get gmii_sel reg address\n");
1321                                 return -ENOENT;
1322                         }
1323
1324                         if (ofnode_read_bool(subnode, "rmii-clock-ext"))
1325                                 data->rmii_clock_external = true;
1326
1327                         data->phy_sel_compat = ofnode_read_string(subnode,
1328                                                                   "compatible");
1329                         if (!data->phy_sel_compat) {
1330                                 pr_err("Not able to get gmii_sel compatible\n");
1331                                 return -ENOENT;
1332                         }
1333                 }
1334         }
1335
1336         data->slave_data[0].slave_reg_ofs = CPSW_SLAVE0_OFFSET;
1337         data->slave_data[0].sliver_reg_ofs = CPSW_SLIVER0_OFFSET;
1338
1339         if (data->slaves == 2) {
1340                 data->slave_data[1].slave_reg_ofs = CPSW_SLAVE1_OFFSET;
1341                 data->slave_data[1].sliver_reg_ofs = CPSW_SLIVER1_OFFSET;
1342         }
1343
1344         ret = ti_cm_get_macid_addr(dev, data->active_slave, data);
1345         if (ret < 0) {
1346                 pr_err("cpsw read efuse mac failed\n");
1347                 return ret;
1348         }
1349
1350         pdata->phy_interface = data->slave_data[data->active_slave].phy_if;
1351         if (pdata->phy_interface == -1) {
1352                 debug("%s: Invalid PHY interface '%s'\n", __func__,
1353                       phy_string_for_interface(pdata->phy_interface));
1354                 return -EINVAL;
1355         }
1356
1357         return 0;
1358 }
1359
1360 static const struct udevice_id cpsw_eth_ids[] = {
1361         { .compatible = "ti,cpsw" },
1362         { .compatible = "ti,am335x-cpsw" },
1363         { }
1364 };
1365 #endif
1366
1367 int cpsw_get_slave_phy_addr(struct udevice *dev, int slave)
1368 {
1369         struct cpsw_priv *priv = dev_get_priv(dev);
1370         struct cpsw_platform_data *data = priv->data;
1371
1372         return data->slave_data[slave].phy_addr;
1373 }
1374
1375 U_BOOT_DRIVER(eth_cpsw) = {
1376         .name   = "eth_cpsw",
1377         .id     = UCLASS_ETH,
1378 #if CONFIG_IS_ENABLED(OF_CONTROL)
1379         .of_match = cpsw_eth_ids,
1380         .of_to_plat = cpsw_eth_of_to_plat,
1381         .plat_auto      = sizeof(struct eth_pdata),
1382 #endif
1383         .probe  = cpsw_eth_probe,
1384         .ops    = &cpsw_eth_ops,
1385         .priv_auto      = sizeof(struct cpsw_priv),
1386         .flags = DM_FLAG_ALLOC_PRIV_DMA | DM_FLAG_PRE_RELOC,
1387 };
1388 #endif /* CONFIG_DM_ETH */