1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2018 Allied Telesis Labs
10 * High Level Configuration Options (easy to change)
13 #define CONFIG_DISPLAY_BOARDINFO_LATE
15 #define CONFIG_SYS_TCLK 250000000 /* 250MHz */
18 * NS16550 Configuration
20 #define CONFIG_SYS_NS16550_SERIAL
21 #define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK
22 #if !defined(CONFIG_DM_SERIAL)
23 #define CONFIG_SYS_NS16550_REG_SIZE (-4)
24 #define CONFIG_SYS_NS16550_COM1 MV_UART_CONSOLE_BASE
28 * Serial Port configuration
29 * The following definitions let you select what serial you want to use
30 * for your console driver.
33 #define CONFIG_CONS_INDEX 1 /*Console on UART0 */
36 * Commands configuration
38 #define CONFIG_CMD_PCI
41 #define CONFIG_SYS_NAND_ONFI_DETECTION
42 #define CONFIG_SYS_MAX_NAND_DEVICE 1
44 #define BBT_CUSTOM_SCAN
45 #define BBT_CUSTOM_SCAN_PAGE 0
46 #define BBT_CUSTOM_SCAN_POSITION 2048
48 /* SPI NOR flash default params, used by sf commands */
50 #define MTDIDS_DEFAULT "nand0=nand"
51 #define MTDPARTS_DEFAULT "mtdparts=nand:240M(user),8M(errlog),8M(nand-bbt)"
52 #define MTDPARTS_MTDOOPS "errlog"
54 /* Partition support */
56 /* Additional FS support/configuration */
58 /* USB/EHCI configuration */
59 #define CONFIG_EHCI_IS_TDI
61 /* Environment in SPI NOR flash */
63 #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
66 #ifndef CONFIG_SPL_BUILD
67 #define CONFIG_PCI_SCAN_SHOW
71 #define CONFIG_SYS_NAND_ONFI_DETECTION
72 #define CONFIG_CMD_UBI
73 #define CONFIG_CMD_UBIFS
74 #define CONFIG_CMD_MTDPARTS
76 #define CONFIG_SYS_MALLOC_LEN (4 << 20)
78 #include <asm/arch/config.h>
81 * Other required minimal configurations
83 #define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */
85 /* Keep device tree and initrd in low memory so the kernel can access them */
86 #define CONFIG_EXTRA_ENV_SETTINGS \
87 "fdt_high=0x10000000\0" \
88 "initrd_high=0x10000000\0"
90 #define CONFIG_SYS_LOAD_ADDR 0x1000000
91 #define CONFIG_UBI_PART user
92 #define CONFIG_UBIFS_VOLUME user
97 #define CONFIG_SPL_SIZE (140 << 10)
98 #define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_SIZE - 0x0030)
100 #define CONFIG_SPL_BSS_START_ADDR (0x40000000 + CONFIG_SPL_SIZE)
101 #define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
103 #ifdef CONFIG_SPL_BUILD
104 #define CONFIG_SYS_MALLOC_SIMPLE
107 #define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
108 #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
110 /* SPL related SPI defines */
111 #define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
113 #endif /* _CONFIG_X530_H */