2 * Copyright 2016 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <fsl_dtsec.h>
14 #include "../common/fman.h"
16 int board_eth_init(bd_t *bis)
18 #ifdef CONFIG_FMAN_ENET
20 struct memac_mdio_info dtsec_mdio_info;
21 struct memac_mdio_info tgec_mdio_info;
24 struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
26 srds_s1 = in_be32(&gur->rcwsr[4]) &
27 FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
28 srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
30 dtsec_mdio_info.regs =
31 (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
33 dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
35 /* Register the 1G MDIO bus */
36 fm_memac_mdio_init(bis, &dtsec_mdio_info);
39 (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
40 tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
42 /* Register the 10G MDIO bus */
43 fm_memac_mdio_init(bis, &tgec_mdio_info);
45 /* Set the two on-board RGMII PHY address */
46 fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR);
47 fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR);
49 /* Set the two on-board SGMII PHY address */
50 fm_info_set_phy_address(FM1_DTSEC5, SGMII_PHY1_ADDR);
51 fm_info_set_phy_address(FM1_DTSEC6, SGMII_PHY2_ADDR);
53 /* Set the on-board AQ PHY address */
54 fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
60 printf("Invalid SerDes protocol 0x%x for LS1046ARDB\n",
65 dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
66 for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++)
67 fm_info_set_mdio(i, dev);
69 /* XFI on lane A, MAC 9 */
70 dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
71 fm_info_set_mdio(FM1_10GEC1, dev);
76 return pci_eth_init(bis);