drivers/mmc/sdhci-cadence.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2016 Socionext Inc.
   4  *   Author: Masahiro Yamada <[email protected]>
   5  */
   6
   7 #include <common.h>
   8 #include <dm.h>
   9 #include <dm/device_compat.h>
  10 #include <linux/bitfield.h>
  11 #include <linux/bitops.h>
  12 #include <linux/bug.h>
  13 #include <linux/io.h>
  14 #include <linux/iopoll.h>
  15 #include <linux/sizes.h>
  16 #include <linux/libfdt.h>
  17 #include <mmc.h>
  18 #include <sdhci.h>
  19
  20 /* HRS - Host Register Set (specific to Cadence) */
  21 #define SDHCI_CDNS_HRS04                0x10            /* PHY access port */
  22 #define   SDHCI_CDNS_HRS04_ACK                  BIT(26)
  23 #define   SDHCI_CDNS_HRS04_RD                   BIT(25)
  24 #define   SDHCI_CDNS_HRS04_WR                   BIT(24)
  25 #define   SDHCI_CDNS_HRS04_RDATA                GENMASK(23, 16)
  26 #define   SDHCI_CDNS_HRS04_WDATA                GENMASK(15, 8)
  27 #define   SDHCI_CDNS_HRS04_ADDR                 GENMASK(5, 0)
  28
  29 #define SDHCI_CDNS_HRS06                0x18            /* eMMC control */
  30 #define   SDHCI_CDNS_HRS06_TUNE_UP              BIT(15)
  31 #define   SDHCI_CDNS_HRS06_TUNE                 GENMASK(13, 8)
  32 #define   SDHCI_CDNS_HRS06_MODE                 GENMASK(2, 0)
  33 #define   SDHCI_CDNS_HRS06_MODE_SD              0x0
  34 #define   SDHCI_CDNS_HRS06_MODE_MMC_SDR         0x2
  35 #define   SDHCI_CDNS_HRS06_MODE_MMC_DDR         0x3
  36 #define   SDHCI_CDNS_HRS06_MODE_MMC_HS200       0x4
  37 #define   SDHCI_CDNS_HRS06_MODE_MMC_HS400       0x5
  38 #define   SDHCI_CDNS_HRS06_MODE_MMC_HS400ES     0x6
  39
  40 /* SRS - Slot Register Set (SDHCI-compatible) */
  41 #define SDHCI_CDNS_SRS_BASE             0x200
  42
  43 /* PHY */
  44 #define SDHCI_CDNS_PHY_DLY_SD_HS        0x00
  45 #define SDHCI_CDNS_PHY_DLY_SD_DEFAULT   0x01
  46 #define SDHCI_CDNS_PHY_DLY_UHS_SDR12    0x02
  47 #define SDHCI_CDNS_PHY_DLY_UHS_SDR25    0x03
  48 #define SDHCI_CDNS_PHY_DLY_UHS_SDR50    0x04
  49 #define SDHCI_CDNS_PHY_DLY_UHS_DDR50    0x05
  50 #define SDHCI_CDNS_PHY_DLY_EMMC_LEGACY  0x06
  51 #define SDHCI_CDNS_PHY_DLY_EMMC_SDR     0x07
  52 #define SDHCI_CDNS_PHY_DLY_EMMC_DDR     0x08
  53 #define SDHCI_CDNS_PHY_DLY_SDCLK        0x0b
  54 #define SDHCI_CDNS_PHY_DLY_HSMMC        0x0c
  55 #define SDHCI_CDNS_PHY_DLY_STROBE       0x0d
  56
  57 /*
  58  * The tuned val register is 6 bit-wide, but not the whole of the range is
  59  * available.  The range 0-42 seems to be available (then 43 wraps around to 0)
  60  * but I am not quite sure if it is official.  Use only 0 to 39 for safety.
  61  */
  62 #define SDHCI_CDNS_MAX_TUNING_LOOP      40
  63
  64 struct sdhci_cdns_plat {
  65         struct mmc_config cfg;
  66         struct mmc mmc;
  67         void __iomem *hrs_addr;
  68 };
  69
  70 struct sdhci_cdns_phy_cfg {
  71         const char *property;
  72         u8 addr;
  73 };
  74
  75 static const struct sdhci_cdns_phy_cfg sdhci_cdns_phy_cfgs[] = {
  76         { "cdns,phy-input-delay-sd-highspeed", SDHCI_CDNS_PHY_DLY_SD_HS, },
  77         { "cdns,phy-input-delay-legacy", SDHCI_CDNS_PHY_DLY_SD_DEFAULT, },
  78         { "cdns,phy-input-delay-sd-uhs-sdr12", SDHCI_CDNS_PHY_DLY_UHS_SDR12, },
  79         { "cdns,phy-input-delay-sd-uhs-sdr25", SDHCI_CDNS_PHY_DLY_UHS_SDR25, },
  80         { "cdns,phy-input-delay-sd-uhs-sdr50", SDHCI_CDNS_PHY_DLY_UHS_SDR50, },
  81         { "cdns,phy-input-delay-sd-uhs-ddr50", SDHCI_CDNS_PHY_DLY_UHS_DDR50, },
  82         { "cdns,phy-input-delay-mmc-highspeed", SDHCI_CDNS_PHY_DLY_EMMC_SDR, },
  83         { "cdns,phy-input-delay-mmc-ddr", SDHCI_CDNS_PHY_DLY_EMMC_DDR, },
  84         { "cdns,phy-dll-delay-sdclk", SDHCI_CDNS_PHY_DLY_SDCLK, },
  85         { "cdns,phy-dll-delay-sdclk-hsmmc", SDHCI_CDNS_PHY_DLY_HSMMC, },
  86         { "cdns,phy-dll-delay-strobe", SDHCI_CDNS_PHY_DLY_STROBE, },
  87 };
  88
  89 static int sdhci_cdns_write_phy_reg(struct sdhci_cdns_plat *plat,
  90                                     u8 addr, u8 data)
  91 {
  92         void __iomem *reg = plat->hrs_addr + SDHCI_CDNS_HRS04;
  93         u32 tmp;
  94         int ret;
  95
  96         tmp = FIELD_PREP(SDHCI_CDNS_HRS04_WDATA, data) |
  97               FIELD_PREP(SDHCI_CDNS_HRS04_ADDR, addr);
  98         writel(tmp, reg);
  99
 100         tmp |= SDHCI_CDNS_HRS04_WR;
 101         writel(tmp, reg);
 102
 103         ret = readl_poll_timeout(reg, tmp, tmp & SDHCI_CDNS_HRS04_ACK, 10);
 104         if (ret)
 105                 return ret;
 106
 107         tmp &= ~SDHCI_CDNS_HRS04_WR;
 108         writel(tmp, reg);
 109
 110         return 0;
 111 }
 112
 113 static int sdhci_cdns_phy_init(struct sdhci_cdns_plat *plat,
 114                                 const void *fdt, int nodeoffset)
 115 {
 116         const fdt32_t *prop;
 117         int ret, i;
 118
 119         for (i = 0; i < ARRAY_SIZE(sdhci_cdns_phy_cfgs); i++) {
 120                 prop = fdt_getprop(fdt, nodeoffset,
 121                                    sdhci_cdns_phy_cfgs[i].property, NULL);
 122                 if (!prop)
 123                         continue;
 124
 125                 ret = sdhci_cdns_write_phy_reg(plat,
 126                                                sdhci_cdns_phy_cfgs[i].addr,
 127                                                fdt32_to_cpu(*prop));
 128                 if (ret)
 129                         return ret;
 130         }
 131
 132         return 0;
 133 }
 134
 135 static void sdhci_cdns_set_control_reg(struct sdhci_host *host)
 136 {
 137         struct mmc *mmc = host->mmc;
 138         struct sdhci_cdns_plat *plat = dev_get_platdata(mmc->dev);
 139         unsigned int clock = mmc->clock;
 140         u32 mode, tmp;
 141
 142         /*
 143          * REVISIT:
 144          * The mode should be decided by MMC_TIMING_* like Linux, but
 145          * U-Boot does not support timing.  Use the clock frequency instead.
 146          */
 147         if (clock <= 26000000) {
 148                 mode = SDHCI_CDNS_HRS06_MODE_SD; /* use this for Legacy */
 149         } else if (clock <= 52000000) {
 150                 if (mmc->ddr_mode)
 151                         mode = SDHCI_CDNS_HRS06_MODE_MMC_DDR;
 152                 else
 153                         mode = SDHCI_CDNS_HRS06_MODE_MMC_SDR;
 154         } else {
 155                 if (mmc->ddr_mode)
 156                         mode = SDHCI_CDNS_HRS06_MODE_MMC_HS400;
 157                 else
 158                         mode = SDHCI_CDNS_HRS06_MODE_MMC_HS200;
 159         }
 160
 161         tmp = readl(plat->hrs_addr + SDHCI_CDNS_HRS06);
 162         tmp &= ~SDHCI_CDNS_HRS06_MODE;
 163         tmp |= FIELD_PREP(SDHCI_CDNS_HRS06_MODE, mode);
 164         writel(tmp, plat->hrs_addr + SDHCI_CDNS_HRS06);
 165 }
 166
 167 static const struct sdhci_ops sdhci_cdns_ops = {
 168         .set_control_reg = sdhci_cdns_set_control_reg,
 169 };
 170
 171 static int sdhci_cdns_set_tune_val(struct sdhci_cdns_plat *plat,
 172                                    unsigned int val)
 173 {
 174         void __iomem *reg = plat->hrs_addr + SDHCI_CDNS_HRS06;
 175         u32 tmp;
 176         int i, ret;
 177
 178         if (WARN_ON(!FIELD_FIT(SDHCI_CDNS_HRS06_TUNE, val)))
 179                 return -EINVAL;
 180
 181         tmp = readl(reg);
 182         tmp &= ~SDHCI_CDNS_HRS06_TUNE;
 183         tmp |= FIELD_PREP(SDHCI_CDNS_HRS06_TUNE, val);
 184
 185         /*
 186          * Workaround for IP errata:
 187          * The IP6116 SD/eMMC PHY design has a timing issue on receive data
 188          * path. Send tune request twice.
 189          */
 190         for (i = 0; i < 2; i++) {
 191                 tmp |= SDHCI_CDNS_HRS06_TUNE_UP;
 192                 writel(tmp, reg);
 193
 194                 ret = readl_poll_timeout(reg, tmp,
 195                                          !(tmp & SDHCI_CDNS_HRS06_TUNE_UP), 1);
 196                 if (ret)
 197                         return ret;
 198         }
 199
 200         return 0;
 201 }
 202
 203 static int __maybe_unused sdhci_cdns_execute_tuning(struct udevice *dev,
 204                                                     unsigned int opcode)
 205 {
 206         struct sdhci_cdns_plat *plat = dev_get_platdata(dev);
 207         struct mmc *mmc = &plat->mmc;
 208         int cur_streak = 0;
 209         int max_streak = 0;
 210         int end_of_streak = 0;
 211         int i;
 212
 213         /*
 214          * This handler only implements the eMMC tuning that is specific to
 215          * this controller.  The tuning for SD timing should be handled by the
 216          * SDHCI core.
 217          */
 218         if (!IS_MMC(mmc))
 219                 return -ENOTSUPP;
 220
 221         if (WARN_ON(opcode != MMC_CMD_SEND_TUNING_BLOCK_HS200))
 222                 return -EINVAL;
 223
 224         for (i = 0; i < SDHCI_CDNS_MAX_TUNING_LOOP; i++) {
 225                 if (sdhci_cdns_set_tune_val(plat, i) ||
 226                     mmc_send_tuning(mmc, opcode, NULL)) { /* bad */
 227                         cur_streak = 0;
 228                 } else { /* good */
 229                         cur_streak++;
 230                         if (cur_streak > max_streak) {
 231                                 max_streak = cur_streak;
 232                                 end_of_streak = i;
 233                         }
 234                 }
 235         }
 236
 237         if (!max_streak) {
 238                 dev_err(dev, "no tuning point found\n");
 239                 return -EIO;
 240         }
 241
 242         return sdhci_cdns_set_tune_val(plat, end_of_streak - max_streak / 2);
 243 }
 244
 245 static struct dm_mmc_ops sdhci_cdns_mmc_ops;
 246
 247 static int sdhci_cdns_bind(struct udevice *dev)
 248 {
 249         struct sdhci_cdns_plat *plat = dev_get_platdata(dev);
 250
 251         return sdhci_bind(dev, &plat->mmc, &plat->cfg);
 252 }
 253
 254 static int sdhci_cdns_probe(struct udevice *dev)
 255 {
 256         DECLARE_GLOBAL_DATA_PTR;
 257         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
 258         struct sdhci_cdns_plat *plat = dev_get_platdata(dev);
 259         struct sdhci_host *host = dev_get_priv(dev);
 260         fdt_addr_t base;
 261         int ret;
 262
 263         base = dev_read_addr(dev);
 264         if (base == FDT_ADDR_T_NONE)
 265                 return -EINVAL;
 266
 267         plat->hrs_addr = devm_ioremap(dev, base, SZ_1K);
 268         if (!plat->hrs_addr)
 269                 return -ENOMEM;
 270
 271         host->name = dev->name;
 272         host->ioaddr = plat->hrs_addr + SDHCI_CDNS_SRS_BASE;
 273         host->ops = &sdhci_cdns_ops;
 274         host->quirks |= SDHCI_QUIRK_WAIT_SEND_CMD;
 275         sdhci_cdns_mmc_ops = sdhci_ops;
 276 #ifdef MMC_SUPPORTS_TUNING
 277         sdhci_cdns_mmc_ops.execute_tuning = sdhci_cdns_execute_tuning;
 278 #endif
 279
 280         ret = mmc_of_parse(dev, &plat->cfg);
 281         if (ret)
 282                 return ret;
 283
 284         ret = sdhci_cdns_phy_init(plat, gd->fdt_blob, dev_of_offset(dev));
 285         if (ret)
 286                 return ret;
 287
 288         host->mmc = &plat->mmc;
 289         host->mmc->dev = dev;
 290         ret = sdhci_setup_cfg(&plat->cfg, host, 0, 0);
 291         if (ret)
 292                 return ret;
 293
 294         upriv->mmc = &plat->mmc;
 295         host->mmc->priv = host;
 296
 297         return sdhci_probe(dev);
 298 }
 299
 300 static const struct udevice_id sdhci_cdns_match[] = {
 301         { .compatible = "socionext,uniphier-sd4hc" },
 302         { .compatible = "cdns,sd4hc" },
 303         { /* sentinel */ }
 304 };
 305
 306 U_BOOT_DRIVER(sdhci_cdns) = {
 307         .name = "sdhci-cdns",
 308         .id = UCLASS_MMC,
 309         .of_match = sdhci_cdns_match,
 310         .bind = sdhci_cdns_bind,
 311         .probe = sdhci_cdns_probe,
 312         .priv_auto      = sizeof(struct sdhci_host),
 313         .plat_auto      = sizeof(struct sdhci_cdns_plat),
 314         .ops = &sdhci_cdns_mmc_ops,
 315 };