include/configs/M54455EVB.h

   1 /*
   2  * Configuation settings for the Freescale MCF54455 EVB board.
   3  *
   4  * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
   5  * TsiChung Liew ([email protected])
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 /*
  11  * board/config.h - configuration options, board specific
  12  */
  13
  14 #ifndef _M54455EVB_H
  15 #define _M54455EVB_H
  16
  17 /*
  18  * High Level Configuration Options
  19  * (easy to change)
  20  */
  21 #define CONFIG_M54455EVB        /* M54455EVB board */
  22
  23 #define CONFIG_MCFUART
  24 #define CONFIG_SYS_UART_PORT            (0)
  25
  26 #undef CONFIG_WATCHDOG
  27
  28 #define CONFIG_TIMESTAMP        /* Print image info with timestamp */
  29
  30 /*
  31  * BOOTP options
  32  */
  33 #define CONFIG_BOOTP_BOOTFILESIZE
  34 #define CONFIG_BOOTP_BOOTPATH
  35 #define CONFIG_BOOTP_GATEWAY
  36 #define CONFIG_BOOTP_HOSTNAME
  37
  38 /* Command line configuration */
  39 #define CONFIG_CMD_IDE
  40 #define CONFIG_CMD_JFFS2
  41 #undef CONFIG_CMD_PCI
  42 #define CONFIG_CMD_REGINFO
  43
  44 /* Network configuration */
  45 #define CONFIG_MCFFEC
  46 #ifdef CONFIG_MCFFEC
  47 #       define CONFIG_MII               1
  48 #       define CONFIG_MII_INIT          1
  49 #       define CONFIG_SYS_DISCOVER_PHY
  50 #       define CONFIG_SYS_RX_ETH_BUFFER 8
  51 #       define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  52
  53 #       define CONFIG_SYS_FEC0_PINMUX   0
  54 #       define CONFIG_SYS_FEC1_PINMUX   0
  55 #       define CONFIG_SYS_FEC0_MIIBASE  CONFIG_SYS_FEC0_IOBASE
  56 #       define CONFIG_SYS_FEC1_MIIBASE  CONFIG_SYS_FEC0_IOBASE
  57 #       define MCFFEC_TOUT_LOOP 50000
  58 #       define CONFIG_HAS_ETH1
  59
  60 #       define CONFIG_BOOTARGS          "root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:5M(kernel)ro,-(jffs2)"
  61 #       define CONFIG_ETHPRIME          "FEC0"
  62 #       define CONFIG_IPADDR            192.162.1.2
  63 #       define CONFIG_NETMASK           255.255.255.0
  64 #       define CONFIG_SERVERIP          192.162.1.1
  65 #       define CONFIG_GATEWAYIP         192.162.1.1
  66
  67 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
  68 #       ifndef CONFIG_SYS_DISCOVER_PHY
  69 #               define FECDUPLEX        FULL
  70 #               define FECSPEED         _100BASET
  71 #       else
  72 #               ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  73 #                       define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  74 #               endif
  75 #       endif                   /* CONFIG_SYS_DISCOVER_PHY */
  76 #endif
  77
  78 #define CONFIG_HOSTNAME         M54455EVB
  79 #ifdef CONFIG_SYS_STMICRO_BOOT
  80 /* ST Micro serial flash */
  81 #define CONFIG_SYS_LOAD_ADDR2           0x40010013
  82 #define CONFIG_EXTRA_ENV_SETTINGS               \
  83         "netdev=eth0\0"                         \
  84         "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"     \
  85         "loadaddr=0x40010000\0"                 \
  86         "sbfhdr=sbfhdr.bin\0"                   \
  87         "uboot=u-boot.bin\0"                    \
  88         "load=tftp ${loadaddr} ${sbfhdr};"      \
  89         "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0"       \
  90         "upd=run load; run prog\0"              \
  91         "prog=sf probe 0:1 1000000 3;"          \
  92         "sf erase 0 30000;"                     \
  93         "sf write ${loadaddr} 0 0x30000;"       \
  94         "save\0"                                \
  95         ""
  96 #else
  97 /* Atmel and Intel */
  98 #ifdef CONFIG_SYS_ATMEL_BOOT
  99 #       define CONFIG_SYS_UBOOT_END     0x0403FFFF
 100 #elif defined(CONFIG_SYS_INTEL_BOOT)
 101 #       define CONFIG_SYS_UBOOT_END     0x3FFFF
 102 #endif
 103 #define CONFIG_EXTRA_ENV_SETTINGS               \
 104         "netdev=eth0\0"                         \
 105         "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"     \
 106         "loadaddr=0x40010000\0"                 \
 107         "uboot=u-boot.bin\0"                    \
 108         "load=tftp ${loadaddr} ${uboot}\0"      \
 109         "upd=run load; run prog\0"              \
 110         "prog=prot off " __stringify(CONFIG_SYS_FLASH_BASE)     \
 111         " " __stringify(CONFIG_SYS_UBOOT_END) ";"               \
 112         "era " __stringify(CONFIG_SYS_FLASH_BASE) " "           \
 113         __stringify(CONFIG_SYS_UBOOT_END) ";"                   \
 114         "cp.b ${loadaddr} " __stringify(CONFIG_SYS_FLASH_BASE)  \
 115         " ${filesize}; save\0"                  \
 116         ""
 117 #endif
 118
 119 /* ATA configuration */
 120 #define CONFIG_IDE_RESET        1
 121 #define CONFIG_IDE_PREINIT      1
 122 #define CONFIG_ATAPI
 123 #undef CONFIG_LBA48
 124
 125 #define CONFIG_SYS_IDE_MAXBUS           1
 126 #define CONFIG_SYS_IDE_MAXDEVICE        2
 127
 128 #define CONFIG_SYS_ATA_BASE_ADDR        0x90000000
 129 #define CONFIG_SYS_ATA_IDE0_OFFSET      0
 130
 131 #define CONFIG_SYS_ATA_DATA_OFFSET      0xA0    /* Offset for data I/O                            */
 132 #define CONFIG_SYS_ATA_REG_OFFSET       0xA0    /* Offset for normal register accesses */
 133 #define CONFIG_SYS_ATA_ALT_OFFSET       0xC0    /* Offset for alternate registers           */
 134 #define CONFIG_SYS_ATA_STRIDE           4       /* Interval between registers                 */
 135
 136 /* Realtime clock */
 137 #define CONFIG_MCFRTC
 138 #undef RTC_DEBUG
 139 #define CONFIG_SYS_RTC_OSCILLATOR       (32 * CONFIG_SYS_HZ)
 140
 141 /* Timer */
 142 #define CONFIG_MCFTMR
 143 #undef CONFIG_MCFPIT
 144
 145 /* I2c */
 146 #define CONFIG_SYS_I2C
 147 #define CONFIG_SYS_I2C_FSL
 148 #define CONFIG_SYS_FSL_I2C_SPEED        80000
 149 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 150 #define CONFIG_SYS_FSL_I2C_OFFSET       0x58000
 151 #define CONFIG_SYS_IMMR         CONFIG_SYS_MBAR
 152
 153 /* DSPI and Serial Flash */
 154 #define CONFIG_CF_SPI
 155 #define CONFIG_CF_DSPI
 156 #define CONFIG_HARD_SPI
 157 #define CONFIG_SYS_SBFHDR_SIZE          0x13
 158 #ifdef CONFIG_CMD_SPI
 159
 160 #       define CONFIG_SYS_DSPI_CTAR0            (DSPI_CTAR_TRSZ(7) | \
 161                                          DSPI_CTAR_PCSSCK_1CLK | \
 162                                          DSPI_CTAR_PASC(0) | \
 163                                          DSPI_CTAR_PDT(0) | \
 164                                          DSPI_CTAR_CSSCK(0) | \
 165                                          DSPI_CTAR_ASC(0) | \
 166                                          DSPI_CTAR_DT(1))
 167 #endif
 168
 169 /* PCI */
 170 #ifdef CONFIG_CMD_PCI
 171 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
 172
 173 #define CONFIG_SYS_PCI_CACHE_LINE_SIZE  4
 174
 175 #define CONFIG_SYS_PCI_MEM_BUS          0xA0000000
 176 #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BUS
 177 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000
 178
 179 #define CONFIG_SYS_PCI_IO_BUS           0xB1000000
 180 #define CONFIG_SYS_PCI_IO_PHYS          CONFIG_SYS_PCI_IO_BUS
 181 #define CONFIG_SYS_PCI_IO_SIZE          0x01000000
 182
 183 #define CONFIG_SYS_PCI_CFG_BUS          0xB0000000
 184 #define CONFIG_SYS_PCI_CFG_PHYS CONFIG_SYS_PCI_CFG_BUS
 185 #define CONFIG_SYS_PCI_CFG_SIZE 0x01000000
 186 #endif
 187
 188 /* FPGA - Spartan 2 */
 189 /* experiment
 190 #define CONFIG_FPGA
 191 #define CONFIG_FPGA_COUNT       1
 192 #define CONFIG_SYS_FPGA_PROG_FEEDBACK
 193 #define CONFIG_SYS_FPGA_CHECK_CTRLC
 194 */
 195
 196 /* Input, PCI, Flexbus, and VCO */
 197 #define CONFIG_EXTRA_CLOCK
 198
 199 #define CONFIG_PRAM             2048    /* 2048 KB */
 200
 201 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 202
 203 #if defined(CONFIG_CMD_KGDB)
 204 #define CONFIG_SYS_CBSIZE                       1024    /* Console I/O Buffer Size */
 205 #else
 206 #define CONFIG_SYS_CBSIZE                       256     /* Console I/O Buffer Size */
 207 #endif
 208 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)        /* Print Buffer Size */
 209 #define CONFIG_SYS_MAXARGS              16      /* max number of command args */
 210 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 211
 212 #define CONFIG_SYS_LOAD_ADDR            (CONFIG_SYS_SDRAM_BASE + 0x10000)
 213
 214 #define CONFIG_SYS_MBAR         0xFC000000
 215
 216 /*
 217  * Low Level Configuration Settings
 218  * (address mappings, register initial values, etc.)
 219  * You should know what you are doing if you make changes here.
 220  */
 221
 222 /*-----------------------------------------------------------------------
 223  * Definitions for initial stack pointer and data area (in DPRAM)
 224  */
 225 #define CONFIG_SYS_INIT_RAM_ADDR        0x80000000
 226 #define CONFIG_SYS_INIT_RAM_SIZE                0x8000  /* Size of used area in internal SRAM */
 227 #define CONFIG_SYS_INIT_RAM_CTRL        0x221
 228 #define CONFIG_SYS_GBL_DATA_OFFSET      ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32)
 229 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 230 #define CONFIG_SYS_SBFHDR_DATA_OFFSET   (CONFIG_SYS_INIT_RAM_SIZE - 32)
 231
 232 /*-----------------------------------------------------------------------
 233  * Start addresses for the final memory configuration
 234  * (Set up by the startup code)
 235  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 236  */
 237 #define CONFIG_SYS_SDRAM_BASE           0x40000000
 238 #define CONFIG_SYS_SDRAM_BASE1          0x48000000
 239 #define CONFIG_SYS_SDRAM_SIZE           256     /* SDRAM size in MB */
 240 #define CONFIG_SYS_SDRAM_CFG1           0x65311610
 241 #define CONFIG_SYS_SDRAM_CFG2           0x59670000
 242 #define CONFIG_SYS_SDRAM_CTRL           0xEA0B2000
 243 #define CONFIG_SYS_SDRAM_EMOD           0x40010000
 244 #define CONFIG_SYS_SDRAM_MODE           0x00010033
 245 #define CONFIG_SYS_SDRAM_DRV_STRENGTH   0xAA
 246
 247 #define CONFIG_SYS_MEMTEST_START        CONFIG_SYS_SDRAM_BASE + 0x400
 248 #define CONFIG_SYS_MEMTEST_END          ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
 249
 250 #ifdef CONFIG_CF_SBF
 251 #       define CONFIG_SERIAL_BOOT
 252 #       define CONFIG_SYS_MONITOR_BASE  (CONFIG_SYS_TEXT_BASE + 0x400)
 253 #else
 254 #       define CONFIG_SYS_MONITOR_BASE  (CONFIG_SYS_FLASH_BASE + 0x400)
 255 #endif
 256 #define CONFIG_SYS_BOOTPARAMS_LEN       64*1024
 257 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor */
 258
 259 /* Reserve 256 kB for malloc() */
 260 #define CONFIG_SYS_MALLOC_LEN           (256 << 10)
 261
 262 /*
 263  * For booting Linux, the board info and command line data
 264  * have to be in the first 8 MB of memory, since this is
 265  * the maximum mapped by the Linux kernel during initialization ??
 266  */
 267 /* Initial Memory map for Linux */
 268 #define CONFIG_SYS_BOOTMAPSZ            (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
 269
 270 /*
 271  * Configuration for environment
 272  * Environment is not embedded in u-boot. First time runing may have env
 273  * crc error warning if there is no correct environment on the flash.
 274  */
 275 #ifdef CONFIG_CF_SBF
 276 #       define CONFIG_ENV_IS_IN_SPI_FLASH
 277 #       define CONFIG_ENV_SPI_CS                1
 278 #else
 279 #       define CONFIG_ENV_IS_IN_FLASH   1
 280 #endif
 281 #undef CONFIG_ENV_OVERWRITE
 282
 283 /*-----------------------------------------------------------------------
 284  * FLASH organization
 285  */
 286 #ifdef CONFIG_SYS_STMICRO_BOOT
 287 #       define CONFIG_SYS_FLASH_BASE            CONFIG_SYS_CS0_BASE
 288 #       define CONFIG_SYS_FLASH0_BASE           CONFIG_SYS_CS1_BASE
 289 #       define CONFIG_ENV_OFFSET                0x30000
 290 #       define CONFIG_ENV_SIZE          0x2000
 291 #       define CONFIG_ENV_SECT_SIZE     0x10000
 292 #endif
 293 #ifdef CONFIG_SYS_ATMEL_BOOT
 294 #       define CONFIG_SYS_FLASH_BASE            CONFIG_SYS_CS0_BASE
 295 #       define CONFIG_SYS_FLASH0_BASE           CONFIG_SYS_CS0_BASE
 296 #       define CONFIG_SYS_FLASH1_BASE           CONFIG_SYS_CS1_BASE
 297 #       define CONFIG_ENV_ADDR          (CONFIG_SYS_FLASH_BASE + 0x40000)
 298 #       define CONFIG_ENV_SIZE          0x2000
 299 #       define CONFIG_ENV_SECT_SIZE     0x10000
 300 #endif
 301 #ifdef CONFIG_SYS_INTEL_BOOT
 302 #       define CONFIG_SYS_FLASH_BASE            CONFIG_SYS_CS0_BASE
 303 #       define CONFIG_SYS_FLASH0_BASE           CONFIG_SYS_CS0_BASE
 304 #       define CONFIG_SYS_FLASH1_BASE           CONFIG_SYS_CS1_BASE
 305 #       define CONFIG_ENV_ADDR          (CONFIG_SYS_FLASH_BASE + 0x40000)
 306 #       define CONFIG_ENV_SIZE          0x2000
 307 #       define CONFIG_ENV_SECT_SIZE     0x20000
 308 #endif
 309
 310 #define CONFIG_SYS_FLASH_CFI
 311 #ifdef CONFIG_SYS_FLASH_CFI
 312
 313 #       define CONFIG_FLASH_CFI_DRIVER  1
 314 #       define CONFIG_SYS_FLASH_USE_BUFFER_WRITE        1
 315 #       define CONFIG_SYS_FLASH_SIZE            0x1000000       /* Max size that the board might have */
 316 #       define CONFIG_SYS_FLASH_CFI_WIDTH       FLASH_CFI_8BIT
 317 #       define CONFIG_SYS_MAX_FLASH_BANKS       2       /* max number of memory banks */
 318 #       define CONFIG_SYS_MAX_FLASH_SECT        137     /* max number of sectors on one chip */
 319 #       define CONFIG_SYS_FLASH_PROTECTION      /* "Real" (hardware) sectors protection */
 320 #       define CONFIG_SYS_FLASH_CHECKSUM
 321 #       define CONFIG_SYS_FLASH_BANKS_LIST      { CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE }
 322 #       define CONFIG_FLASH_CFI_LEGACY
 323
 324 #ifdef CONFIG_FLASH_CFI_LEGACY
 325 #       define CONFIG_SYS_ATMEL_REGION          4
 326 #       define CONFIG_SYS_ATMEL_TOTALSECT       11
 327 #       define CONFIG_SYS_ATMEL_SECT            {1, 2, 1, 7}
 328 #       define CONFIG_SYS_ATMEL_SECTSZ          {0x4000, 0x2000, 0x8000, 0x10000}
 329 #endif
 330 #endif
 331
 332 /*
 333  * This is setting for JFFS2 support in u-boot.
 334  * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
 335  */
 336 #ifdef CONFIG_CMD_JFFS2
 337 #ifdef CF_STMICRO_BOOT
 338 #       define CONFIG_JFFS2_DEV         "nor1"
 339 #       define CONFIG_JFFS2_PART_SIZE   0x01000000
 340 #       define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH2_BASE + 0x500000)
 341 #endif
 342 #ifdef CONFIG_SYS_ATMEL_BOOT
 343 #       define CONFIG_JFFS2_DEV         "nor1"
 344 #       define CONFIG_JFFS2_PART_SIZE   0x01000000
 345 #       define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH1_BASE + 0x500000)
 346 #endif
 347 #ifdef CONFIG_SYS_INTEL_BOOT
 348 #       define CONFIG_JFFS2_DEV         "nor0"
 349 #       define CONFIG_JFFS2_PART_SIZE   (0x01000000 - 0x500000)
 350 #       define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x500000)
 351 #endif
 352 #endif
 353
 354 /*-----------------------------------------------------------------------
 355  * Cache Configuration
 356  */
 357 #define CONFIG_SYS_CACHELINE_SIZE               16
 358
 359 #define ICACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 360                                          CONFIG_SYS_INIT_RAM_SIZE - 8)
 361 #define DCACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 362                                          CONFIG_SYS_INIT_RAM_SIZE - 4)
 363 #define CONFIG_SYS_ICACHE_INV           (CF_CACR_BCINVA + CF_CACR_ICINVA)
 364 #define CONFIG_SYS_DCACHE_INV           (CF_CACR_DCINVA)
 365 #define CONFIG_SYS_CACHE_ACR2           (CONFIG_SYS_SDRAM_BASE | \
 366                                          CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
 367                                          CF_ACR_EN | CF_ACR_SM_ALL)
 368 #define CONFIG_SYS_CACHE_ICACR          (CF_CACR_BEC | CF_CACR_IEC | \
 369                                          CF_CACR_ICINVA | CF_CACR_EUSP)
 370 #define CONFIG_SYS_CACHE_DCACR          ((CONFIG_SYS_CACHE_ICACR | \
 371                                          CF_CACR_DEC | CF_CACR_DDCM_P | \
 372                                          CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
 373
 374 /*-----------------------------------------------------------------------
 375  * Memory bank definitions
 376  */
 377 /*
 378  * CS0 - NOR Flash 1, 2, 4, or 8MB
 379  * CS1 - CompactFlash and registers
 380  * CS2 - CPLD
 381  * CS3 - FPGA
 382  * CS4 - Available
 383  * CS5 - Available
 384  */
 385
 386 #if defined(CONFIG_SYS_ATMEL_BOOT) || defined(CONFIG_SYS_STMICRO_BOOT)
 387  /* Atmel Flash */
 388 #define CONFIG_SYS_CS0_BASE             0x04000000
 389 #define CONFIG_SYS_CS0_MASK             0x00070001
 390 #define CONFIG_SYS_CS0_CTRL             0x00001140
 391 /* Intel Flash */
 392 #define CONFIG_SYS_CS1_BASE             0x00000000
 393 #define CONFIG_SYS_CS1_MASK             0x01FF0001
 394 #define CONFIG_SYS_CS1_CTRL             0x00000D60
 395
 396 #define CONFIG_SYS_ATMEL_BASE           CONFIG_SYS_CS0_BASE
 397 #else
 398 /* Intel Flash */
 399 #define CONFIG_SYS_CS0_BASE             0x00000000
 400 #define CONFIG_SYS_CS0_MASK             0x01FF0001
 401 #define CONFIG_SYS_CS0_CTRL             0x00000D60
 402  /* Atmel Flash */
 403 #define CONFIG_SYS_CS1_BASE             0x04000000
 404 #define CONFIG_SYS_CS1_MASK             0x00070001
 405 #define CONFIG_SYS_CS1_CTRL             0x00001140
 406
 407 #define CONFIG_SYS_ATMEL_BASE           CONFIG_SYS_CS1_BASE
 408 #endif
 409
 410 /* CPLD */
 411 #define CONFIG_SYS_CS2_BASE             0x08000000
 412 #define CONFIG_SYS_CS2_MASK             0x00070001
 413 #define CONFIG_SYS_CS2_CTRL             0x003f1140
 414
 415 /* FPGA */
 416 #define CONFIG_SYS_CS3_BASE             0x09000000
 417 #define CONFIG_SYS_CS3_MASK             0x00070001
 418 #define CONFIG_SYS_CS3_CTRL             0x00000020
 419
 420 #endif                          /* _M54455EVB_H */