board/atmel/at91sam9261ek/at91sam9261ek.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2007-2008
   4  * Stelian Pop <[email protected]>
   5  * Lead Tech Design <www.leadtechdesign.com>
   6  */
   7
   8 #include <config.h>
   9 #include <debug_uart.h>
  10 #include <init.h>
  11 #include <vsprintf.h>
  12 #include <asm/global_data.h>
  13 #include <asm/io.h>
  14 #include <asm/arch/at91sam9261.h>
  15 #include <asm/arch/at91sam9261_matrix.h>
  16 #include <asm/arch/at91sam9_smc.h>
  17 #include <asm/arch/at91_common.h>
  18 #include <asm/arch/at91_rstc.h>
  19 #include <asm/arch/clk.h>
  20 #include <asm/arch/gpio.h>
  21 #include <atmel_lcdc.h>
  22 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_DRIVER_DM9000)
  23 #include <net.h>
  24 #include <netdev.h>
  25 #endif
  26 #include <asm/mach-types.h>
  27
  28 DECLARE_GLOBAL_DATA_PTR;
  29
  30 /* ------------------------------------------------------------------------- */
  31 /*
  32  * Miscelaneous platform dependent initialisations
  33  */
  34
  35 #ifdef CONFIG_CMD_NAND
  36 static void at91sam9261ek_nand_hw_init(void)
  37 {
  38         struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
  39         struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
  40         unsigned long csa;
  41
  42         /* Enable CS3 */
  43         csa = readl(&matrix->ebicsa);
  44         csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
  45
  46         writel(csa, &matrix->ebicsa);
  47
  48         /* Configure SMC CS3 for NAND/SmartMedia */
  49 #ifdef CONFIG_AT91SAM9G10EK
  50         writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
  51                 AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
  52                 &smc->cs[3].setup);
  53         writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(7) |
  54                 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(7),
  55                 &smc->cs[3].pulse);
  56         writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(7),
  57                 &smc->cs[3].cycle);
  58 #else
  59         writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
  60                 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
  61                 &smc->cs[3].setup);
  62         writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
  63                 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
  64                 &smc->cs[3].pulse);
  65         writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
  66                 &smc->cs[3].cycle);
  67 #endif
  68         writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  69                        AT91_SMC_MODE_EXNW_DISABLE |
  70 #ifdef CONFIG_SYS_NAND_DBW_16
  71                        AT91_SMC_MODE_DBW_16 |
  72 #else /* CONFIG_SYS_NAND_DBW_8 */
  73                        AT91_SMC_MODE_DBW_8 |
  74 #endif
  75                        AT91_SMC_MODE_TDF_CYCLE(2),
  76                        &smc->cs[3].mode);
  77
  78         at91_periph_clk_enable(ATMEL_ID_PIOC);
  79
  80         /* Configure RDY/BSY */
  81         at91_set_gpio_input(CFG_SYS_NAND_READY_PIN, 1);
  82
  83         /* Enable NandFlash */
  84         at91_set_gpio_output(CFG_SYS_NAND_ENABLE_PIN, 1);
  85
  86         at91_set_A_periph(AT91_PIN_PC0, 0);     /* NANDOE */
  87         at91_set_A_periph(AT91_PIN_PC1, 0);     /* NANDWE */
  88 }
  89 #endif
  90
  91 #ifdef CONFIG_DRIVER_DM9000
  92 static void at91sam9261ek_dm9000_hw_init(void)
  93 {
  94         struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
  95
  96         /* Configure SMC CS2 for DM9000 */
  97 #ifdef CONFIG_AT91SAM9G10EK
  98         writel(AT91_SMC_SETUP_NWE(3) | AT91_SMC_SETUP_NCS_WR(0) |
  99                 AT91_SMC_SETUP_NRD(3) | AT91_SMC_SETUP_NCS_RD(0),
 100                 &smc->cs[2].setup);
 101         writel(AT91_SMC_PULSE_NWE(6) | AT91_SMC_PULSE_NCS_WR(8) |
 102                 AT91_SMC_PULSE_NRD(6) | AT91_SMC_PULSE_NCS_RD(8),
 103                 &smc->cs[2].pulse);
 104         writel(AT91_SMC_CYCLE_NWE(20) | AT91_SMC_CYCLE_NRD(20),
 105                 &smc->cs[2].cycle);
 106         writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
 107                        AT91_SMC_MODE_EXNW_DISABLE |
 108                        AT91_SMC_MODE_BAT | AT91_SMC_MODE_DBW_16 |
 109                        AT91_SMC_MODE_TDF_CYCLE(1),
 110                        &smc->cs[2].mode);
 111 #else
 112         writel(AT91_SMC_SETUP_NWE(3) | AT91_SMC_SETUP_NCS_WR(0) |
 113                 AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
 114                 &smc->cs[2].setup);
 115         writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(8) |
 116                 AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(8),
 117                 &smc->cs[2].pulse);
 118         writel(AT91_SMC_CYCLE_NWE(16) | AT91_SMC_CYCLE_NRD(16),
 119                 &smc->cs[2].cycle);
 120         writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
 121                        AT91_SMC_MODE_EXNW_DISABLE |
 122                        AT91_SMC_MODE_BAT | AT91_SMC_MODE_DBW_16 |
 123                        AT91_SMC_MODE_TDF_CYCLE(1),
 124                        &smc->cs[2].mode);
 125 #endif
 126
 127         /* Configure Reset signal as output */
 128         at91_set_gpio_output(AT91_PIN_PC10, 0);
 129
 130         /* Configure Interrupt pin as input, no pull-up */
 131         at91_set_gpio_input(AT91_PIN_PC11, 0);
 132 }
 133 #endif
 134
 135 #ifdef CONFIG_DEBUG_UART_BOARD_INIT
 136 void board_debug_uart_init(void)
 137 {
 138         at91_seriald_hw_init();
 139 }
 140 #endif
 141
 142 #ifdef CONFIG_BOARD_EARLY_INIT_F
 143 int board_early_init_f(void)
 144 {
 145         return 0;
 146 }
 147 #endif
 148
 149 int board_init(void)
 150 {
 151 #ifdef CONFIG_AT91SAM9G10EK
 152         /* arch number of AT91SAM9G10EK-Board */
 153         gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9G10EK;
 154 #else
 155         /* arch number of AT91SAM9261EK-Board */
 156         gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9261EK;
 157 #endif
 158         /* adress of boot parameters */
 159         gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
 160
 161 #ifdef CONFIG_CMD_NAND
 162         at91sam9261ek_nand_hw_init();
 163 #endif
 164 #ifdef CONFIG_DRIVER_DM9000
 165         at91sam9261ek_dm9000_hw_init();
 166 #endif
 167         return 0;
 168 }
 169
 170 #ifdef CONFIG_DRIVER_DM9000
 171 int board_eth_init(struct bd_info *bis)
 172 {
 173         return dm9000_initialize(bis);
 174 }
 175 #endif
 176
 177 int dram_init(void)
 178 {
 179         gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
 180                 CFG_SYS_SDRAM_SIZE);
 181
 182         return 0;
 183 }
 184
 185 #ifdef CONFIG_RESET_PHY_R
 186 void reset_phy(void)
 187 {
 188 #ifdef CONFIG_DRIVER_DM9000
 189         /*
 190          * Initialize ethernet HW addr prior to starting Linux,
 191          * needed for nfsroot
 192          */
 193         eth_init();
 194 #endif
 195 }
 196 #endif