drivers/clk/clk-divider.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2019 DENX Software Engineering
   4  * Lukasz Majewski, DENX Software Engineering, [email protected]
   5  *
   6  * Copyright (C) 2011 Sascha Hauer, Pengutronix <[email protected]>
   7  * Copyright (C) 2011 Richard Zhao, Linaro <[email protected]>
   8  * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <[email protected]>
   9  *
  10  */
  11
  12 #define LOG_CATEGORY UCLASS_CLK
  13
  14 #include <asm/io.h>
  15 #include <malloc.h>
  16 #include <clk-uclass.h>
  17 #include <log.h>
  18 #include <dm/device.h>
  19 #include <dm/devres.h>
  20 #include <dm/uclass.h>
  21 #include <dm/lists.h>
  22 #include <dm/device_compat.h>
  23 #include <dm/device-internal.h>
  24 #include <linux/bug.h>
  25 #include <linux/clk-provider.h>
  26 #include <linux/err.h>
  27 #include <linux/log2.h>
  28 #include <div64.h>
  29 #include <clk.h>
  30 #include <linux/printk.h>
  31 #include "clk.h"
  32
  33 #define UBOOT_DM_CLK_CCF_DIVIDER "ccf_clk_divider"
  34
  35 unsigned int clk_divider_get_table_div(const struct clk_div_table *table,
  36                                        unsigned int val)
  37 {
  38         const struct clk_div_table *clkt;
  39
  40         for (clkt = table; clkt->div; clkt++)
  41                 if (clkt->val == val)
  42                         return clkt->div;
  43         return 0;
  44 }
  45
  46 static unsigned int _get_div(const struct clk_div_table *table,
  47                              unsigned int val, unsigned long flags, u8 width)
  48 {
  49         if (flags & CLK_DIVIDER_ONE_BASED)
  50                 return val;
  51         if (flags & CLK_DIVIDER_POWER_OF_TWO)
  52                 return 1 << val;
  53         if (flags & CLK_DIVIDER_MAX_AT_ZERO)
  54                 return val ? val : clk_div_mask(width) + 1;
  55         if (table)
  56                 return clk_divider_get_table_div(table, val);
  57         return val + 1;
  58 }
  59
  60 unsigned long divider_recalc_rate(struct clk *hw, unsigned long parent_rate,
  61                                   unsigned int val,
  62                                   const struct clk_div_table *table,
  63                                   unsigned long flags, unsigned long width)
  64 {
  65         unsigned int div;
  66
  67         div = _get_div(table, val, flags, width);
  68         if (!div) {
  69                 WARN(!(flags & CLK_DIVIDER_ALLOW_ZERO),
  70                      "%s: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n",
  71                      clk_hw_get_name(hw));
  72                 return parent_rate;
  73         }
  74
  75         return DIV_ROUND_UP_ULL((u64)parent_rate, div);
  76 }
  77
  78 static ulong clk_divider_recalc_rate(struct clk *clk)
  79 {
  80         struct clk_divider *divider = to_clk_divider(clk);
  81         unsigned long parent_rate = clk_get_parent_rate(clk);
  82         unsigned int val;
  83
  84 #if IS_ENABLED(CONFIG_SANDBOX_CLK_CCF)
  85         val = divider->io_divider_val;
  86 #else
  87         val = readl(divider->reg);
  88 #endif
  89         val >>= divider->shift;
  90         val &= clk_div_mask(divider->width);
  91
  92         return divider_recalc_rate(clk, parent_rate, val, divider->table,
  93                                    divider->flags, divider->width);
  94 }
  95
  96 bool clk_divider_is_valid_table_div(const struct clk_div_table *table,
  97                                     unsigned int div)
  98 {
  99         const struct clk_div_table *clkt;
 100
 101         for (clkt = table; clkt->div; clkt++)
 102                 if (clkt->div == div)
 103                         return true;
 104         return false;
 105 }
 106
 107 bool clk_divider_is_valid_div(const struct clk_div_table *table,
 108                               unsigned int div, unsigned long flags)
 109 {
 110         if (flags & CLK_DIVIDER_POWER_OF_TWO)
 111                 return is_power_of_2(div);
 112         if (table)
 113                 return clk_divider_is_valid_table_div(table, div);
 114         return true;
 115 }
 116
 117 unsigned int clk_divider_get_table_val(const struct clk_div_table *table,
 118                                        unsigned int div)
 119 {
 120         const struct clk_div_table *clkt;
 121
 122         for (clkt = table; clkt->div; clkt++)
 123                 if (clkt->div == div)
 124                         return clkt->val;
 125         return 0;
 126 }
 127
 128 static unsigned int _get_val(const struct clk_div_table *table,
 129                              unsigned int div, unsigned long flags, u8 width)
 130 {
 131         if (flags & CLK_DIVIDER_ONE_BASED)
 132                 return div;
 133         if (flags & CLK_DIVIDER_POWER_OF_TWO)
 134                 return __ffs(div);
 135         if (flags & CLK_DIVIDER_MAX_AT_ZERO)
 136                 return (div == clk_div_mask(width) + 1) ? 0 : div;
 137         if (table)
 138                 return clk_divider_get_table_val(table, div);
 139         return div - 1;
 140 }
 141 int divider_get_val(unsigned long rate, unsigned long parent_rate,
 142                     const struct clk_div_table *table, u8 width,
 143                     unsigned long flags)
 144 {
 145         unsigned int div, value;
 146
 147         div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
 148
 149         if (!clk_divider_is_valid_div(table, div, flags))
 150                 return -EINVAL;
 151
 152         value = _get_val(table, div, flags, width);
 153
 154         return min_t(unsigned int, value, clk_div_mask(width));
 155 }
 156
 157 static ulong clk_divider_set_rate(struct clk *clk, unsigned long rate)
 158 {
 159         struct clk_divider *divider = to_clk_divider(clk);
 160         unsigned long parent_rate = clk_get_parent_rate(clk);
 161         int value;
 162         u32 val;
 163
 164         value = divider_get_val(rate, parent_rate, divider->table,
 165                                 divider->width, divider->flags);
 166         if (value < 0)
 167                 return value;
 168
 169         if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {
 170                 val = clk_div_mask(divider->width) << (divider->shift + 16);
 171         } else {
 172                 val = readl(divider->reg);
 173                 val &= ~(clk_div_mask(divider->width) << divider->shift);
 174         }
 175         val |= (u32)value << divider->shift;
 176         writel(val, divider->reg);
 177
 178         return clk_get_rate(clk);
 179 }
 180
 181 const struct clk_ops clk_divider_ops = {
 182         .get_rate = clk_divider_recalc_rate,
 183         .set_rate = clk_divider_set_rate,
 184 };
 185
 186 static struct clk *_register_divider(struct device *dev, const char *name,
 187                 const char *parent_name, unsigned long flags,
 188                 void __iomem *reg, u8 shift, u8 width,
 189                 u8 clk_divider_flags, const struct clk_div_table *table)
 190 {
 191         struct clk_divider *div;
 192         struct clk *clk;
 193         int ret;
 194
 195         if (clk_divider_flags & CLK_DIVIDER_HIWORD_MASK) {
 196                 if (width + shift > 16) {
 197                         dev_warn(dev, "divider value exceeds LOWORD field\n");
 198                         return ERR_PTR(-EINVAL);
 199                 }
 200         }
 201
 202         /* allocate the divider */
 203         div = kzalloc(sizeof(*div), GFP_KERNEL);
 204         if (!div)
 205                 return ERR_PTR(-ENOMEM);
 206
 207         /* struct clk_divider assignments */
 208         div->reg = reg;
 209         div->shift = shift;
 210         div->width = width;
 211         div->flags = clk_divider_flags;
 212         div->table = table;
 213 #if IS_ENABLED(CONFIG_SANDBOX_CLK_CCF)
 214         div->io_divider_val = *(u32 *)reg;
 215 #endif
 216
 217         /* register the clock */
 218         clk = &div->clk;
 219         clk->flags = flags;
 220
 221         ret = clk_register(clk, UBOOT_DM_CLK_CCF_DIVIDER, name, parent_name);
 222         if (ret) {
 223                 kfree(div);
 224                 return ERR_PTR(ret);
 225         }
 226
 227         return clk;
 228 }
 229
 230 struct clk *clk_register_divider(struct device *dev, const char *name,
 231                 const char *parent_name, unsigned long flags,
 232                 void __iomem *reg, u8 shift, u8 width,
 233                 u8 clk_divider_flags)
 234 {
 235         struct clk *clk;
 236
 237         clk =  _register_divider(dev, name, parent_name, flags, reg, shift,
 238                                  width, clk_divider_flags, NULL);
 239         if (IS_ERR(clk))
 240                 return ERR_CAST(clk);
 241         return clk;
 242 }
 243
 244 U_BOOT_DRIVER(ccf_clk_divider) = {
 245         .name   = UBOOT_DM_CLK_CCF_DIVIDER,
 246         .id     = UCLASS_CLK,
 247         .ops    = &clk_divider_ops,
 248         .flags = DM_FLAG_PRE_RELOC,
 249 };