drivers/timer/cadence-ttc.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2018 Xilinx, Inc. (Michal Simek)
   4  */
   5
   6 #include <common.h>
   7 #include <bootstage.h>
   8 #include <dm.h>
   9 #include <errno.h>
  10 #include <init.h>
  11 #include <timer.h>
  12 #include <asm/io.h>
  13 #include <linux/bitops.h>
  14 #include <linux/err.h>
  15
  16 #define CNT_CNTRL_RESET         BIT(4)
  17
  18 struct cadence_ttc_regs {
  19         u32 clk_cntrl1; /* 0x0 - Clock Control 1 */
  20         u32 clk_cntrl2; /* 0x4 - Clock Control 2 */
  21         u32 clk_cntrl3; /* 0x8 - Clock Control 3 */
  22         u32 counter_cntrl1; /* 0xC - Counter Control 1 */
  23         u32 counter_cntrl2; /* 0x10 - Counter Control 2 */
  24         u32 counter_cntrl3; /* 0x14 - Counter Control 3 */
  25         u32 counter_val1; /* 0x18 - Counter Control 1 */
  26         u32 counter_val2; /* 0x1C - Counter Control 2 */
  27         u32 counter_val3; /* 0x20 - Counter Control 3 */
  28         u32 reserved[15];
  29         u32 interrupt_enable1; /* 0x60 - Interrupt Enable 1 */
  30         u32 interrupt_enable2; /* 0x64 - Interrupt Enable 2 */
  31         u32 interrupt_enable3; /* 0x68 - Interrupt Enable 3 */
  32 };
  33
  34 struct cadence_ttc_priv {
  35         struct cadence_ttc_regs *regs;
  36 };
  37
  38 #if CONFIG_IS_ENABLED(BOOTSTAGE)
  39 ulong timer_get_boot_us(void)
  40 {
  41         u64 ticks = 0;
  42         u32 rate = 1;
  43         u64 us;
  44         int ret;
  45
  46         ret = dm_timer_init();
  47         if (!ret) {
  48                 /* The timer is available */
  49                 rate = timer_get_rate(gd->timer);
  50                 timer_get_count(gd->timer, &ticks);
  51         } else {
  52                 return 0;
  53         }
  54
  55         us = (ticks * 1000) / rate;
  56         return us;
  57 }
  58 #endif
  59
  60 static int cadence_ttc_get_count(struct udevice *dev, u64 *count)
  61 {
  62         struct cadence_ttc_priv *priv = dev_get_priv(dev);
  63
  64         *count = readl(&priv->regs->counter_val1);
  65
  66         return 0;
  67 }
  68
  69 static int cadence_ttc_probe(struct udevice *dev)
  70 {
  71         struct cadence_ttc_priv *priv = dev_get_priv(dev);
  72
  73         /* Disable interrupts for sure */
  74         writel(0, &priv->regs->interrupt_enable1);
  75         writel(0, &priv->regs->interrupt_enable2);
  76         writel(0, &priv->regs->interrupt_enable3);
  77
  78         /* Make sure that clocks are configured properly without prescaller */
  79         writel(0, &priv->regs->clk_cntrl1);
  80         writel(0, &priv->regs->clk_cntrl2);
  81         writel(0, &priv->regs->clk_cntrl3);
  82
  83         /* Reset and enable this counter */
  84         writel(CNT_CNTRL_RESET, &priv->regs->counter_cntrl1);
  85
  86         return 0;
  87 }
  88
  89 static int cadence_ttc_ofdata_to_platdata(struct udevice *dev)
  90 {
  91         struct cadence_ttc_priv *priv = dev_get_priv(dev);
  92
  93         priv->regs = map_physmem(dev_read_addr(dev),
  94                                  sizeof(struct cadence_ttc_regs), MAP_NOCACHE);
  95         if (IS_ERR(priv->regs))
  96                 return PTR_ERR(priv->regs);
  97
  98         return 0;
  99 }
 100
 101 static const struct timer_ops cadence_ttc_ops = {
 102         .get_count = cadence_ttc_get_count,
 103 };
 104
 105 static const struct udevice_id cadence_ttc_ids[] = {
 106         { .compatible = "cdns,ttc" },
 107         {}
 108 };
 109
 110 U_BOOT_DRIVER(cadence_ttc) = {
 111         .name = "cadence_ttc",
 112         .id = UCLASS_TIMER,
 113         .of_match = cadence_ttc_ids,
 114         .ofdata_to_platdata = cadence_ttc_ofdata_to_platdata,
 115         .priv_auto_alloc_size = sizeof(struct cadence_ttc_priv),
 116         .probe = cadence_ttc_probe,
 117         .ops = &cadence_ttc_ops,
 118 };