board/aristainetos/aristainetos.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2014
   4  * Heiko Schocher, DENX Software Engineering, [email protected].
   5  *
   6  * Based on:
   7  * Copyright (C) 2012 Freescale Semiconductor, Inc.
   8  *
   9  * Author: Fabio Estevam <[email protected]>
  10  */
  11
  12 #include <command.h>
  13 #include <image.h>
  14 #include <init.h>
  15 #include <asm/arch/clock.h>
  16 #include <asm/arch/imx-regs.h>
  17 #include <asm/arch/iomux.h>
  18 #include <asm/arch/mx6-pins.h>
  19 #include <linux/errno.h>
  20 #include <asm/gpio.h>
  21 #include <asm/mach-imx/iomux-v3.h>
  22 #include <asm/mach-imx/boot_mode.h>
  23 #include <asm/mach-imx/video.h>
  24 #include <asm/arch/crm_regs.h>
  25 #include <asm/io.h>
  26 #include <asm/arch/sys_proto.h>
  27 #include <bmp_logo.h>
  28 #include <dm/root.h>
  29 #include <env.h>
  30 #include <i2c_eeprom.h>
  31 #include <i2c.h>
  32 #include <micrel.h>
  33 #include <miiphy.h>
  34 #include <lcd.h>
  35 #include <led.h>
  36 #include <power/pmic.h>
  37 #include <power/regulator.h>
  38 #include <power/da9063_pmic.h>
  39 #include <splash.h>
  40 #include <video_fb.h>
  41
  42 DECLARE_GLOBAL_DATA_PTR;
  43
  44 enum {
  45         BOARD_TYPE_4 = 4,
  46         BOARD_TYPE_7 = 7,
  47 };
  48
  49 #define ARI_BT_4 "aristainetos2_4@2"
  50 #define ARI_BT_7 "aristainetos2_7@1"
  51
  52 int board_phy_config(struct phy_device *phydev)
  53 {
  54         /* control data pad skew - devaddr = 0x02, register = 0x04 */
  55         ksz9031_phy_extended_write(phydev, 0x02,
  56                                    MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
  57                                    MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
  58         /* rx data pad skew - devaddr = 0x02, register = 0x05 */
  59         ksz9031_phy_extended_write(phydev, 0x02,
  60                                    MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
  61                                    MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
  62         /* tx data pad skew - devaddr = 0x02, register = 0x06 */
  63         ksz9031_phy_extended_write(phydev, 0x02,
  64                                    MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
  65                                    MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
  66         /* gtx and rx clock pad skew - devaddr = 0x02, register = 0x08 */
  67         ksz9031_phy_extended_write(phydev, 0x02,
  68                                    MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
  69                                    MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x03FF);
  70
  71         if (phydev->drv->config)
  72                 phydev->drv->config(phydev);
  73
  74         return 0;
  75 }
  76
  77 static int rotate_logo_one(unsigned char *out, unsigned char *in)
  78 {
  79         int   i, j;
  80
  81         for (i = 0; i < BMP_LOGO_WIDTH; i++)
  82                 for (j = 0; j < BMP_LOGO_HEIGHT; j++)
  83                         out[j * BMP_LOGO_WIDTH + BMP_LOGO_HEIGHT - 1 - i] =
  84                         in[i * BMP_LOGO_WIDTH + j];
  85         return 0;
  86 }
  87
  88 /*
  89  * Rotate the BMP_LOGO (only)
  90  * Will only work, if the logo is square, as
  91  * BMP_LOGO_HEIGHT and BMP_LOGO_WIDTH are defines, not variables
  92  */
  93 void rotate_logo(int rotations)
  94 {
  95         unsigned char out_logo[BMP_LOGO_WIDTH * BMP_LOGO_HEIGHT];
  96         struct bmp_header *header;
  97         unsigned char *in_logo;
  98         int   i, j;
  99
 100         if (BMP_LOGO_WIDTH != BMP_LOGO_HEIGHT)
 101                 return;
 102
 103         header = (struct bmp_header *)bmp_logo_bitmap;
 104         in_logo = bmp_logo_bitmap + header->data_offset;
 105
 106         /* one 90 degree rotation */
 107         if (rotations == 1  ||  rotations == 2  ||  rotations == 3)
 108                 rotate_logo_one(out_logo, in_logo);
 109
 110         /* second 90 degree rotation */
 111         if (rotations == 2  ||  rotations == 3)
 112                 rotate_logo_one(in_logo, out_logo);
 113
 114         /* third 90 degree rotation */
 115         if (rotations == 3)
 116                 rotate_logo_one(out_logo, in_logo);
 117
 118         /* copy result back to original array */
 119         if (rotations == 1  ||  rotations == 3)
 120                 for (i = 0; i < BMP_LOGO_WIDTH; i++)
 121                         for (j = 0; j < BMP_LOGO_HEIGHT; j++)
 122                                 in_logo[i * BMP_LOGO_WIDTH + j] =
 123                                 out_logo[i * BMP_LOGO_WIDTH + j];
 124 }
 125
 126 static void enable_lvds(struct display_info_t const *dev)
 127 {
 128         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 129         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 130         int reg;
 131         s32 timeout = 100000;
 132
 133         /* set PLL5 clock */
 134         reg = readl(&ccm->analog_pll_video);
 135         reg |= BM_ANADIG_PLL_VIDEO_POWERDOWN;
 136         writel(reg, &ccm->analog_pll_video);
 137
 138         /* set PLL5 to 232720000Hz */
 139         reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT;
 140         reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(0x26);
 141         reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
 142         reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0);
 143         writel(reg, &ccm->analog_pll_video);
 144
 145         writel(BF_ANADIG_PLL_VIDEO_NUM_A(0xC0238),
 146                &ccm->analog_pll_video_num);
 147         writel(BF_ANADIG_PLL_VIDEO_DENOM_B(0xF4240),
 148                &ccm->analog_pll_video_denom);
 149
 150         reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN;
 151         writel(reg, &ccm->analog_pll_video);
 152
 153         while (timeout--)
 154                 if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
 155                         break;
 156         if (timeout < 0)
 157                 printf("Warning: video pll lock timeout!\n");
 158
 159         reg = readl(&ccm->analog_pll_video);
 160         reg |= BM_ANADIG_PLL_VIDEO_ENABLE;
 161         reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS;
 162         writel(reg, &ccm->analog_pll_video);
 163
 164         /* set LDB0, LDB1 clk select to 000/000 (PLL5 clock) */
 165         reg = readl(&ccm->cs2cdr);
 166         reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
 167                  | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 168         reg |= (0 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
 169                 | (0 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
 170         writel(reg, &ccm->cs2cdr);
 171
 172         reg = readl(&ccm->cscmr2);
 173         reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
 174         writel(reg, &ccm->cscmr2);
 175
 176         reg = readl(&ccm->chsccdr);
 177         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 178                 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 179         writel(reg, &ccm->chsccdr);
 180
 181         reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
 182               | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
 183               | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH
 184               | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
 185               | IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT
 186               | IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
 187               | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
 188         writel(reg, &iomux->gpr[2]);
 189
 190         reg = readl(&iomux->gpr[3]);
 191         reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
 192                | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
 193                   << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
 194         writel(reg, &iomux->gpr[3]);
 195 }
 196
 197 static void enable_spi_display(struct display_info_t const *dev)
 198 {
 199         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 200         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 201         int reg;
 202         s32 timeout = 100000;
 203
 204 #if defined(CONFIG_VIDEO_BMP_LOGO)
 205         rotate_logo(3);  /* portrait display in landscape mode */
 206 #endif
 207
 208         reg = readl(&ccm->cs2cdr);
 209
 210         /* select pll 5 clock */
 211         reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
 212                 | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 213         writel(reg, &ccm->cs2cdr);
 214
 215         /* set PLL5 to 197994996Hz */
 216         reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT;
 217         reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(0x21);
 218         reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
 219         reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0);
 220         writel(reg, &ccm->analog_pll_video);
 221
 222         writel(BF_ANADIG_PLL_VIDEO_NUM_A(0xfbf4),
 223                &ccm->analog_pll_video_num);
 224         writel(BF_ANADIG_PLL_VIDEO_DENOM_B(0xf4240),
 225                &ccm->analog_pll_video_denom);
 226
 227         reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN;
 228         writel(reg, &ccm->analog_pll_video);
 229
 230         while (timeout--)
 231                 if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
 232                         break;
 233         if (timeout < 0)
 234                 printf("Warning: video pll lock timeout!\n");
 235
 236         reg = readl(&ccm->analog_pll_video);
 237         reg |= BM_ANADIG_PLL_VIDEO_ENABLE;
 238         reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS;
 239         writel(reg, &ccm->analog_pll_video);
 240
 241         /* set LDB0, LDB1 clk select to 000/000 (PLL5 clock) */
 242         reg = readl(&ccm->cs2cdr);
 243         reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
 244                  | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 245         reg |= (0 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
 246                 | (0 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
 247         writel(reg, &ccm->cs2cdr);
 248
 249         reg = readl(&ccm->cscmr2);
 250         reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
 251         writel(reg, &ccm->cscmr2);
 252
 253         reg = readl(&ccm->chsccdr);
 254         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 255                 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 256         reg &= ~MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK;
 257         reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET);
 258         reg &= ~MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK;
 259         reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
 260         writel(reg, &ccm->chsccdr);
 261
 262         reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
 263               | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
 264               | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH
 265               | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
 266               | IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT
 267               | IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
 268               | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
 269         writel(reg, &iomux->gpr[2]);
 270
 271         reg = readl(&iomux->gpr[3]);
 272         reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
 273                | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
 274                   << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
 275         writel(reg, &iomux->gpr[3]);
 276 }
 277
 278 static void setup_display(void)
 279 {
 280         enable_ipu_clock();
 281 }
 282
 283 static void set_gpr_register(void)
 284 {
 285         struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
 286
 287         writel(IOMUXC_GPR1_APP_CLK_REQ_N | IOMUXC_GPR1_PCIE_RDY_L23 |
 288                IOMUXC_GPR1_EXC_MON_SLVE |
 289                (2 << IOMUXC_GPR1_ADDRS0_OFFSET) |
 290                IOMUXC_GPR1_ACT_CS0,
 291                &iomuxc_regs->gpr[1]);
 292         writel(0x0, &iomuxc_regs->gpr[8]);
 293         writel(IOMUXC_GPR12_ARMP_IPG_CLK_EN | IOMUXC_GPR12_ARMP_AHB_CLK_EN |
 294                IOMUXC_GPR12_ARMP_ATB_CLK_EN | IOMUXC_GPR12_ARMP_APB_CLK_EN,
 295                &iomuxc_regs->gpr[12]);
 296 }
 297
 298 extern char __bss_start[], __bss_end[];
 299 int board_early_init_f(void)
 300 {
 301         select_ldb_di_clock_source(MXC_PLL5_CLK);
 302         set_gpr_register();
 303
 304         /*
 305          * clear bss here, so we can use spi driver
 306          * before relocation and read Environment
 307          * from spi flash.
 308          */
 309         memset(__bss_start, 0x00, __bss_end - __bss_start);
 310
 311         return 0;
 312 }
 313
 314 static void setup_one_led(char *label, int state)
 315 {
 316         struct udevice *dev;
 317         int ret;
 318
 319         ret = led_get_by_label(label, &dev);
 320         if (ret == 0)
 321                 led_set_state(dev, state);
 322 }
 323
 324 static void setup_board_gpio(void)
 325 {
 326         setup_one_led("led_ena", LEDST_ON);
 327         /* switch off Status LEDs */
 328         setup_one_led("led_yellow", LEDST_OFF);
 329         setup_one_led("led_red", LEDST_OFF);
 330         setup_one_led("led_green", LEDST_OFF);
 331         setup_one_led("led_blue", LEDST_OFF);
 332 }
 333
 334 #define ARI_RESC_FMT "setenv rescue_reason setenv bootargs \\${bootargs}" \
 335                 " rescueReason=%d "
 336
 337 static void aristainetos_run_rescue_command(int reason)
 338 {
 339         char rescue_reason_command[80];
 340
 341         sprintf(rescue_reason_command, ARI_RESC_FMT, reason);
 342         run_command(rescue_reason_command, 0);
 343 }
 344
 345 static int aristainetos_eeprom(void)
 346 {
 347         struct udevice *dev;
 348         int off;
 349         int ret;
 350         u8 data[0x10];
 351         u8 rescue_reason;
 352
 353         off = fdt_path_offset(gd->fdt_blob, "eeprom0");
 354         if (off < 0) {
 355                 printf("%s: No eeprom0 path offset\n", __func__);
 356                 return off;
 357         }
 358
 359         ret = uclass_get_device_by_of_offset(UCLASS_I2C_EEPROM, off, &dev);
 360         if (ret) {
 361                 printf("%s: Could not find EEPROM\n", __func__);
 362                 return ret;
 363         }
 364
 365         ret = i2c_set_chip_offset_len(dev, 2);
 366         if (ret)
 367                 return ret;
 368
 369         ret = i2c_eeprom_read(dev, 0x1ff0, (uint8_t *)data, 6);
 370         if (ret) {
 371                 printf("%s: Could not read EEPROM\n", __func__);
 372                 return ret;
 373         }
 374
 375         if (strncmp((char *)&data[3], "ReScUe", 6) == 0) {
 376                 rescue_reason = *(uint8_t *)&data[9];
 377                 memset(&data[3], 0xff, 7);
 378                 i2c_eeprom_write(dev, 0x1ff0, (uint8_t *)&data[3], 7);
 379                 printf("\nBooting into Rescue System (EEPROM)\n");
 380                 aristainetos_run_rescue_command(rescue_reason);
 381                 run_command("run rescue_load_fit rescueboot", 0);
 382         } else if (strncmp((char *)data, "DeF", 3) == 0) {
 383                 memset(data, 0xff, 3);
 384                 i2c_eeprom_write(dev, 0x1ff0, (uint8_t *)data, 3);
 385                 printf("\nClear u-boot environment (set back to defaults)\n");
 386                 run_command("run default_env; saveenv; saveenv", 0);
 387         }
 388
 389         return 0;
 390 };
 391
 392 static void aristainetos_bootmode_settings(void)
 393 {
 394         struct gpio_desc *desc;
 395         struct src *psrc = (struct src *)SRC_BASE_ADDR;
 396         unsigned int sbmr1 = readl(&psrc->sbmr1);
 397         char *my_bootdelay;
 398         char bootmode = 0;
 399         int ret;
 400
 401         /*
 402          * Check the boot-source. If booting from NOR Flash,
 403          * disable bootdelay
 404          */
 405         ret = gpio_hog_lookup_name("bootsel0", &desc);
 406         if (!ret)
 407                 bootmode |= (dm_gpio_get_value(desc) ? 1 : 0) << 0;
 408         ret = gpio_hog_lookup_name("bootsel1", &desc);
 409         if (!ret)
 410                 bootmode |= (dm_gpio_get_value(desc) ? 1 : 0) << 1;
 411         ret = gpio_hog_lookup_name("bootsel2", &desc);
 412         if (!ret)
 413                 bootmode |= (dm_gpio_get_value(desc) ? 1 : 0) << 2;
 414
 415         if (bootmode == 7) {
 416                 my_bootdelay = env_get("nor_bootdelay");
 417                 if (my_bootdelay)
 418                         env_set("bootdelay", my_bootdelay);
 419                 else
 420                         env_set("bootdelay", "-2");
 421         }
 422
 423         if (sbmr1 & 0x40) {
 424                 env_set("bootmode", "1");
 425                 printf("SD bootmode jumper set!\n");
 426         } else {
 427                 env_set("bootmode", "0");
 428         }
 429
 430         /* read out some jumper values*/
 431         ret = gpio_hog_lookup_name("env_reset", &desc);
 432         if (!ret) {
 433                 if (dm_gpio_get_value(desc)) {
 434                         printf("\nClear env (set back to defaults)\n");
 435                         run_command("run default_env; saveenv; saveenv", 0);
 436                 }
 437         }
 438         ret = gpio_hog_lookup_name("boot_rescue", &desc);
 439         if (!ret) {
 440                 if (dm_gpio_get_value(desc)) {
 441                         aristainetos_run_rescue_command(16);
 442                         run_command("run rescue_xload_boot", 0);
 443                 }
 444         }
 445 }
 446
 447 #if defined(CONFIG_DM_PMIC_DA9063)
 448 /*
 449  * On the aristainetos2c boards the PMIC needs to be initialized,
 450  * because the Ethernet PHY uses a different regulator that is not
 451  * setup per hardware default. This does not influence the other versions
 452  * as this regulator isn't used there at all.
 453  *
 454  * Unfortunately we have not yet a interface to setup all
 455  * values we need.
 456  */
 457 static int setup_pmic_voltages(void)
 458 {
 459         struct udevice *dev;
 460         int off;
 461         int ret;
 462
 463         off = fdt_path_offset(gd->fdt_blob, "pmic0");
 464         if (off < 0) {
 465                 printf("%s: No pmic path offset\n", __func__);
 466                 return off;
 467         }
 468
 469         ret = uclass_get_device_by_of_offset(UCLASS_PMIC, off, &dev);
 470         if (ret) {
 471                 printf("%s: Could not find PMIC\n", __func__);
 472                 return ret;
 473         }
 474
 475         pmic_reg_write(dev, DA9063_REG_PAGE_CON, 0x01);
 476         pmic_reg_write(dev, DA9063_REG_BPRO_CFG, 0xc1);
 477         ret = pmic_reg_read(dev, DA9063_REG_BUCK_ILIM_B);
 478         if (ret < 0) {
 479                 printf("%s: error %d get register\n", __func__, ret);
 480                 return ret;
 481         }
 482         ret &= 0xf0;
 483         ret |= 0x09;
 484         pmic_reg_write(dev, DA9063_REG_BUCK_ILIM_B, ret);
 485         pmic_reg_write(dev, DA9063_REG_VBPRO_A, 0x43);
 486         pmic_reg_write(dev, DA9063_REG_VBPRO_B, 0xc3);
 487
 488         return 0;
 489 }
 490 #else
 491 static int setup_pmic_voltages(void)
 492 {
 493         return 0;
 494 }
 495 #endif
 496
 497 int board_late_init(void)
 498 {
 499         int x, y;
 500
 501         led_default_state();
 502         splash_get_pos(&x, &y);
 503         bmp_display((ulong)&bmp_logo_bitmap[0], x, y);
 504
 505         aristainetos_bootmode_settings();
 506
 507         /* eeprom work */
 508         aristainetos_eeprom();
 509
 510         /* set board_type */
 511         if (gd->board_type == BOARD_TYPE_4)
 512                 env_set("board_type", ARI_BT_4);
 513         else
 514                 env_set("board_type", ARI_BT_7);
 515
 516         if (setup_pmic_voltages())
 517                 printf("Error setup PMIC\n");
 518
 519         return 0;
 520 }
 521
 522 int dram_init(void)
 523 {
 524         gd->ram_size = imx_ddr_size();
 525
 526         return 0;
 527 }
 528
 529 struct display_info_t const displays[] = {
 530         {
 531                 .bus    = -1,
 532                 .addr   = 0,
 533                 .pixfmt = IPU_PIX_FMT_RGB24,
 534                 .detect = NULL,
 535                 .enable = enable_lvds,
 536                 .mode   = {
 537                         .name           = "lb07wv8",
 538                         .refresh        = 60,
 539                         .xres           = 800,
 540                         .yres           = 480,
 541                         .pixclock       = 30066,
 542                         .left_margin    = 88,
 543                         .right_margin   = 88,
 544                         .upper_margin   = 20,
 545                         .lower_margin   = 20,
 546                         .hsync_len      = 80,
 547                         .vsync_len      = 5,
 548                         .sync           = FB_SYNC_EXT,
 549                         .vmode          = FB_VMODE_NONINTERLACED
 550                 }
 551         }
 552 #if ((CONFIG_SYS_BOARD_VERSION == 2) || \
 553         (CONFIG_SYS_BOARD_VERSION == 3) || \
 554         (CONFIG_SYS_BOARD_VERSION == 4) || \
 555         (CONFIG_SYS_BOARD_VERSION == 5))
 556         , {
 557                 .bus    = -1,
 558                 .addr   = 0,
 559                 .pixfmt = IPU_PIX_FMT_RGB24,
 560                 .detect = NULL,
 561                 .enable = enable_spi_display,
 562                 .mode   = {
 563                         .name           = "lg4573",
 564                         .refresh        = 57,
 565                         .xres           = 480,
 566                         .yres           = 800,
 567                         .pixclock       = 37037,
 568                         .left_margin    = 59,
 569                         .right_margin   = 10,
 570                         .upper_margin   = 15,
 571                         .lower_margin   = 15,
 572                         .hsync_len      = 10,
 573                         .vsync_len      = 15,
 574                         .sync           = FB_SYNC_EXT | FB_SYNC_HOR_HIGH_ACT |
 575                                           FB_SYNC_VERT_HIGH_ACT,
 576                         .vmode          = FB_VMODE_NONINTERLACED
 577                 }
 578         }
 579 #endif
 580 };
 581 size_t display_count = ARRAY_SIZE(displays);
 582
 583 #if defined(CONFIG_MTD_RAW_NAND)
 584 iomux_v3_cfg_t nfc_pads[] = {
 585         MX6_PAD_NANDF_CLE__NAND_CLE             | MUX_PAD_CTRL(NO_PAD_CTRL),
 586         MX6_PAD_NANDF_ALE__NAND_ALE             | MUX_PAD_CTRL(NO_PAD_CTRL),
 587         MX6_PAD_NANDF_WP_B__NAND_WP_B   | MUX_PAD_CTRL(NO_PAD_CTRL),
 588         MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL),
 589         MX6_PAD_NANDF_CS0__NAND_CE0_B           | MUX_PAD_CTRL(NO_PAD_CTRL),
 590         MX6_PAD_SD4_CMD__NAND_RE_B              | MUX_PAD_CTRL(NO_PAD_CTRL),
 591         MX6_PAD_SD4_CLK__NAND_WE_B              | MUX_PAD_CTRL(NO_PAD_CTRL),
 592         MX6_PAD_NANDF_D0__NAND_DATA00           | MUX_PAD_CTRL(NO_PAD_CTRL),
 593         MX6_PAD_NANDF_D1__NAND_DATA01           | MUX_PAD_CTRL(NO_PAD_CTRL),
 594         MX6_PAD_NANDF_D2__NAND_DATA02           | MUX_PAD_CTRL(NO_PAD_CTRL),
 595         MX6_PAD_NANDF_D3__NAND_DATA03           | MUX_PAD_CTRL(NO_PAD_CTRL),
 596         MX6_PAD_NANDF_D4__NAND_DATA04           | MUX_PAD_CTRL(NO_PAD_CTRL),
 597         MX6_PAD_NANDF_D5__NAND_DATA05           | MUX_PAD_CTRL(NO_PAD_CTRL),
 598         MX6_PAD_NANDF_D6__NAND_DATA06           | MUX_PAD_CTRL(NO_PAD_CTRL),
 599         MX6_PAD_NANDF_D7__NAND_DATA07           | MUX_PAD_CTRL(NO_PAD_CTRL),
 600         MX6_PAD_SD4_DAT0__NAND_DQS              | MUX_PAD_CTRL(NO_PAD_CTRL),
 601 };
 602
 603 static void setup_gpmi_nand(void)
 604 {
 605         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 606
 607         /* config gpmi nand iomux */
 608         imx_iomux_v3_setup_multiple_pads(nfc_pads,
 609                                          ARRAY_SIZE(nfc_pads));
 610
 611         /* gate ENFC_CLK_ROOT clock first,before clk source switch */
 612         clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
 613
 614         /* config gpmi and bch clock to 100 MHz */
 615         clrsetbits_le32(&mxc_ccm->cs2cdr,
 616                         MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
 617                         MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
 618                         MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
 619                         MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
 620                         MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
 621                         MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
 622
 623         /* enable ENFC_CLK_ROOT clock */
 624         setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
 625
 626         /* enable gpmi and bch clock gating */
 627         setbits_le32(&mxc_ccm->CCGR4,
 628                      MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
 629                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
 630                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
 631                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
 632                      MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
 633
 634         /* enable apbh clock gating */
 635         setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
 636 }
 637 #else
 638 static void setup_gpmi_nand(void)
 639 {
 640 }
 641 #endif
 642
 643 int board_init(void)
 644 {
 645         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 646
 647         /* address of boot parameters */
 648         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 649
 650         setup_board_gpio();
 651         setup_gpmi_nand();
 652         setup_display();
 653
 654         /* GPIO_1 for USB_OTG_ID */
 655         clrsetbits_le32(&iomux->gpr[1], IOMUXC_GPR1_USB_OTG_ID_SEL_MASK, 0);
 656         return 0;
 657 }
 658
 659 int board_fit_config_name_match(const char *name)
 660 {
 661         if (gd->board_type == BOARD_TYPE_4 &&
 662             strchr(name, 0x34))
 663                 return 0;
 664
 665         if (gd->board_type == BOARD_TYPE_7 &&
 666             strchr(name, 0x37))
 667                 return 0;
 668
 669         return -1;
 670 }
 671
 672 static void do_board_detect(void)
 673 {
 674         int ret;
 675         char s[30];
 676
 677         /* default use board type 7 */
 678         gd->board_type = BOARD_TYPE_7;
 679         if (env_init())
 680                 return;
 681
 682         ret = env_get_f("panel", s, sizeof(s));
 683         if (ret < 0)
 684                 return;
 685
 686         if (!strncmp("lg4573", s, 6))
 687                 gd->board_type = BOARD_TYPE_4;
 688 }
 689
 690 #ifdef CONFIG_DTB_RESELECT
 691 int embedded_dtb_select(void)
 692 {
 693         int rescan;
 694
 695         do_board_detect();
 696         fdtdec_resetup(&rescan);
 697
 698         return 0;
 699 }
 700 #endif