drivers/memory/ti-gpmc.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Texas Instruments GPMC Driver
   4  *
   5  * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
   6  */
   7
   8 #include <asm/io.h>
   9 #include <clk.h>
  10 #include <dm.h>
  11 #include <dm/device-internal.h>
  12 #include <dm/device_compat.h>
  13 #include <dm/devres.h>
  14 #include <dm/lists.h>
  15 #include <linux/mtd/omap_gpmc.h>
  16 #include <linux/ioport.h>
  17 #include <linux/io.h>
  18 #include <linux/sizes.h>
  19 #include "ti-gpmc.h"
  20
  21 enum gpmc_clk_domain {
  22         GPMC_CD_FCLK,
  23         GPMC_CD_CLK
  24 };
  25
  26 struct gpmc_cs_data {
  27         const char *name;
  28 #define GPMC_CS_RESERVED        BIT(0)
  29         u32 flags;
  30 };
  31
  32 struct ti_gpmc {
  33         void __iomem *base;
  34         u32 cs_num;
  35         u32 nr_waitpins;
  36         struct clk *l3_clk;
  37         u32 capability_flags;
  38         struct resource data;
  39 };
  40
  41 static struct gpmc_cs_data gpmc_cs[GPMC_CS_NUM];
  42 static unsigned int gpmc_cs_num = GPMC_CS_NUM;
  43 static unsigned int gpmc_nr_waitpins;
  44 static unsigned int gpmc_capability;
  45 static void __iomem *gpmc_base;
  46 static struct clk *gpmc_l3_clk;
  47
  48 /* Public, as required by nand/raw/omap_gpmc.c */
  49 const struct gpmc *gpmc_cfg;
  50
  51 /*
  52  * The first 1MB of GPMC address space is typically mapped to
  53  * the internal ROM. Never allocate the first page, to
  54  * facilitate bug detection; even if we didn't boot from ROM.
  55  * As GPMC minimum partition size is 16MB we can only start from
  56  * there.
  57  */
  58 #define GPMC_MEM_START          0x1000000
  59 #define GPMC_MEM_END            0x3FFFFFFF
  60
  61 static void gpmc_write_reg(int idx, u32 val)
  62 {
  63         writel_relaxed(val, gpmc_base + idx);
  64 }
  65
  66 static u32 gpmc_read_reg(int idx)
  67 {
  68         return readl_relaxed(gpmc_base + idx);
  69 }
  70
  71 static void gpmc_cs_write_reg(int cs, int idx, u32 val)
  72 {
  73         void __iomem *reg_addr;
  74
  75         reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
  76         writel_relaxed(val, reg_addr);
  77 }
  78
  79 static u32 gpmc_cs_read_reg(int cs, int idx)
  80 {
  81         void __iomem *reg_addr;
  82
  83         reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
  84         return readl_relaxed(reg_addr);
  85 }
  86
  87 static unsigned long gpmc_get_fclk_period(void)
  88 {
  89         unsigned long rate = clk_get_rate(gpmc_l3_clk);
  90
  91         rate /= 1000;
  92         rate = 1000000000 / rate;       /* In picoseconds */
  93
  94         return rate;
  95 }
  96
  97 /**
  98  * gpmc_get_clk_period - get period of selected clock domain in ps
  99  * @cs: Chip Select Region.
 100  * @cd: Clock Domain.
 101  *
 102  * GPMC_CS_CONFIG1 GPMCFCLKDIVIDER for cs has to be setup
 103  * prior to calling this function with GPMC_CD_CLK.
 104  */
 105 static unsigned long gpmc_get_clk_period(int cs, enum gpmc_clk_domain cd)
 106 {
 107         unsigned long tick_ps = gpmc_get_fclk_period();
 108         u32 l;
 109         int div;
 110
 111         switch (cd) {
 112         case GPMC_CD_CLK:
 113                 /* get current clk divider */
 114                 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
 115                 div = (l & 0x03) + 1;
 116                 /* get GPMC_CLK period */
 117                 tick_ps *= div;
 118                 break;
 119         case GPMC_CD_FCLK:
 120         default:
 121                 break;
 122         }
 123
 124         return tick_ps;
 125 }
 126
 127 static unsigned int gpmc_ns_to_clk_ticks(unsigned int time_ns, int cs,
 128                                          enum gpmc_clk_domain cd)
 129 {
 130         unsigned long tick_ps;
 131
 132         /* Calculate in picosecs to yield more exact results */
 133         tick_ps = gpmc_get_clk_period(cs, cd);
 134
 135         return (time_ns * 1000 + tick_ps - 1) / tick_ps;
 136 }
 137
 138 static unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
 139 {
 140         return gpmc_ns_to_clk_ticks(time_ns, /* any CS */ 0, GPMC_CD_FCLK);
 141 }
 142
 143 static unsigned int gpmc_ps_to_ticks(unsigned int time_ps)
 144 {
 145         unsigned long tick_ps;
 146
 147         /* Calculate in picosecs to yield more exact results */
 148         tick_ps = gpmc_get_fclk_period();
 149
 150         return (time_ps + tick_ps - 1) / tick_ps;
 151 }
 152
 153 static __maybe_unused unsigned int gpmc_clk_ticks_to_ns(unsigned int ticks, int cs,
 154                                                         enum gpmc_clk_domain cd)
 155 {
 156         return ticks * gpmc_get_clk_period(cs, cd) / 1000;
 157 }
 158
 159 static inline void gpmc_cs_modify_reg(int cs, int reg, u32 mask, bool value)
 160 {
 161         u32 l;
 162
 163         l = gpmc_cs_read_reg(cs, reg);
 164         if (value)
 165                 l |= mask;
 166         else
 167                 l &= ~mask;
 168         gpmc_cs_write_reg(cs, reg, l);
 169 }
 170
 171 static void gpmc_cs_bool_timings(int cs, const struct gpmc_bool_timings *p)
 172 {
 173         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG1,
 174                            GPMC_CONFIG1_TIME_PARA_GRAN,
 175                            p->time_para_granularity);
 176         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG2,
 177                            GPMC_CONFIG2_CSEXTRADELAY, p->cs_extra_delay);
 178         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG3,
 179                            GPMC_CONFIG3_ADVEXTRADELAY, p->adv_extra_delay);
 180         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4,
 181                            GPMC_CONFIG4_OEEXTRADELAY, p->oe_extra_delay);
 182         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4,
 183                            GPMC_CONFIG4_WEEXTRADELAY, p->we_extra_delay);
 184         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6,
 185                            GPMC_CONFIG6_CYCLE2CYCLESAMECSEN,
 186                            p->cycle2cyclesamecsen);
 187         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6,
 188                            GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN,
 189                            p->cycle2cyclediffcsen);
 190 }
 191
 192 #if IS_ENABLED(CONFIG_TI_GPMC_DEBUG)
 193 /**
 194  * get_gpmc_timing_reg - read a timing parameter and print DTS settings for it.
 195  * @cs:      Chip Select Region
 196  * @reg:     GPMC_CS_CONFIGn register offset.
 197  * @st_bit:  Start Bit
 198  * @end_bit: End Bit. Must be >= @st_bit.
 199  * @max:     Maximum parameter value (before optional @shift).
 200  *           If 0, maximum is as high as @st_bit and @end_bit allow.
 201  * @name:    DTS node name, w/o "gpmc,"
 202  * @cd:      Clock Domain of timing parameter.
 203  * @shift:   Parameter value left shifts @shift, which is then printed instead of value.
 204  * @raw:     Raw Format Option.
 205  *           raw format:  gpmc,name = <value>
 206  *           tick format: gpmc,name = <value> /&zwj;* x ns -- y ns; x ticks *&zwj;/
 207  *           Where x ns -- y ns result in the same tick value.
 208  *           When @max is exceeded, "invalid" is printed inside comment.
 209  * @noval:   Parameter values equal to 0 are not printed.
 210  * @return:  Specified timing parameter (after optional @shift).
 211  *
 212  */
 213 static int get_gpmc_timing_reg(/* timing specifiers */
 214         int cs, int reg, int st_bit, int end_bit, int max,
 215         const char *name, const enum gpmc_clk_domain cd,
 216         /* value transform */
 217         int shift,
 218         /* format specifiers */
 219         bool raw, bool noval)
 220 {
 221         u32 l;
 222         int nr_bits;
 223         int mask;
 224         bool invalid;
 225
 226         l = gpmc_cs_read_reg(cs, reg);
 227         nr_bits = end_bit - st_bit + 1;
 228         mask = (1 << nr_bits) - 1;
 229         l = (l >> st_bit) & mask;
 230         if (!max)
 231                 max = mask;
 232         invalid = l > max;
 233         if (shift)
 234                 l = (shift << l);
 235         if (noval && l == 0)
 236                 return 0;
 237         if (!raw) {
 238                 /* DTS tick format for timings in ns */
 239                 unsigned int time_ns;
 240                 unsigned int time_ns_min = 0;
 241
 242                 if (l)
 243                         time_ns_min = gpmc_clk_ticks_to_ns(l - 1, cs, cd) + 1;
 244                 time_ns = gpmc_clk_ticks_to_ns(l, cs, cd);
 245                 printf("gpmc,%s = <%u>; /* %u ns - %u ns; %i ticks%s*/\n",
 246                        name, time_ns, time_ns_min, time_ns, l,
 247                        invalid ? "; invalid " : " ");
 248         } else {
 249                 /* raw format */
 250                 printf("gpmc,%s = <%u>;%s\n", name, l,
 251                        invalid ? " /* invalid */" : "");
 252         }
 253
 254         return l;
 255 }
 256
 257 #define GPMC_PRINT_CONFIG(cs, config) \
 258         printf("CS%i %s: 0x%08x\n", cs, #config, \
 259                 gpmc_cs_read_reg(cs, config))
 260 #define GPMC_GET_RAW(reg, st, end, field) \
 261         get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 1, 0)
 262 #define GPMC_GET_RAW_MAX(reg, st, end, max, field) \
 263         get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, GPMC_CD_FCLK, 0, 1, 0)
 264 #define GPMC_GET_RAW_BOOL(reg, st, end, field) \
 265         get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 1, 1)
 266 #define GPMC_GET_RAW_SHIFT_MAX(reg, st, end, shift, max, field) \
 267         get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, GPMC_CD_FCLK, (shift), 1, 1)
 268 #define GPMC_GET_TICKS(reg, st, end, field) \
 269         get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 0, 0)
 270 #define GPMC_GET_TICKS_CD(reg, st, end, field, cd) \
 271         get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, (cd), 0, 0, 0)
 272 #define GPMC_GET_TICKS_CD_MAX(reg, st, end, max, field, cd) \
 273         get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, (cd), 0, 0, 0)
 274
 275 static void gpmc_show_regs(int cs, const char *desc)
 276 {
 277         printf("gpmc cs%i %s:\n", cs, desc);
 278         GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG1);
 279         GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG2);
 280         GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG3);
 281         GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG4);
 282         GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG5);
 283         GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG6);
 284 }
 285
 286 /*
 287  * Note that gpmc,wait-pin handing wrongly assumes bit 8 is available,
 288  * see commit c9fb809.
 289  */
 290 static void gpmc_cs_show_timings(int cs, const char *desc)
 291 {
 292         gpmc_show_regs(cs, desc);
 293
 294         printf("gpmc cs%i access configuration:\n", cs);
 295         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1,  4,  4, "time-para-granularity");
 296         GPMC_GET_RAW(GPMC_CS_CONFIG1,  8,  9, "mux-add-data");
 297         GPMC_GET_RAW_SHIFT_MAX(GPMC_CS_CONFIG1, 12, 13, 1,
 298                                GPMC_CONFIG1_DEVICESIZE_MAX, "device-width");
 299         GPMC_GET_RAW(GPMC_CS_CONFIG1, 16, 17, "wait-pin");
 300         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 21, 21, "wait-on-write");
 301         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 22, 22, "wait-on-read");
 302         GPMC_GET_RAW_SHIFT_MAX(GPMC_CS_CONFIG1, 23, 24, 4,
 303                                GPMC_CONFIG1_ATTACHEDDEVICEPAGELENGTH_MAX,
 304                                "burst-length");
 305         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 27, 27, "sync-write");
 306         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 28, 28, "burst-write");
 307         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 29, 29, "gpmc,sync-read");
 308         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 30, 30, "burst-read");
 309         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 31, 31, "burst-wrap");
 310
 311         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG2,  7,  7, "cs-extra-delay");
 312
 313         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG3,  7,  7, "adv-extra-delay");
 314
 315         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG4, 23, 23, "we-extra-delay");
 316         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG4,  7,  7, "oe-extra-delay");
 317
 318         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG6,  7,  7, "cycle2cycle-samecsen");
 319         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG6,  6,  6, "cycle2cycle-diffcsen");
 320
 321         printf("gpmc cs%i timings configuration:\n", cs);
 322         GPMC_GET_TICKS(GPMC_CS_CONFIG2,  0,  3, "cs-on-ns");
 323         GPMC_GET_TICKS(GPMC_CS_CONFIG2,  8, 12, "cs-rd-off-ns");
 324         GPMC_GET_TICKS(GPMC_CS_CONFIG2, 16, 20, "cs-wr-off-ns");
 325
 326         GPMC_GET_TICKS(GPMC_CS_CONFIG3,  0,  3, "adv-on-ns");
 327         GPMC_GET_TICKS(GPMC_CS_CONFIG3,  8, 12, "adv-rd-off-ns");
 328         GPMC_GET_TICKS(GPMC_CS_CONFIG3, 16, 20, "adv-wr-off-ns");
 329         if (gpmc_capability & GPMC_HAS_MUX_AAD) {
 330                 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 4, 6, "adv-aad-mux-on-ns");
 331                 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 24, 26,
 332                                "adv-aad-mux-rd-off-ns");
 333                 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 28, 30,
 334                                "adv-aad-mux-wr-off-ns");
 335         }
 336
 337         GPMC_GET_TICKS(GPMC_CS_CONFIG4,  0,  3, "oe-on-ns");
 338         GPMC_GET_TICKS(GPMC_CS_CONFIG4,  8, 12, "oe-off-ns");
 339         if (gpmc_capability & GPMC_HAS_MUX_AAD) {
 340                 GPMC_GET_TICKS(GPMC_CS_CONFIG4,  4,  6, "oe-aad-mux-on-ns");
 341                 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 13, 15, "oe-aad-mux-off-ns");
 342         }
 343         GPMC_GET_TICKS(GPMC_CS_CONFIG4, 16, 19, "we-on-ns");
 344         GPMC_GET_TICKS(GPMC_CS_CONFIG4, 24, 28, "we-off-ns");
 345
 346         GPMC_GET_TICKS(GPMC_CS_CONFIG5,  0,  4, "rd-cycle-ns");
 347         GPMC_GET_TICKS(GPMC_CS_CONFIG5,  8, 12, "wr-cycle-ns");
 348         GPMC_GET_TICKS(GPMC_CS_CONFIG5, 16, 20, "access-ns");
 349
 350         GPMC_GET_TICKS(GPMC_CS_CONFIG5, 24, 27, "page-burst-access-ns");
 351
 352         GPMC_GET_TICKS(GPMC_CS_CONFIG6, 0, 3, "bus-turnaround-ns");
 353         GPMC_GET_TICKS(GPMC_CS_CONFIG6, 8, 11, "cycle2cycle-delay-ns");
 354
 355         GPMC_GET_TICKS_CD_MAX(GPMC_CS_CONFIG1, 18, 19,
 356                               GPMC_CONFIG1_WAITMONITORINGTIME_MAX,
 357                               "wait-monitoring-ns", GPMC_CD_CLK);
 358         GPMC_GET_TICKS_CD_MAX(GPMC_CS_CONFIG1, 25, 26,
 359                               GPMC_CONFIG1_CLKACTIVATIONTIME_MAX,
 360                               "clk-activation-ns", GPMC_CD_FCLK);
 361
 362         GPMC_GET_TICKS(GPMC_CS_CONFIG6, 16, 19, "wr-data-mux-bus-ns");
 363         GPMC_GET_TICKS(GPMC_CS_CONFIG6, 24, 28, "wr-access-ns");
 364 }
 365 #else
 366 static inline void gpmc_cs_show_timings(int cs, const char *desc)
 367 {
 368 }
 369 #endif
 370
 371 /**
 372  * set_gpmc_timing_reg - set a single timing parameter for Chip Select Region.
 373  * Caller is expected to have initialized CONFIG1 GPMCFCLKDIVIDER
 374  * prior to calling this function with @cd equal to GPMC_CD_CLK.
 375  *
 376  * @cs:      Chip Select Region.
 377  * @reg:     GPMC_CS_CONFIGn register offset.
 378  * @st_bit:  Start Bit
 379  * @end_bit: End Bit. Must be >= @st_bit.
 380  * @max:     Maximum parameter value.
 381  *           If 0, maximum is as high as @st_bit and @end_bit allow.
 382  * @time:    Timing parameter in ns.
 383  * @cd:      Timing parameter clock domain.
 384  * @name:    Timing parameter name.
 385  * @return:  0 on success, -1 on error.
 386  */
 387 static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit, int max,
 388                                int time, enum gpmc_clk_domain cd, const char *name)
 389 {
 390         u32 l;
 391         int ticks, mask, nr_bits;
 392
 393         if (time == 0)
 394                 ticks = 0;
 395         else
 396                 ticks = gpmc_ns_to_clk_ticks(time, cs, cd);
 397         nr_bits = end_bit - st_bit + 1;
 398         mask = (1 << nr_bits) - 1;
 399
 400         if (!max)
 401                 max = mask;
 402
 403         if (ticks > max) {
 404                 pr_err("%s: GPMC CS%d: %s %d ns, %d ticks > %d ticks\n",
 405                        __func__, cs, name, time, ticks, max);
 406
 407                 return -1;
 408         }
 409
 410         l = gpmc_cs_read_reg(cs, reg);
 411         if (IS_ENABLED(CONFIG_TI_GPMC_DEBUG)) {
 412                 printf("GPMC CS%d: %-17s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n",
 413                        cs, name, ticks, gpmc_get_clk_period(cs, cd) * ticks / 1000,
 414                        (l >> st_bit) & mask, time);
 415         }
 416
 417         l &= ~(mask << st_bit);
 418         l |= ticks << st_bit;
 419         gpmc_cs_write_reg(cs, reg, l);
 420
 421         return 0;
 422 }
 423
 424 /**
 425  * gpmc_calc_waitmonitoring_divider - calculate proper GPMCFCLKDIVIDER based on WAITMONITORINGTIME
 426  * WAITMONITORINGTIME will be _at least_ as long as desired, i.e.
 427  * read  --> don't sample bus too early
 428  * write --> data is longer on bus
 429  *
 430  * Formula:
 431  * gpmc_clk_div + 1 = ceil(ceil(waitmonitoringtime_ns / gpmc_fclk_ns)
 432  *                    / waitmonitoring_ticks)
 433  * WAITMONITORINGTIME resulting in 0 or 1 tick with div = 1 are caught by
 434  * div <= 0 check.
 435  *
 436  * @wait_monitoring: WAITMONITORINGTIME in ns.
 437  * @return:          -1 on failure to scale, else proper divider > 0.
 438  */
 439 static int gpmc_calc_waitmonitoring_divider(unsigned int wait_monitoring)
 440 {
 441         int div = gpmc_ns_to_ticks(wait_monitoring);
 442
 443         div += GPMC_CONFIG1_WAITMONITORINGTIME_MAX - 1;
 444         div /= GPMC_CONFIG1_WAITMONITORINGTIME_MAX;
 445
 446         if (div > 4)
 447                 return -1;
 448         if (div <= 0)
 449                 div = 1;
 450
 451         return div;
 452 }
 453
 454 /**
 455  * gpmc_calc_divider - calculate GPMC_FCLK divider for sync_clk GPMC_CLK period.
 456  * @sync_clk: GPMC_CLK period in ps.
 457  * @return:   Returns at least 1 if GPMC_FCLK can be divided to GPMC_CLK.
 458  *            Else, returns -1.
 459  */
 460 static int gpmc_calc_divider(unsigned int sync_clk)
 461 {
 462         int div = gpmc_ps_to_ticks(sync_clk);
 463
 464         if (div > 4)
 465                 return -1;
 466         if (div <= 0)
 467                 div = 1;
 468
 469         return div;
 470 }
 471
 472 /**
 473  * gpmc_cs_set_timings - program timing parameters for Chip Select Region.
 474  * @cs:     Chip Select Region.
 475  * @t:      GPMC timing parameters.
 476  * @s:      GPMC timing settings.
 477  * @return: 0 on success, -1 on error.
 478  */
 479 static int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t,
 480                                const struct gpmc_settings *s)
 481 {
 482         int div, ret;
 483         u32 l;
 484
 485         div = gpmc_calc_divider(t->sync_clk);
 486         if (div < 0)
 487                 return -EINVAL;
 488
 489         /*
 490          * See if we need to change the divider for waitmonitoringtime.
 491          *
 492          * Calculate GPMCFCLKDIVIDER independent of gpmc,sync-clk-ps in DT for
 493          * pure asynchronous accesses, i.e. both read and write asynchronous.
 494          * However, only do so if WAITMONITORINGTIME is actually used, i.e.
 495          * either WAITREADMONITORING or WAITWRITEMONITORING is set.
 496          *
 497          * This statement must not change div to scale async WAITMONITORINGTIME
 498          * to protect mixed synchronous and asynchronous accesses.
 499          *
 500          * We raise an error later if WAITMONITORINGTIME does not fit.
 501          */
 502         if (!s->sync_read && !s->sync_write &&
 503             (s->wait_on_read || s->wait_on_write)
 504            ) {
 505                 div = gpmc_calc_waitmonitoring_divider(t->wait_monitoring);
 506                 if (div < 0) {
 507                         pr_err("%s: waitmonitoringtime %3d ns too large for greatest gpmcfclkdivider.\n",
 508                                __func__,
 509                                t->wait_monitoring
 510                                );
 511                         return -ENXIO;
 512                 }
 513         }
 514
 515         ret = 0;
 516         ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG2, 0, 3, 0, t->cs_on,
 517                                    GPMC_CD_FCLK, "cs_on");
 518         ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG2, 8, 12, 0, t->cs_rd_off,
 519                                    GPMC_CD_FCLK, "cs_rd_off");
 520         ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG2, 16, 20, 0, t->cs_wr_off,
 521                                    GPMC_CD_FCLK, "cs_wr_off");
 522         if (ret)
 523                 return -ENXIO;
 524
 525         ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG3, 0, 3, 0, t->adv_on,
 526                                    GPMC_CD_FCLK, "adv_on");
 527         ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG3, 8, 12, 0, t->adv_rd_off,
 528                                    GPMC_CD_FCLK, "adv_rd_off");
 529         ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG3, 16, 20, 0, t->adv_wr_off,
 530                                    GPMC_CD_FCLK, "adv_wr_off");
 531         if (ret)
 532                 return -ENXIO;
 533
 534         if (gpmc_capability & GPMC_HAS_MUX_AAD) {
 535                 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG3, 4, 6, 0,
 536                                            t->adv_aad_mux_on, GPMC_CD_FCLK,
 537                                            "adv_aad_mux_on");
 538                 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG3, 24, 26, 0,
 539                                            t->adv_aad_mux_rd_off, GPMC_CD_FCLK,
 540                                            "adv_aad_mux_rd_off");
 541                 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG3, 28, 30, 0,
 542                                            t->adv_aad_mux_wr_off, GPMC_CD_FCLK,
 543                                            "adv_aad_mux_wr_off");
 544                 if (ret)
 545                         return -ENXIO;
 546         }
 547
 548         ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG4, 0, 3, 0, t->oe_on,
 549                                    GPMC_CD_FCLK, "oe_on");
 550         ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG4, 8, 12, 0, t->oe_off,
 551                                    GPMC_CD_FCLK, "oe_off");
 552         if (gpmc_capability & GPMC_HAS_MUX_AAD) {
 553                 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG4, 4, 6, 0,
 554                                            t->oe_aad_mux_on, GPMC_CD_FCLK,
 555                                            "oe_aad_mux_on");
 556                 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG4, 13, 15, 0,
 557                                            t->oe_aad_mux_off, GPMC_CD_FCLK,
 558                                            "oe_aad_mux_off");
 559         }
 560         ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG4, 16, 19, 0, t->we_on,
 561                                    GPMC_CD_FCLK, "we_on");
 562         ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG4, 24, 28, 0, t->we_off,
 563                                    GPMC_CD_FCLK, "we_off");
 564         if (ret)
 565                 return -ENXIO;
 566
 567         ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG5, 0, 4, 0, t->rd_cycle,
 568                                    GPMC_CD_FCLK, "rd_cycle");
 569         ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG5, 8, 12, 0, t->wr_cycle,
 570                                    GPMC_CD_FCLK, "wr_cycle");
 571         ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG5, 16, 20, 0, t->access,
 572                                    GPMC_CD_FCLK, "access");
 573         ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG5, 24, 27, 0,
 574                                    t->page_burst_access, GPMC_CD_FCLK,
 575                                    "page_burst_access");
 576         if (ret)
 577                 return -ENXIO;
 578
 579         ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG6, 0, 3, 0,
 580                                    t->bus_turnaround, GPMC_CD_FCLK,
 581                                    "bus_turnaround");
 582         ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG6, 8, 11, 0,
 583                                    t->cycle2cycle_delay, GPMC_CD_FCLK,
 584                                    "cycle2cycle_delay");
 585         if (ret)
 586                 return -ENXIO;
 587
 588         if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS) {
 589                 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG6, 16, 19, 0,
 590                                            t->wr_data_mux_bus, GPMC_CD_FCLK,
 591                                            "wr_data_mux_bus");
 592                 if (ret)
 593                         return -ENXIO;
 594         }
 595         if (gpmc_capability & GPMC_HAS_WR_ACCESS) {
 596                 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG6, 24, 28, 0,
 597                                            t->wr_access, GPMC_CD_FCLK,
 598                                            "wr_access");
 599                 if (ret)
 600                         return -ENXIO;
 601         }
 602
 603         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
 604         l &= ~0x03;
 605         l |= (div - 1);
 606         gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l);
 607
 608         ret = 0;
 609         ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG1, 18, 19,
 610                                    GPMC_CONFIG1_WAITMONITORINGTIME_MAX,
 611                                    t->wait_monitoring, GPMC_CD_CLK,
 612                                    "wait_monitoring");
 613         ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG1, 25, 26,
 614                                    GPMC_CONFIG1_CLKACTIVATIONTIME_MAX,
 615                                    t->clk_activation, GPMC_CD_FCLK,
 616                                    "clk_activation");
 617         if (ret)
 618                 return -ENXIO;
 619
 620         if (IS_ENABLED(CONFIG_TI_GPMC_DEBUG)) {
 621                 printf("GPMC CS%d CLK period is %lu ns (div %d)\n",
 622                        cs, (div * gpmc_get_fclk_period()) / 1000, div);
 623         }
 624
 625         gpmc_cs_bool_timings(cs, &t->bool_timings);
 626         gpmc_cs_show_timings(cs, "after gpmc_set_timings");
 627
 628         return 0;
 629 }
 630
 631 static int gpmc_cs_set_memconf(int cs, resource_size_t base, u32 size)
 632 {
 633         u32 l;
 634         u32 mask;
 635
 636         /*
 637          * Ensure that base address is aligned on a
 638          * boundary equal to or greater than size.
 639          */
 640         if (base & (size - 1))
 641                 return -EINVAL;
 642
 643         base >>= GPMC_CHUNK_SHIFT;
 644         mask = (1 << GPMC_SECTION_SHIFT) - size;
 645         mask >>= GPMC_CHUNK_SHIFT;
 646         mask <<= GPMC_CONFIG7_MASKADDRESS_OFFSET;
 647
 648         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
 649         l &= ~GPMC_CONFIG7_MASK;
 650         l |= base & GPMC_CONFIG7_BASEADDRESS_MASK;
 651         l |= mask & GPMC_CONFIG7_MASKADDRESS_MASK;
 652         l |= GPMC_CONFIG7_CSVALID;
 653         gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
 654
 655         return 0;
 656 }
 657
 658 static void gpmc_cs_enable_mem(int cs)
 659 {
 660         u32 l;
 661
 662         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
 663         l |= GPMC_CONFIG7_CSVALID;
 664         gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
 665 }
 666
 667 static void gpmc_cs_disable_mem(int cs)
 668 {
 669         u32 l;
 670
 671         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
 672         l &= ~GPMC_CONFIG7_CSVALID;
 673         gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
 674 }
 675
 676 static void gpmc_cs_set_reserved(int cs, int reserved)
 677 {
 678         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 679
 680         gpmc->flags |= GPMC_CS_RESERVED;
 681 }
 682
 683 static bool gpmc_cs_reserved(int cs)
 684 {
 685         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 686
 687         return gpmc->flags & GPMC_CS_RESERVED;
 688 }
 689
 690 static unsigned long gpmc_mem_align(unsigned long size)
 691 {
 692         int order;
 693
 694         size = (size - 1) >> (GPMC_CHUNK_SHIFT - 1);
 695         order = GPMC_CHUNK_SHIFT - 1;
 696         do {
 697                 size >>= 1;
 698                 order++;
 699         } while (size);
 700         size = 1 << order;
 701         return size;
 702 }
 703
 704 static int gpmc_cs_request(ofnode node, int cs, struct resource *res)
 705 {
 706         int r = -1;
 707         u32 size;
 708         resource_size_t addr_base = res->start;
 709
 710         if (cs >= gpmc_cs_num) {
 711                 pr_err("%s: requested chip-select is disabled\n", __func__);
 712                 return -ENODEV;
 713         }
 714
 715         size = gpmc_mem_align(resource_size(res));
 716         if (size > (1 << GPMC_SECTION_SHIFT))
 717                 return -ENOMEM;
 718
 719         if (gpmc_cs_reserved(cs)) {
 720                 r = -EBUSY;
 721                 goto out;
 722         }
 723
 724         if (addr_base & (SZ_16M - 1)) {
 725                 pr_err("CS region should be aligned to 16M boundary\n");
 726                 goto out;
 727         }
 728
 729         /* Disable CS while changing base address and size mask */
 730         gpmc_cs_disable_mem(cs);
 731
 732         r = gpmc_cs_set_memconf(cs, addr_base, size);
 733         if (r < 0)
 734                 goto out;
 735
 736         /* Enable CS */
 737         gpmc_cs_enable_mem(cs);
 738         gpmc_cs_set_reserved(cs, 1);
 739 out:
 740         return r;
 741 }
 742
 743 static void gpmc_cs_free(int cs)
 744 {
 745         if (cs >= gpmc_cs_num || cs < 0 || !gpmc_cs_reserved(cs)) {
 746                 pr_warn("Trying to free non-reserved GPMC CS%d\n", cs);
 747                 return;
 748         }
 749
 750         gpmc_cs_disable_mem(cs);
 751         gpmc_cs_set_reserved(cs, 0);
 752 }
 753
 754 /**
 755  * gpmc_configure - write request to configure gpmc
 756  * @cmd: command type
 757  * @wval: value to write
 758  * @return status of the operation
 759  */
 760 static int gpmc_configure(int cmd, int wval)
 761 {
 762         u32 regval;
 763
 764         switch (cmd) {
 765         case GPMC_CONFIG_WP:
 766                 regval = gpmc_read_reg(GPMC_CONFIG);
 767                 if (wval)
 768                         regval &= ~GPMC_CONFIG_WRITEPROTECT; /* WP is ON */
 769                 else
 770                         regval |= GPMC_CONFIG_WRITEPROTECT;  /* WP is OFF */
 771                 gpmc_write_reg(GPMC_CONFIG, regval);
 772                 break;
 773
 774         default:
 775                 pr_err("%s: command not supported\n", __func__);
 776                 return -EINVAL;
 777         }
 778
 779         return 0;
 780 }
 781
 782 /**
 783  * gpmc_cs_program_settings - programs non-timing related settings
 784  * @cs:         GPMC chip-select to program
 785  * @p:          pointer to GPMC settings structure
 786  *
 787  * Programs non-timing related settings for a GPMC chip-select, such as
 788  * bus-width, burst configuration, etc. Function should be called once
 789  * for each chip-select that is being used and must be called before
 790  * calling gpmc_cs_set_timings() as timing parameters in the CONFIG1
 791  * register will be initialised to zero by this function. Returns 0 on
 792  * success and appropriate negative error code on failure.
 793  */
 794 static int gpmc_cs_program_settings(int cs, struct gpmc_settings *p)
 795 {
 796         u32 config1;
 797
 798         if (!p->device_width || p->device_width > GPMC_DEVWIDTH_16BIT) {
 799                 pr_err("%s: invalid width %d!", __func__, p->device_width);
 800                 return -EINVAL;
 801         }
 802
 803         /* Address-data multiplexing not supported for NAND devices */
 804         if (p->device_nand && p->mux_add_data) {
 805                 pr_err("%s: invalid configuration!\n", __func__);
 806                 return -EINVAL;
 807         }
 808
 809         if (p->mux_add_data > GPMC_MUX_AD ||
 810             (p->mux_add_data == GPMC_MUX_AAD &&
 811              !(gpmc_capability & GPMC_HAS_MUX_AAD))) {
 812                 pr_err("%s: invalid multiplex configuration!\n", __func__);
 813                 return -EINVAL;
 814         }
 815
 816         /* Page/burst mode supports lengths of 4, 8 and 16 bytes */
 817         if (p->burst_read || p->burst_write) {
 818                 switch (p->burst_len) {
 819                 case GPMC_BURST_4:
 820                 case GPMC_BURST_8:
 821                 case GPMC_BURST_16:
 822                         break;
 823                 default:
 824                         pr_err("%s: invalid page/burst-length (%d)\n",
 825                                __func__, p->burst_len);
 826                         return -EINVAL;
 827                 }
 828         }
 829
 830         if (p->wait_pin > gpmc_nr_waitpins) {
 831                 pr_err("%s: invalid wait-pin (%d)\n", __func__, p->wait_pin);
 832                 return -EINVAL;
 833         }
 834
 835         config1 = GPMC_CONFIG1_DEVICESIZE((p->device_width - 1));
 836
 837         if (p->sync_read)
 838                 config1 |= GPMC_CONFIG1_READTYPE_SYNC;
 839         if (p->sync_write)
 840                 config1 |= GPMC_CONFIG1_WRITETYPE_SYNC;
 841         if (p->wait_on_read)
 842                 config1 |= GPMC_CONFIG1_WAIT_READ_MON;
 843         if (p->wait_on_write)
 844                 config1 |= GPMC_CONFIG1_WAIT_WRITE_MON;
 845         if (p->wait_on_read || p->wait_on_write)
 846                 config1 |= GPMC_CONFIG1_WAIT_PIN_SEL(p->wait_pin);
 847         if (p->device_nand)
 848                 config1 |= GPMC_CONFIG1_DEVICETYPE(GPMC_DEVICETYPE_NAND);
 849         if (p->mux_add_data)
 850                 config1 |= GPMC_CONFIG1_MUXTYPE(p->mux_add_data);
 851         if (p->burst_read)
 852                 config1 |= GPMC_CONFIG1_READMULTIPLE_SUPP;
 853         if (p->burst_write)
 854                 config1 |= GPMC_CONFIG1_WRITEMULTIPLE_SUPP;
 855         if (p->burst_read || p->burst_write) {
 856                 config1 |= GPMC_CONFIG1_PAGE_LEN(p->burst_len >> 3);
 857                 config1 |= p->burst_wrap ? GPMC_CONFIG1_WRAPBURST_SUPP : 0;
 858         }
 859
 860         gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, config1);
 861
 862         return 0;
 863 }
 864
 865 static void gpmc_cs_set_name(int cs, const char *name)
 866 {
 867         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 868
 869         gpmc->name = name;
 870 }
 871
 872 static const char *gpmc_cs_get_name(int cs)
 873 {
 874         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 875
 876         return gpmc->name;
 877 }
 878
 879 /**
 880  * gpmc_read_settings_dt - read gpmc settings from device-tree
 881  * @np:         pointer to device-tree node for a gpmc child device
 882  * @p:          pointer to gpmc settings structure
 883  *
 884  * Reads the GPMC settings for a GPMC child device from device-tree and
 885  * stores them in the GPMC settings structure passed. The GPMC settings
 886  * structure is initialised to zero by this function and so any
 887  * previously stored settings will be cleared.
 888  */
 889 static void gpmc_read_settings_dt(ofnode np, struct gpmc_settings *p)
 890 {
 891         memset(p, 0, sizeof(struct gpmc_settings));
 892
 893         p->sync_read = ofnode_read_bool(np, "gpmc,sync-read");
 894         p->sync_write = ofnode_read_bool(np, "gpmc,sync-write");
 895         ofnode_read_u32(np, "gpmc,device-width", &p->device_width);
 896         ofnode_read_u32(np, "gpmc,mux-add-data", &p->mux_add_data);
 897
 898         if (!ofnode_read_u32(np, "gpmc,burst-length", &p->burst_len)) {
 899                 p->burst_wrap = ofnode_read_bool(np, "gpmc,burst-wrap");
 900                 p->burst_read = ofnode_read_bool(np, "gpmc,burst-read");
 901                 p->burst_write = ofnode_read_bool(np, "gpmc,burst-write");
 902                 if (!p->burst_read && !p->burst_write)
 903                         pr_warn("%s: page/burst-length set but not used!\n",
 904                                 __func__);
 905         }
 906
 907         if (!ofnode_read_u32(np, "gpmc,wait-pin", &p->wait_pin)) {
 908                 p->wait_on_read = ofnode_read_bool(np,
 909                                                    "gpmc,wait-on-read");
 910                 p->wait_on_write = ofnode_read_bool(np,
 911                                                     "gpmc,wait-on-write");
 912                 if (!p->wait_on_read && !p->wait_on_write)
 913                         pr_debug("%s: rd/wr wait monitoring not enabled!\n",
 914                                  __func__);
 915         }
 916 }
 917
 918 static void gpmc_read_timings_dt(ofnode np,
 919                                  struct gpmc_timings *gpmc_t)
 920 {
 921         struct gpmc_bool_timings *p;
 922
 923         if (!gpmc_t)
 924                 return;
 925
 926         memset(gpmc_t, 0, sizeof(*gpmc_t));
 927
 928         /* minimum clock period for syncronous mode */
 929         ofnode_read_u32(np, "gpmc,sync-clk-ps", &gpmc_t->sync_clk);
 930
 931         /* chip select timtings */
 932         ofnode_read_u32(np, "gpmc,cs-on-ns", &gpmc_t->cs_on);
 933         ofnode_read_u32(np, "gpmc,cs-rd-off-ns", &gpmc_t->cs_rd_off);
 934         ofnode_read_u32(np, "gpmc,cs-wr-off-ns", &gpmc_t->cs_wr_off);
 935
 936         /* ADV signal timings */
 937         ofnode_read_u32(np, "gpmc,adv-on-ns", &gpmc_t->adv_on);
 938         ofnode_read_u32(np, "gpmc,adv-rd-off-ns", &gpmc_t->adv_rd_off);
 939         ofnode_read_u32(np, "gpmc,adv-wr-off-ns", &gpmc_t->adv_wr_off);
 940         ofnode_read_u32(np, "gpmc,adv-aad-mux-on-ns",
 941                         &gpmc_t->adv_aad_mux_on);
 942         ofnode_read_u32(np, "gpmc,adv-aad-mux-rd-off-ns",
 943                         &gpmc_t->adv_aad_mux_rd_off);
 944         ofnode_read_u32(np, "gpmc,adv-aad-mux-wr-off-ns",
 945                         &gpmc_t->adv_aad_mux_wr_off);
 946
 947         /* WE signal timings */
 948         ofnode_read_u32(np, "gpmc,we-on-ns", &gpmc_t->we_on);
 949         ofnode_read_u32(np, "gpmc,we-off-ns", &gpmc_t->we_off);
 950
 951         /* OE signal timings */
 952         ofnode_read_u32(np, "gpmc,oe-on-ns", &gpmc_t->oe_on);
 953         ofnode_read_u32(np, "gpmc,oe-off-ns", &gpmc_t->oe_off);
 954         ofnode_read_u32(np, "gpmc,oe-aad-mux-on-ns",
 955                         &gpmc_t->oe_aad_mux_on);
 956         ofnode_read_u32(np, "gpmc,oe-aad-mux-off-ns",
 957                         &gpmc_t->oe_aad_mux_off);
 958
 959         /* access and cycle timings */
 960         ofnode_read_u32(np, "gpmc,page-burst-access-ns",
 961                         &gpmc_t->page_burst_access);
 962         ofnode_read_u32(np, "gpmc,access-ns", &gpmc_t->access);
 963         ofnode_read_u32(np, "gpmc,rd-cycle-ns", &gpmc_t->rd_cycle);
 964         ofnode_read_u32(np, "gpmc,wr-cycle-ns", &gpmc_t->wr_cycle);
 965         ofnode_read_u32(np, "gpmc,bus-turnaround-ns",
 966                         &gpmc_t->bus_turnaround);
 967         ofnode_read_u32(np, "gpmc,cycle2cycle-delay-ns",
 968                         &gpmc_t->cycle2cycle_delay);
 969         ofnode_read_u32(np, "gpmc,wait-monitoring-ns",
 970                         &gpmc_t->wait_monitoring);
 971         ofnode_read_u32(np, "gpmc,clk-activation-ns",
 972                         &gpmc_t->clk_activation);
 973
 974         /* only applicable to OMAP3+ */
 975         ofnode_read_u32(np, "gpmc,wr-access-ns", &gpmc_t->wr_access);
 976         ofnode_read_u32(np, "gpmc,wr-data-mux-bus-ns",
 977                         &gpmc_t->wr_data_mux_bus);
 978
 979         /* bool timing parameters */
 980         p = &gpmc_t->bool_timings;
 981
 982         p->cycle2cyclediffcsen =
 983                 ofnode_read_bool(np, "gpmc,cycle2cycle-diffcsen");
 984         p->cycle2cyclesamecsen =
 985                 ofnode_read_bool(np, "gpmc,cycle2cycle-samecsen");
 986         p->we_extra_delay = ofnode_read_bool(np, "gpmc,we-extra-delay");
 987         p->oe_extra_delay = ofnode_read_bool(np, "gpmc,oe-extra-delay");
 988         p->adv_extra_delay = ofnode_read_bool(np, "gpmc,adv-extra-delay");
 989         p->cs_extra_delay = ofnode_read_bool(np, "gpmc,cs-extra-delay");
 990         p->time_para_granularity =
 991                 ofnode_read_bool(np, "gpmc,time-para-granularity");
 992 }
 993
 994 /**
 995  * gpmc_probe_generic_child - configures the gpmc for a child device
 996  * @dev:        pointer to gpmc platform device
 997  * @child:      pointer to device-tree node for child device
 998  *
 999  * Allocates and configures a GPMC chip-select for a child device.
1000  * Returns 0 on success and appropriate negative error code on failure.
1001  */
1002 static int gpmc_probe_generic_child(struct udevice *dev,
1003                                     ofnode child)
1004 {
1005         struct gpmc_settings gpmc_s;
1006         struct gpmc_timings gpmc_t;
1007         struct resource res;
1008         const char *name;
1009         int ret;
1010         u32 val, cs;
1011
1012         if (ofnode_read_u32(child, "reg", &cs) < 0) {
1013                 dev_err(dev, "can't get reg property of child %s\n",
1014                         ofnode_get_name(child));
1015                 return -ENODEV;
1016         }
1017
1018         if (ofnode_read_resource(child, 0, &res) < 0) {
1019                 dev_err(dev, "%s has malformed 'reg' property\n",
1020                         ofnode_get_name(child));
1021                 return -ENODEV;
1022         }
1023
1024         /*
1025          * Check if we have multiple instances of the same device
1026          * on a single chip select. If so, use the already initialized
1027          * timings.
1028          */
1029         name = gpmc_cs_get_name(cs);
1030         if (name && !strcmp(name, ofnode_get_name(child)))
1031                 goto no_timings;
1032
1033         ret = gpmc_cs_request(child, cs, &res);
1034         if (ret < 0) {
1035                 dev_err(dev, "cannot request GPMC CS %d\n", cs);
1036                 return ret;
1037         }
1038         gpmc_cs_set_name(cs, ofnode_get_name(child));
1039
1040         gpmc_read_settings_dt(child, &gpmc_s);
1041         gpmc_read_timings_dt(child, &gpmc_t);
1042
1043         /*
1044          * For some GPMC devices we still need to rely on the bootloader
1045          * timings because the devices can be connected via FPGA.
1046          * REVISIT: Add timing support from slls644g.pdf.
1047          */
1048         if (!gpmc_t.cs_rd_off) {
1049                 pr_warn("enable GPMC debug to configure .dts timings for CS%i\n",
1050                         cs);
1051                 gpmc_cs_show_timings(cs,
1052                                      "please add GPMC bootloader timings to .dts");
1053                 goto no_timings;
1054         }
1055
1056         /* CS must be disabled while making changes to gpmc configuration */
1057         gpmc_cs_disable_mem(cs);
1058
1059         if (!ofnode_read_u32(child, "nand-bus-width", &val)) {
1060                 /* NAND specific setup */
1061                 ofnode_read_u32(child, "nand-bus-width", &val);
1062                 switch (val) {
1063                 case 8:
1064                         gpmc_s.device_width = GPMC_DEVWIDTH_8BIT;
1065                         break;
1066                 case 16:
1067                         gpmc_s.device_width = GPMC_DEVWIDTH_16BIT;
1068                         break;
1069                 default:
1070                         dev_err(dev, "%s: invalid 'nand-bus-width'\n",
1071                                 ofnode_get_name(child));
1072                         ret = -EINVAL;
1073                         goto err;
1074                 }
1075
1076                 /* disable write protect */
1077                 gpmc_configure(GPMC_CONFIG_WP, 0);
1078                 gpmc_s.device_nand = true;
1079         } else {
1080                 ret = ofnode_read_u32(child, "bank-width",
1081                                       &gpmc_s.device_width);
1082                 if (ret < 0 && !gpmc_s.device_width) {
1083                         dev_err(dev,
1084                                 "%s has no 'gpmc,device-width' property\n",
1085                                 ofnode_get_name(child));
1086                         goto err;
1087                 }
1088         }
1089
1090         gpmc_cs_show_timings(cs, "before gpmc_cs_program_settings");
1091
1092         ret = gpmc_cs_program_settings(cs, &gpmc_s);
1093         if (ret < 0)
1094                 goto err;
1095
1096         ret = gpmc_cs_set_timings(cs, &gpmc_t, &gpmc_s);
1097         if (ret) {
1098                 dev_err(dev, "failed to set gpmc timings for: %s\n",
1099                         ofnode_get_name(child));
1100                 goto err;
1101         }
1102
1103         /* Clear limited address i.e. enable A26-A11 */
1104         val = gpmc_read_reg(GPMC_CONFIG);
1105         val &= ~GPMC_CONFIG_LIMITEDADDRESS;
1106         gpmc_write_reg(GPMC_CONFIG, val);
1107
1108         /* Enable CS region */
1109         gpmc_cs_enable_mem(cs);
1110
1111 no_timings:
1112
1113         return 0;
1114
1115 err:
1116         gpmc_cs_free(cs);
1117
1118         return ret;
1119 }
1120
1121 static void gpmc_probe_dt_children(struct udevice *dev)
1122 {
1123         int ret;
1124         ofnode child;
1125
1126         ofnode_for_each_subnode(child, dev_ofnode(dev)) {
1127                 ret = gpmc_probe_generic_child(dev, child);
1128                 if (ret) {
1129                         dev_err(dev, "Cannot parse child %s:%d",
1130                                 ofnode_get_name(child), ret);
1131                 }
1132         }
1133 }
1134
1135 static int gpmc_parse_dt(struct udevice *dev, struct ti_gpmc *gpmc)
1136 {
1137         int ret;
1138         u32 val;
1139
1140         ret = ofnode_read_u32(dev_ofnode(dev), "gpmc,num-cs",
1141                               &val);
1142         if (ret < 0) {
1143                 pr_err("%s: number of chip-selects not defined\n", __func__);
1144                 return ret;
1145         } else if (val < 1) {
1146                 pr_err("%s: all chip-selects are disabled\n", __func__);
1147                 return -EINVAL;
1148         } else if (val > GPMC_CS_NUM) {
1149                 pr_err("%s: number of supported chip-selects cannot be > %d\n",
1150                        __func__, GPMC_CS_NUM);
1151                 return -EINVAL;
1152         }
1153
1154         gpmc->cs_num = val;
1155         gpmc_cs_num = val;
1156
1157         ret = ofnode_read_u32(dev_ofnode(dev), "gpmc,num-waitpins",
1158                               &gpmc->nr_waitpins);
1159         if (ret < 0) {
1160                 pr_err("%s: number of wait pins not found!\n", __func__);
1161                 return ret;
1162         }
1163
1164         gpmc_nr_waitpins = gpmc->nr_waitpins;
1165
1166         return 0;
1167 }
1168
1169 static int gpmc_probe(struct udevice *dev)
1170 {
1171         struct ti_gpmc *priv = dev_get_priv(dev);
1172         int ret;
1173         struct resource res;
1174
1175         ret = dev_read_resource_byname(dev, "cfg", &res);
1176         if (ret) {
1177                 /* Legacy DT */
1178                 dev_read_resource(dev, 0, &res);
1179                 priv->base = devm_ioremap(dev, res.start, resource_size(&res));
1180
1181                 priv->data.start = GPMC_MEM_START;
1182                 priv->data.end = GPMC_MEM_END;
1183         } else {
1184                 priv->base = devm_ioremap(dev, res.start, resource_size(&res));
1185                 ret = dev_read_resource_byname(dev, "data", &res);
1186                 if (ret)
1187                         return -ENOENT;
1188
1189                 priv->data = res;
1190         }
1191
1192         if (!priv->base)
1193                 return -ENOMEM;
1194
1195         gpmc_cfg = (struct gpmc *)priv->base;
1196         gpmc_base = priv->base;
1197
1198         /*
1199          * Disable all IRQs as some bootroms might leave them enabled
1200          * and that will cause a lock-up later
1201          */
1202         gpmc_write_reg(GPMC_IRQENABLE, 0);
1203
1204         priv->l3_clk = devm_clk_get(dev, "fck");
1205         if (IS_ERR(priv->l3_clk))
1206                 return PTR_ERR(priv->l3_clk);
1207
1208         if (!clk_get_rate(priv->l3_clk))
1209                 return -EINVAL;
1210
1211         gpmc_l3_clk = priv->l3_clk;
1212
1213         ret = gpmc_parse_dt(dev, priv);
1214         if (ret)
1215                 return ret;
1216
1217         priv->capability_flags = dev->driver->of_match->data;
1218         gpmc_capability = priv->capability_flags;
1219
1220         gpmc_probe_dt_children(dev);
1221
1222         return 0;
1223 }
1224
1225 #define GPMC_DATA_REV2_4 0
1226 #define GPMC_DATA_REV5 (GPMC_HAS_WR_ACCESS | GPMC_HAS_WR_DATA_MUX_BUS)
1227 #define GPMC_DATA_REV6 (GPMC_HAS_WR_ACCESS | GPMC_HAS_WR_DATA_MUX_BUS | GPMC_HAS_MUX_AAD)
1228
1229 static const struct udevice_id gpmc_dt_ids[] = {
1230         { .compatible = "ti,am64-gpmc", .data = GPMC_DATA_REV6, },
1231         { .compatible = "ti,am3352-gpmc", .data = GPMC_DATA_REV5, },
1232         { .compatible = "ti,omap2420-gpmc", .data = GPMC_DATA_REV2_4, },
1233         { .compatible = "ti,omap2430-gpmc", .data = GPMC_DATA_REV2_4, },
1234         { .compatible = "ti,omap3430-gpmc", .data = GPMC_DATA_REV5, },
1235         { .compatible = "ti,omap4430-gpmc", .data = GPMC_DATA_REV6, },
1236         { } /* sentinel */
1237 };
1238
1239 U_BOOT_DRIVER(ti_gpmc) = {
1240         .name   = "ti-gpmc",
1241         .id     = UCLASS_MEMORY,
1242         .of_match = gpmc_dt_ids,
1243         .probe  = gpmc_probe,
1244         .flags  = DM_FLAG_ALLOC_PRIV_DMA,
1245 };