include/configs/ls1046ardb.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2016 Freescale Semiconductor
   4  * Copyright 2019 NXP
   5  */
   6
   7 #ifndef __LS1046ARDB_H__
   8 #define __LS1046ARDB_H__
   9
  10 #include "ls1046a_common.h"
  11
  12 #define CONFIG_SYS_CLK_FREQ             100000000
  13
  14 #define CONFIG_LAYERSCAPE_NS_ACCESS
  15
  16 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  17 /* Physical Memory Map */
  18 #define CONFIG_CHIP_SELECTS_PER_CTRL    4
  19
  20 #define SPD_EEPROM_ADDRESS              0x51
  21 #define CONFIG_SYS_SPD_BUS_NUM          0
  22
  23 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  24
  25 #if defined(CONFIG_QSPI_BOOT)
  26 #define CONFIG_SYS_UBOOT_BASE           0x40100000
  27 #define CONFIG_SYS_SPL_ARGS_ADDR        0x90000000
  28 #endif
  29
  30 #ifndef SPL_NO_IFC
  31 /* IFC */
  32 #define CONFIG_FSL_IFC
  33 /*
  34  * NAND Flash Definitions
  35  */
  36 #endif
  37
  38 #define CONFIG_SYS_NAND_BASE            0x7e800000
  39 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
  40
  41 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
  42 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  43                                 | CSPR_PORT_SIZE_8      \
  44                                 | CSPR_MSEL_NAND        \
  45                                 | CSPR_V)
  46 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64 * 1024)
  47 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
  48                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
  49                                 | CSOR_NAND_ECC_MODE_8  /* 8-bit ECC */ \
  50                                 | CSOR_NAND_RAL_3       /* RAL = 3 Bytes */ \
  51                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
  52                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
  53                                 | CSOR_NAND_PB(64))     /* 64 Pages Per Block */
  54
  55 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x7) | \
  56                                         FTIM0_NAND_TWP(0x18)   | \
  57                                         FTIM0_NAND_TWCHT(0x7) | \
  58                                         FTIM0_NAND_TWH(0xa))
  59 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
  60                                         FTIM1_NAND_TWBE(0x39)  | \
  61                                         FTIM1_NAND_TRR(0xe)   | \
  62                                         FTIM1_NAND_TRP(0x18))
  63 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0xf) | \
  64                                         FTIM2_NAND_TREH(0xa) | \
  65                                         FTIM2_NAND_TWHRE(0x1e))
  66 #define CONFIG_SYS_NAND_FTIM3           0x0
  67
  68 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
  69 #define CONFIG_SYS_MAX_NAND_DEVICE      1
  70 #define CONFIG_MTD_NAND_VERIFY_WRITE
  71
  72 /*
  73  * CPLD
  74  */
  75 #define CONFIG_SYS_CPLD_BASE            0x7fb00000
  76 #define CPLD_BASE_PHYS                  CONFIG_SYS_CPLD_BASE
  77
  78 #define CONFIG_SYS_CPLD_CSPR_EXT        (0x0)
  79 #define CONFIG_SYS_CPLD_CSPR            (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
  80                                         CSPR_PORT_SIZE_8 | \
  81                                         CSPR_MSEL_GPCM | \
  82                                         CSPR_V)
  83 #define CONFIG_SYS_CPLD_AMASK           IFC_AMASK(64 * 1024)
  84 #define CONFIG_SYS_CPLD_CSOR            CSOR_NOR_ADM_SHIFT(16)
  85
  86 /* CPLD Timing parameters for IFC GPCM */
  87 #define CONFIG_SYS_CPLD_FTIM0           (FTIM0_GPCM_TACSE(0x0e) | \
  88                                         FTIM0_GPCM_TEADC(0x0e) | \
  89                                         FTIM0_GPCM_TEAHC(0x0e))
  90 #define CONFIG_SYS_CPLD_FTIM1           (FTIM1_GPCM_TACO(0xff) | \
  91                                         FTIM1_GPCM_TRAD(0x3f))
  92 #define CONFIG_SYS_CPLD_FTIM2           (FTIM2_GPCM_TCS(0xf) | \
  93                                         FTIM2_GPCM_TCH(0xf) | \
  94                                         FTIM2_GPCM_TWP(0x3E))
  95 #define CONFIG_SYS_CPLD_FTIM3           0x0
  96
  97 /* IFC Timing Params */
  98 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
  99 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 100 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 101 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 102 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 103 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 104 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 105 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 106
 107 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_CPLD_CSPR_EXT
 108 #define CONFIG_SYS_CSPR2                CONFIG_SYS_CPLD_CSPR
 109 #define CONFIG_SYS_AMASK2               CONFIG_SYS_CPLD_AMASK
 110 #define CONFIG_SYS_CSOR2                CONFIG_SYS_CPLD_CSOR
 111 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_CPLD_FTIM0
 112 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_CPLD_FTIM1
 113 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_CPLD_FTIM2
 114 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_CPLD_FTIM3
 115
 116 /* EEPROM */
 117 #define CONFIG_SYS_I2C_EEPROM_NXID
 118 #define CONFIG_SYS_EEPROM_BUS_NUM               0
 119 #define I2C_RETIMER_ADDR                        0x18
 120
 121 /* PMIC */
 122
 123 /*
 124  * Environment
 125  */
 126 #define CONFIG_SYS_FSL_QSPI_BASE        0x40000000
 127
 128 #define AQR105_IRQ_MASK                 0x80000000
 129 /* FMan */
 130 #ifndef SPL_NO_FMAN
 131 #ifdef CONFIG_SYS_DPAA_FMAN
 132 #define RGMII_PHY1_ADDR                 0x1
 133 #define RGMII_PHY2_ADDR                 0x2
 134
 135 #define SGMII_PHY1_ADDR                 0x3
 136 #define SGMII_PHY2_ADDR                 0x4
 137
 138 #define FM1_10GEC1_PHY_ADDR             0x0
 139
 140 #define FDT_SEQ_MACADDR_FROM_ENV
 141
 142 #define CONFIG_ETHPRIME                 "FM1@DTSEC3"
 143 #endif
 144
 145 #endif
 146
 147 #ifndef SPL_NO_MISC
 148 #ifdef CONFIG_TFABOOT
 149 #define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; "   \
 150                            "env exists secureboot && esbc_halt;;"
 151 #define SD_BOOTCOMMAND "run distro_bootcmd;run sd_bootcmd; "    \
 152                            "env exists secureboot && esbc_halt;"
 153 #endif
 154 #endif
 155
 156 #include <asm/fsl_secure_boot.h>
 157
 158 #endif /* __LS1046ARDB_H__ */