board/xilinx/zynqmp/zynqmp.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2014 - 2015 Xilinx, Inc.
   4  * Michal Simek <[email protected]>
   5  */
   6
   7 #include <common.h>
   8 #include <sata.h>
   9 #include <ahci.h>
  10 #include <scsi.h>
  11 #include <malloc.h>
  12 #include <wdt.h>
  13 #include <asm/arch/clk.h>
  14 #include <asm/arch/hardware.h>
  15 #include <asm/arch/sys_proto.h>
  16 #include <asm/arch/psu_init_gpl.h>
  17 #include <asm/io.h>
  18 #include <dm/device.h>
  19 #include <dm/uclass.h>
  20 #include <usb.h>
  21 #include <dwc3-uboot.h>
  22 #include <zynqmppl.h>
  23 #include <g_dnl.h>
  24
  25 DECLARE_GLOBAL_DATA_PTR;
  26
  27 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT)
  28 static struct udevice *watchdog_dev __attribute__((section(".data"))) = NULL;
  29 #endif
  30
  31 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
  32     !defined(CONFIG_SPL_BUILD)
  33 static xilinx_desc zynqmppl = XILINX_ZYNQMP_DESC;
  34
  35 static const struct {
  36         u32 id;
  37         u32 ver;
  38         char *name;
  39         bool evexists;
  40 } zynqmp_devices[] = {
  41         {
  42                 .id = 0x10,
  43                 .name = "3eg",
  44         },
  45         {
  46                 .id = 0x10,
  47                 .ver = 0x2c,
  48                 .name = "3cg",
  49         },
  50         {
  51                 .id = 0x11,
  52                 .name = "2eg",
  53         },
  54         {
  55                 .id = 0x11,
  56                 .ver = 0x2c,
  57                 .name = "2cg",
  58         },
  59         {
  60                 .id = 0x20,
  61                 .name = "5ev",
  62                 .evexists = 1,
  63         },
  64         {
  65                 .id = 0x20,
  66                 .ver = 0x100,
  67                 .name = "5eg",
  68                 .evexists = 1,
  69         },
  70         {
  71                 .id = 0x20,
  72                 .ver = 0x12c,
  73                 .name = "5cg",
  74                 .evexists = 1,
  75         },
  76         {
  77                 .id = 0x21,
  78                 .name = "4ev",
  79                 .evexists = 1,
  80         },
  81         {
  82                 .id = 0x21,
  83                 .ver = 0x100,
  84                 .name = "4eg",
  85                 .evexists = 1,
  86         },
  87         {
  88                 .id = 0x21,
  89                 .ver = 0x12c,
  90                 .name = "4cg",
  91                 .evexists = 1,
  92         },
  93         {
  94                 .id = 0x30,
  95                 .name = "7ev",
  96                 .evexists = 1,
  97         },
  98         {
  99                 .id = 0x30,
 100                 .ver = 0x100,
 101                 .name = "7eg",
 102                 .evexists = 1,
 103         },
 104         {
 105                 .id = 0x30,
 106                 .ver = 0x12c,
 107                 .name = "7cg",
 108                 .evexists = 1,
 109         },
 110         {
 111                 .id = 0x38,
 112                 .name = "9eg",
 113         },
 114         {
 115                 .id = 0x38,
 116                 .ver = 0x2c,
 117                 .name = "9cg",
 118         },
 119         {
 120                 .id = 0x39,
 121                 .name = "6eg",
 122         },
 123         {
 124                 .id = 0x39,
 125                 .ver = 0x2c,
 126                 .name = "6cg",
 127         },
 128         {
 129                 .id = 0x40,
 130                 .name = "11eg",
 131         },
 132         { /* For testing purpose only */
 133                 .id = 0x50,
 134                 .ver = 0x2c,
 135                 .name = "15cg",
 136         },
 137         {
 138                 .id = 0x50,
 139                 .name = "15eg",
 140         },
 141         {
 142                 .id = 0x58,
 143                 .name = "19eg",
 144         },
 145         {
 146                 .id = 0x59,
 147                 .name = "17eg",
 148         },
 149         {
 150                 .id = 0x61,
 151                 .name = "21dr",
 152         },
 153         {
 154                 .id = 0x63,
 155                 .name = "23dr",
 156         },
 157         {
 158                 .id = 0x65,
 159                 .name = "25dr",
 160         },
 161         {
 162                 .id = 0x64,
 163                 .name = "27dr",
 164         },
 165         {
 166                 .id = 0x60,
 167                 .name = "28dr",
 168         },
 169         {
 170                 .id = 0x62,
 171                 .name = "29dr",
 172         },
 173         {
 174                 .id = 0x66,
 175                 .name = "39dr",
 176         },
 177 };
 178 #endif
 179
 180 int chip_id(unsigned char id)
 181 {
 182         struct pt_regs regs;
 183         int val = -EINVAL;
 184
 185         if (current_el() != 3) {
 186                 regs.regs[0] = ZYNQMP_SIP_SVC_CSU_DMA_CHIPID;
 187                 regs.regs[1] = 0;
 188                 regs.regs[2] = 0;
 189                 regs.regs[3] = 0;
 190
 191                 smc_call(&regs);
 192
 193                 /*
 194                  * SMC returns:
 195                  * regs[0][31:0]  = status of the operation
 196                  * regs[0][63:32] = CSU.IDCODE register
 197                  * regs[1][31:0]  = CSU.version register
 198                  * regs[1][63:32] = CSU.IDCODE2 register
 199                  */
 200                 switch (id) {
 201                 case IDCODE:
 202                         regs.regs[0] = upper_32_bits(regs.regs[0]);
 203                         regs.regs[0] &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
 204                                         ZYNQMP_CSU_IDCODE_SVD_MASK;
 205                         regs.regs[0] >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
 206                         val = regs.regs[0];
 207                         break;
 208                 case VERSION:
 209                         regs.regs[1] = lower_32_bits(regs.regs[1]);
 210                         regs.regs[1] &= ZYNQMP_CSU_SILICON_VER_MASK;
 211                         val = regs.regs[1];
 212                         break;
 213                 case IDCODE2:
 214                         regs.regs[1] = lower_32_bits(regs.regs[1]);
 215                         regs.regs[1] >>= ZYNQMP_CSU_VERSION_EMPTY_SHIFT;
 216                         val = regs.regs[1];
 217                         break;
 218                 default:
 219                         printf("%s, Invalid Req:0x%x\n", __func__, id);
 220                 }
 221         } else {
 222                 switch (id) {
 223                 case IDCODE:
 224                         val = readl(ZYNQMP_CSU_IDCODE_ADDR);
 225                         val &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
 226                                ZYNQMP_CSU_IDCODE_SVD_MASK;
 227                         val >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
 228                         break;
 229                 case VERSION:
 230                         val = readl(ZYNQMP_CSU_VER_ADDR);
 231                         val &= ZYNQMP_CSU_SILICON_VER_MASK;
 232                         break;
 233                 default:
 234                         printf("%s, Invalid Req:0x%x\n", __func__, id);
 235                 }
 236         }
 237
 238         return val;
 239 }
 240
 241 #define ZYNQMP_VERSION_SIZE             9
 242 #define ZYNQMP_PL_STATUS_BIT            9
 243 #define ZYNQMP_IPDIS_VCU_BIT            8
 244 #define ZYNQMP_PL_STATUS_MASK           BIT(ZYNQMP_PL_STATUS_BIT)
 245 #define ZYNQMP_CSU_VERSION_MASK         ~(ZYNQMP_PL_STATUS_MASK)
 246 #define ZYNQMP_CSU_VCUDIS_VER_MASK      ZYNQMP_CSU_VERSION_MASK & \
 247                                         ~BIT(ZYNQMP_IPDIS_VCU_BIT)
 248 #define MAX_VARIANTS_EV                 3
 249
 250 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
 251         !defined(CONFIG_SPL_BUILD)
 252 static char *zynqmp_get_silicon_idcode_name(void)
 253 {
 254         u32 i, id, ver, j;
 255         char *buf;
 256         static char name[ZYNQMP_VERSION_SIZE];
 257
 258         id = chip_id(IDCODE);
 259         ver = chip_id(IDCODE2);
 260
 261         for (i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) {
 262                 if (zynqmp_devices[i].id == id) {
 263                         if (zynqmp_devices[i].evexists &&
 264                             !(ver & ZYNQMP_PL_STATUS_MASK))
 265                                 break;
 266                         if (zynqmp_devices[i].ver == (ver &
 267                             ZYNQMP_CSU_VERSION_MASK))
 268                                 break;
 269                 }
 270         }
 271
 272         if (i >= ARRAY_SIZE(zynqmp_devices))
 273                 return "unknown";
 274
 275         strncat(name, "zu", 2);
 276         if (!zynqmp_devices[i].evexists ||
 277             (ver & ZYNQMP_PL_STATUS_MASK)) {
 278                 strncat(name, zynqmp_devices[i].name,
 279                         ZYNQMP_VERSION_SIZE - 3);
 280                 return name;
 281         }
 282
 283         /*
 284          * Here we are means, PL not powered up and ev variant
 285          * exists. So, we need to ignore VCU disable bit(8) in
 286          * version and findout if its CG or EG/EV variant.
 287          */
 288         for (j = 0; j < MAX_VARIANTS_EV; j++, i++) {
 289                 if ((zynqmp_devices[i].ver & ~BIT(ZYNQMP_IPDIS_VCU_BIT)) ==
 290                     (ver & ZYNQMP_CSU_VCUDIS_VER_MASK)) {
 291                         strncat(name, zynqmp_devices[i].name,
 292                                 ZYNQMP_VERSION_SIZE - 3);
 293                         break;
 294                 }
 295         }
 296
 297         if (j >= MAX_VARIANTS_EV)
 298                 return "unknown";
 299
 300         if (strstr(name, "eg") || strstr(name, "ev")) {
 301                 buf = strstr(name, "e");
 302                 *buf = '\0';
 303         }
 304
 305         return name;
 306 }
 307 #endif
 308
 309 int board_early_init_f(void)
 310 {
 311         int ret = 0;
 312 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_CLK_ZYNQMP)
 313         u32 pm_api_version;
 314
 315         pm_api_version = zynqmp_pmufw_version();
 316         printf("PMUFW:\tv%d.%d\n",
 317                pm_api_version >> ZYNQMP_PM_VERSION_MAJOR_SHIFT,
 318                pm_api_version & ZYNQMP_PM_VERSION_MINOR_MASK);
 319
 320         if (pm_api_version < ZYNQMP_PM_VERSION)
 321                 panic("PMUFW version error. Expected: v%d.%d\n",
 322                       ZYNQMP_PM_VERSION_MAJOR, ZYNQMP_PM_VERSION_MINOR);
 323 #endif
 324
 325 #if defined(CONFIG_ZYNQMP_PSU_INIT_ENABLED)
 326         ret = psu_init();
 327 #endif
 328
 329         return ret;
 330 }
 331
 332 int board_init(void)
 333 {
 334         printf("EL Level:\tEL%d\n", current_el());
 335
 336 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
 337     !defined(CONFIG_SPL_BUILD) || (defined(CONFIG_SPL_FPGA_SUPPORT) && \
 338     defined(CONFIG_SPL_BUILD))
 339         if (current_el() != 3) {
 340                 zynqmppl.name = zynqmp_get_silicon_idcode_name();
 341                 printf("Chip ID:\t%s\n", zynqmppl.name);
 342                 fpga_init();
 343                 fpga_add(fpga_xilinx, &zynqmppl);
 344         }
 345 #endif
 346
 347 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT)
 348         if (uclass_get_device_by_seq(UCLASS_WDT, 0, &watchdog_dev)) {
 349                 debug("Watchdog: Not found by seq!\n");
 350                 if (uclass_get_device(UCLASS_WDT, 0, &watchdog_dev)) {
 351                         puts("Watchdog: Not found!\n");
 352                         return 0;
 353                 }
 354         }
 355
 356         wdt_start(watchdog_dev, 0, 0);
 357         puts("Watchdog: Started\n");
 358 #endif
 359
 360         return 0;
 361 }
 362
 363 #ifdef CONFIG_WATCHDOG
 364 /* Called by macro WATCHDOG_RESET */
 365 void watchdog_reset(void)
 366 {
 367 # if !defined(CONFIG_SPL_BUILD)
 368         static ulong next_reset;
 369         ulong now;
 370
 371         if (!watchdog_dev)
 372                 return;
 373
 374         now = timer_get_us();
 375
 376         /* Do not reset the watchdog too often */
 377         if (now > next_reset) {
 378                 wdt_reset(watchdog_dev);
 379                 next_reset = now + 1000;
 380         }
 381 # endif
 382 }
 383 #endif
 384
 385 int board_early_init_r(void)
 386 {
 387         u32 val;
 388
 389         if (current_el() != 3)
 390                 return 0;
 391
 392         val = readl(&crlapb_base->timestamp_ref_ctrl);
 393         val &= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
 394
 395         if (!val) {
 396                 val = readl(&crlapb_base->timestamp_ref_ctrl);
 397                 val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
 398                 writel(val, &crlapb_base->timestamp_ref_ctrl);
 399
 400                 /* Program freq register in System counter */
 401                 writel(zynqmp_get_system_timer_freq(),
 402                        &iou_scntr_secure->base_frequency_id_register);
 403                 /* And enable system counter */
 404                 writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
 405                        &iou_scntr_secure->counter_control_register);
 406         }
 407         return 0;
 408 }
 409
 410 unsigned long do_go_exec(ulong (*entry)(int, char * const []), int argc,
 411                          char * const argv[])
 412 {
 413         int ret = 0;
 414
 415         if (current_el() > 1) {
 416                 smp_kick_all_cpus();
 417                 dcache_disable();
 418                 armv8_switch_to_el1(0x0, 0, 0, 0, (unsigned long)entry,
 419                                     ES_TO_AARCH64);
 420         } else {
 421                 printf("FAIL: current EL is not above EL1\n");
 422                 ret = EINVAL;
 423         }
 424         return ret;
 425 }
 426
 427 #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
 428 int dram_init_banksize(void)
 429 {
 430         int ret;
 431
 432         ret = fdtdec_setup_memory_banksize();
 433         if (ret)
 434                 return ret;
 435
 436         mem_map_fill();
 437
 438         return 0;
 439 }
 440
 441 int dram_init(void)
 442 {
 443         if (fdtdec_setup_mem_size_base() != 0)
 444                 return -EINVAL;
 445
 446         return 0;
 447 }
 448 #else
 449 int dram_init_banksize(void)
 450 {
 451 #if defined(CONFIG_NR_DRAM_BANKS)
 452         gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
 453         gd->bd->bi_dram[0].size = get_effective_memsize();
 454 #endif
 455
 456         mem_map_fill();
 457
 458         return 0;
 459 }
 460
 461 int dram_init(void)
 462 {
 463         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
 464                                     CONFIG_SYS_SDRAM_SIZE);
 465
 466         return 0;
 467 }
 468 #endif
 469
 470 void reset_cpu(ulong addr)
 471 {
 472 }
 473
 474 #if defined(CONFIG_BOARD_LATE_INIT)
 475 static const struct {
 476         u32 bit;
 477         const char *name;
 478 } reset_reasons[] = {
 479         { RESET_REASON_DEBUG_SYS, "DEBUG" },
 480         { RESET_REASON_SOFT, "SOFT" },
 481         { RESET_REASON_SRST, "SRST" },
 482         { RESET_REASON_PSONLY, "PS-ONLY" },
 483         { RESET_REASON_PMU, "PMU" },
 484         { RESET_REASON_INTERNAL, "INTERNAL" },
 485         { RESET_REASON_EXTERNAL, "EXTERNAL" },
 486         {}
 487 };
 488
 489 static int reset_reason(void)
 490 {
 491         u32 reg;
 492         int i, ret;
 493         const char *reason = NULL;
 494
 495         ret = zynqmp_mmio_read((ulong)&crlapb_base->reset_reason, &reg);
 496         if (ret)
 497                 return -EINVAL;
 498
 499         puts("Reset reason:\t");
 500
 501         for (i = 0; i < ARRAY_SIZE(reset_reasons); i++) {
 502                 if (reg & reset_reasons[i].bit) {
 503                         reason = reset_reasons[i].name;
 504                         printf("%s ", reset_reasons[i].name);
 505                         break;
 506                 }
 507         }
 508
 509         puts("\n");
 510
 511         env_set("reset_reason", reason);
 512
 513         ret = zynqmp_mmio_write(~0, ~0, (ulong)&crlapb_base->reset_reason);
 514         if (ret)
 515                 return -EINVAL;
 516
 517         return ret;
 518 }
 519
 520 static int set_fdtfile(void)
 521 {
 522         char *compatible, *fdtfile;
 523         const char *suffix = ".dtb";
 524         const char *vendor = "xilinx/";
 525
 526         if (env_get("fdtfile"))
 527                 return 0;
 528
 529         compatible = (char *)fdt_getprop(gd->fdt_blob, 0, "compatible", NULL);
 530         if (compatible) {
 531                 debug("Compatible: %s\n", compatible);
 532
 533                 /* Discard vendor prefix */
 534                 strsep(&compatible, ",");
 535
 536                 fdtfile = calloc(1, strlen(vendor) + strlen(compatible) +
 537                                  strlen(suffix) + 1);
 538                 if (!fdtfile)
 539                         return -ENOMEM;
 540
 541                 sprintf(fdtfile, "%s%s%s", vendor, compatible, suffix);
 542
 543                 env_set("fdtfile", fdtfile);
 544                 free(fdtfile);
 545         }
 546
 547         return 0;
 548 }
 549
 550 int board_late_init(void)
 551 {
 552         u32 reg = 0;
 553         u8 bootmode;
 554         struct udevice *dev;
 555         int bootseq = -1;
 556         int bootseq_len = 0;
 557         int env_targets_len = 0;
 558         const char *mode;
 559         char *new_targets;
 560         char *env_targets;
 561         int ret;
 562
 563 #if defined(CONFIG_USB_ETHER) && !defined(CONFIG_USB_GADGET_DOWNLOAD)
 564         usb_ether_init();
 565 #endif
 566
 567         if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
 568                 debug("Saved variables - Skipping\n");
 569                 return 0;
 570         }
 571
 572         ret = set_fdtfile();
 573         if (ret)
 574                 return ret;
 575
 576         ret = zynqmp_mmio_read((ulong)&crlapb_base->boot_mode, &reg);
 577         if (ret)
 578                 return -EINVAL;
 579
 580         if (reg >> BOOT_MODE_ALT_SHIFT)
 581                 reg >>= BOOT_MODE_ALT_SHIFT;
 582
 583         bootmode = reg & BOOT_MODES_MASK;
 584
 585         puts("Bootmode: ");
 586         switch (bootmode) {
 587         case USB_MODE:
 588                 puts("USB_MODE\n");
 589                 mode = "usb";
 590                 env_set("modeboot", "usb_dfu_spl");
 591                 break;
 592         case JTAG_MODE:
 593                 puts("JTAG_MODE\n");
 594                 mode = "pxe dhcp";
 595                 env_set("modeboot", "jtagboot");
 596                 break;
 597         case QSPI_MODE_24BIT:
 598         case QSPI_MODE_32BIT:
 599                 mode = "qspi0";
 600                 puts("QSPI_MODE\n");
 601                 env_set("modeboot", "qspiboot");
 602                 break;
 603         case EMMC_MODE:
 604                 puts("EMMC_MODE\n");
 605                 mode = "mmc0";
 606                 env_set("modeboot", "emmcboot");
 607                 break;
 608         case SD_MODE:
 609                 puts("SD_MODE\n");
 610                 if (uclass_get_device_by_name(UCLASS_MMC,
 611                                               "mmc@ff160000", &dev) &&
 612                     uclass_get_device_by_name(UCLASS_MMC,
 613                                               "sdhci@ff160000", &dev)) {
 614                         puts("Boot from SD0 but without SD0 enabled!\n");
 615                         return -1;
 616                 }
 617                 debug("mmc0 device found at %p, seq %d\n", dev, dev->seq);
 618
 619                 mode = "mmc";
 620                 bootseq = dev->seq;
 621                 env_set("modeboot", "sdboot");
 622                 break;
 623         case SD1_LSHFT_MODE:
 624                 puts("LVL_SHFT_");
 625                 /* fall through */
 626         case SD_MODE1:
 627                 puts("SD_MODE1\n");
 628                 if (uclass_get_device_by_name(UCLASS_MMC,
 629                                               "mmc@ff170000", &dev) &&
 630                     uclass_get_device_by_name(UCLASS_MMC,
 631                                               "sdhci@ff170000", &dev)) {
 632                         puts("Boot from SD1 but without SD1 enabled!\n");
 633                         return -1;
 634                 }
 635                 debug("mmc1 device found at %p, seq %d\n", dev, dev->seq);
 636
 637                 mode = "mmc";
 638                 bootseq = dev->seq;
 639                 env_set("modeboot", "sdboot");
 640                 break;
 641         case NAND_MODE:
 642                 puts("NAND_MODE\n");
 643                 mode = "nand0";
 644                 env_set("modeboot", "nandboot");
 645                 break;
 646         default:
 647                 mode = "";
 648                 printf("Invalid Boot Mode:0x%x\n", bootmode);
 649                 break;
 650         }
 651
 652         if (bootseq >= 0) {
 653                 bootseq_len = snprintf(NULL, 0, "%i", bootseq);
 654                 debug("Bootseq len: %x\n", bootseq_len);
 655         }
 656
 657         /*
 658          * One terminating char + one byte for space between mode
 659          * and default boot_targets
 660          */
 661         env_targets = env_get("boot_targets");
 662         if (env_targets)
 663                 env_targets_len = strlen(env_targets);
 664
 665         new_targets = calloc(1, strlen(mode) + env_targets_len + 2 +
 666                              bootseq_len);
 667         if (!new_targets)
 668                 return -ENOMEM;
 669
 670         if (bootseq >= 0)
 671                 sprintf(new_targets, "%s%x %s", mode, bootseq,
 672                         env_targets ? env_targets : "");
 673         else
 674                 sprintf(new_targets, "%s %s", mode,
 675                         env_targets ? env_targets : "");
 676
 677         env_set("boot_targets", new_targets);
 678
 679         reset_reason();
 680
 681         return 0;
 682 }
 683 #endif
 684
 685 int checkboard(void)
 686 {
 687         puts("Board: Xilinx ZynqMP\n");
 688         return 0;
 689 }