drivers/pinctrl/exynos/pinctrl-exynos850.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2023 Linaro Ltd.
   4  * Author: Sam Protsenko <[email protected]>
   5  *
   6  * Exynos850 pinctrl driver.
   7  */
   8
   9 #include <dm.h>
  10 #include <dm/pinctrl.h>
  11 #include "pinctrl-exynos.h"
  12
  13 #define EXYNOS850_PIN_BANK(pins, reg, id)               \
  14         {                                               \
  15                 .type           = &exynos850_bank_type, \
  16                 .offset         = reg,                  \
  17                 .nr_pins        = pins,                 \
  18                 .name           = id                    \
  19         }
  20
  21 /* CON, DAT, PUD, DRV */
  22 static const struct samsung_pin_bank_type exynos850_bank_type = {
  23         .fld_width = { 4, 1, 4, 4, },
  24         .reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
  25 };
  26
  27 static const struct pinctrl_ops exynos850_pinctrl_ops = {
  28         .set_state = exynos_pinctrl_set_state
  29 };
  30
  31 /* pin banks of exynos850 pin-controller 0 (ALIVE) */
  32 static const struct samsung_pin_bank_data exynos850_pin_banks0[] = {
  33         EXYNOS850_PIN_BANK(8, 0x000, "gpa0"),
  34         EXYNOS850_PIN_BANK(8, 0x020, "gpa1"),
  35         EXYNOS850_PIN_BANK(8, 0x040, "gpa2"),
  36         EXYNOS850_PIN_BANK(8, 0x060, "gpa3"),
  37         EXYNOS850_PIN_BANK(4, 0x080, "gpa4"),
  38         EXYNOS850_PIN_BANK(3, 0x0a0, "gpq0"),
  39 };
  40
  41 /* pin banks of exynos850 pin-controller 1 (CMGP) */
  42 static const struct samsung_pin_bank_data exynos850_pin_banks1[] = {
  43         EXYNOS850_PIN_BANK(1, 0x000, "gpm0"),
  44         EXYNOS850_PIN_BANK(1, 0x020, "gpm1"),
  45         EXYNOS850_PIN_BANK(1, 0x040, "gpm2"),
  46         EXYNOS850_PIN_BANK(1, 0x060, "gpm3"),
  47         EXYNOS850_PIN_BANK(1, 0x080, "gpm4"),
  48         EXYNOS850_PIN_BANK(1, 0x0a0, "gpm5"),
  49         EXYNOS850_PIN_BANK(1, 0x0c0, "gpm6"),
  50         EXYNOS850_PIN_BANK(1, 0x0e0, "gpm7"),
  51 };
  52
  53 /* pin banks of exynos850 pin-controller 2 (AUD) */
  54 static const struct samsung_pin_bank_data exynos850_pin_banks2[] = {
  55         EXYNOS850_PIN_BANK(5, 0x000, "gpb0"),
  56         EXYNOS850_PIN_BANK(5, 0x020, "gpb1"),
  57 };
  58
  59 /* pin banks of exynos850 pin-controller 3 (HSI) */
  60 static const struct samsung_pin_bank_data exynos850_pin_banks3[] = {
  61         EXYNOS850_PIN_BANK(6, 0x000, "gpf2"),
  62 };
  63
  64 /* pin banks of exynos850 pin-controller 4 (CORE) */
  65 static const struct samsung_pin_bank_data exynos850_pin_banks4[] = {
  66         EXYNOS850_PIN_BANK(4, 0x000, "gpf0"),
  67         EXYNOS850_PIN_BANK(8, 0x020, "gpf1"),
  68 };
  69
  70 /* pin banks of exynos850 pin-controller 5 (PERI) */
  71 static const struct samsung_pin_bank_data exynos850_pin_banks5[] = {
  72         EXYNOS850_PIN_BANK(2, 0x000, "gpg0"),
  73         EXYNOS850_PIN_BANK(6, 0x020, "gpp0"),
  74         EXYNOS850_PIN_BANK(4, 0x040, "gpp1"),
  75         EXYNOS850_PIN_BANK(4, 0x060, "gpp2"),
  76         EXYNOS850_PIN_BANK(8, 0x080, "gpg1"),
  77         EXYNOS850_PIN_BANK(8, 0x0a0, "gpg2"),
  78         EXYNOS850_PIN_BANK(1, 0x0c0, "gpg3"),
  79         EXYNOS850_PIN_BANK(3, 0x0e0, "gpc0"),
  80         EXYNOS850_PIN_BANK(6, 0x100, "gpc1"),
  81 };
  82
  83 static const struct samsung_pin_ctrl exynos850_pin_ctrl[] = {
  84         {
  85                 /* pin-controller instance 0 ALIVE data */
  86                 .pin_banks      = exynos850_pin_banks0,
  87                 .nr_banks       = ARRAY_SIZE(exynos850_pin_banks0),
  88         }, {
  89                 /* pin-controller instance 1 CMGP data */
  90                 .pin_banks      = exynos850_pin_banks1,
  91                 .nr_banks       = ARRAY_SIZE(exynos850_pin_banks1),
  92         }, {
  93                 /* pin-controller instance 2 AUD data */
  94                 .pin_banks      = exynos850_pin_banks2,
  95                 .nr_banks       = ARRAY_SIZE(exynos850_pin_banks2),
  96         }, {
  97                 /* pin-controller instance 3 HSI data */
  98                 .pin_banks      = exynos850_pin_banks3,
  99                 .nr_banks       = ARRAY_SIZE(exynos850_pin_banks3),
 100         }, {
 101                 /* pin-controller instance 4 CORE data */
 102                 .pin_banks      = exynos850_pin_banks4,
 103                 .nr_banks       = ARRAY_SIZE(exynos850_pin_banks4),
 104         }, {
 105                 /* pin-controller instance 5 PERI data */
 106                 .pin_banks      = exynos850_pin_banks5,
 107                 .nr_banks       = ARRAY_SIZE(exynos850_pin_banks5),
 108         },
 109         {/* list terminator */}
 110 };
 111
 112 static const struct udevice_id exynos850_pinctrl_ids[] = {
 113         { .compatible = "samsung,exynos850-pinctrl",
 114                 .data = (ulong)exynos850_pin_ctrl },
 115         { }
 116 };
 117
 118 U_BOOT_DRIVER(pinctrl_exynos850) = {
 119         .name           = "pinctrl_exynos850",
 120         .id             = UCLASS_PINCTRL,
 121         .of_match       = exynos850_pinctrl_ids,
 122         .priv_auto      = sizeof(struct exynos_pinctrl_priv),
 123         .ops            = &exynos850_pinctrl_ops,
 124         .probe          = exynos_pinctrl_probe,
 125 };