board/variscite/dart_6ul/spl.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2015-2019 Variscite Ltd.
   4  * Copyright (C) 2019 Parthiban Nallathambi <[email protected]>
   5  */
   6
   7 #include <common.h>
   8 #include <init.h>
   9 #include <spl.h>
  10 #include <asm/arch/clock.h>
  11 #include <asm/io.h>
  12 #include <asm/arch/mx6-ddr.h>
  13 #include <asm/arch/mx6-pins.h>
  14 #include <asm/arch/crm_regs.h>
  15 #include <fsl_esdhc_imx.h>
  16
  17 #define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |             \
  18         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  19         PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  20
  21 static iomux_v3_cfg_t const uart1_pads[] = {
  22         MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  23         MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  24 };
  25
  26 static void setup_iomux_uart(void)
  27 {
  28         imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
  29 }
  30
  31 static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
  32         .grp_addds = 0x00000030,
  33         .grp_ddrmode_ctl = 0x00020000,
  34         .grp_b0ds = 0x00000030,
  35         .grp_ctlds = 0x00000030,
  36         .grp_b1ds = 0x00000030,
  37         .grp_ddrpke = 0x00000000,
  38         .grp_ddrmode = 0x00020000,
  39         .grp_ddr_type = 0x000c0000,
  40 };
  41
  42 static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
  43         .dram_dqm0 = 0x00000030,
  44         .dram_dqm1 = 0x00000030,
  45         .dram_ras = 0x00000030,
  46         .dram_cas = 0x00000030,
  47         .dram_odt0 = 0x00000030,
  48         .dram_odt1 = 0x00000030,
  49         .dram_sdba2 = 0x00000000,
  50         .dram_sdclk_0 = 0x00000008,
  51         .dram_sdqs0 = 0x00000038,
  52         .dram_sdqs1 = 0x00000030,
  53         .dram_reset = 0x00000030,
  54 };
  55
  56 static struct mx6_mmdc_calibration mx6_mmcd_calib = {
  57         .p0_mpwldectrl0 = 0x00000000,
  58         .p0_mpdgctrl0   = 0x414C0158,
  59         .p0_mprddlctl   = 0x40403A3A,
  60         .p0_mpwrdlctl   = 0x40405A56,
  61 };
  62
  63 struct mx6_ddr_sysinfo ddr_sysinfo = {
  64         .dsize = 0,
  65         .cs_density = 20,
  66         .ncs = 1,
  67         .cs1_mirror = 0,
  68         .rtt_wr = 2,
  69         .rtt_nom = 1,           /* RTT_Nom = RZQ/2 */
  70         .walat = 1,             /* Write additional latency */
  71         .ralat = 5,             /* Read additional latency */
  72         .mif3_mode = 3,         /* Command prediction working mode */
  73         .bi_on = 1,             /* Bank interleaving enabled */
  74         .sde_to_rst = 0x10,     /* 14 cycles, 200us (JEDEC default) */
  75         .rst_to_cke = 0x23,     /* 33 cycles, 500us (JEDEC default) */
  76 };
  77
  78 static struct mx6_ddr3_cfg mem_ddr = {
  79         .mem_speed = 800,
  80         .density = 4,
  81         .width = 16,
  82         .banks = 8,
  83         .rowaddr = 15,
  84         .coladdr = 10,
  85         .pagesz = 2,
  86         .trcd = 1375,
  87         .trcmin = 4875,
  88         .trasmin = 3500,
  89 };
  90
  91 static void ccgr_init(void)
  92 {
  93         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  94
  95         writel(0xFFFFFFFF, &ccm->CCGR0);
  96         writel(0xFFFFFFFF, &ccm->CCGR1);
  97         writel(0xFFFFFFFF, &ccm->CCGR2);
  98         writel(0xFFFFFFFF, &ccm->CCGR3);
  99         writel(0xFFFFFFFF, &ccm->CCGR4);
 100         writel(0xFFFFFFFF, &ccm->CCGR5);
 101         writel(0xFFFFFFFF, &ccm->CCGR6);
 102         writel(0xFFFFFFFF, &ccm->CCGR7);
 103         /* Enable Audio Clock for SOM codec */
 104         writel(0x01130100, (long *)CCM_CCOSR);
 105 }
 106
 107 static void spl_dram_init(void)
 108 {
 109         mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
 110         mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
 111 }
 112
 113 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |             \
 114         PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW |               \
 115         PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 116 static iomux_v3_cfg_t const usdhc1_pads[] = {
 117         MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 118         MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 119         MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 120         MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 121         MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 122         MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 123 };
 124
 125 #ifndef CONFIG_NAND_MXS
 126 static iomux_v3_cfg_t const usdhc2_pads[] = {
 127         MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 128         MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 129         MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 130         MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 131         MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 132         MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 133         MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 134         MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 135         MX6_PAD_NAND_DATA06__USDHC2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 136         MX6_PAD_NAND_DATA07__USDHC2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 137 };
 138 #endif
 139
 140 static struct fsl_esdhc_cfg usdhc_cfg[] = {
 141         {
 142                 .esdhc_base = USDHC1_BASE_ADDR,
 143                 .max_bus_width = 4,
 144         },
 145 #ifndef CONFIG_NAND_MXS
 146         {
 147                 .esdhc_base = USDHC2_BASE_ADDR,
 148                 .max_bus_width = 8,
 149         },
 150 #endif
 151 };
 152
 153 int board_mmc_getcd(struct mmc *mmc)
 154 {
 155         return 1;
 156 }
 157
 158 int board_mmc_init(struct bd_info *bis)
 159 {
 160         int i, ret;
 161
 162         for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) {
 163                 switch (i) {
 164                 case 0:
 165                         SETUP_IOMUX_PADS(usdhc1_pads);
 166                         usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 167                         break;
 168 #ifndef CONFIG_NAND_MXS
 169                 case 1:
 170                         SETUP_IOMUX_PADS(usdhc2_pads);
 171                         usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 172                         break;
 173 #endif
 174                 default:
 175                         printf("Warning - USDHC%d controller not supporting\n",
 176                                i + 1);
 177                         return 0;
 178                 }
 179
 180                 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
 181                 if (ret) {
 182                         printf("Warning: failed to initialize mmc dev %d\n", i);
 183                         return ret;
 184                 }
 185         }
 186
 187         return 0;
 188 }
 189
 190 void board_init_f(ulong dummy)
 191 {
 192         /* setup AIPS and disable watchdog */
 193         arch_cpu_init();
 194
 195         ccgr_init();
 196
 197         /* setup GP timer */
 198         timer_init();
 199
 200         setup_iomux_uart();
 201
 202         /* UART clocks enabled and gd valid - init serial console */
 203         preloader_console_init();
 204
 205         /* DDR initialization */
 206         spl_dram_init();
 207
 208         /* Clear the BSS. */
 209         memset(__bss_start, 0, __bss_end - __bss_start);
 210
 211         /* load/boot image from boot device */
 212         board_init_r(NULL, 0);
 213 }