board/freescale/imx93_evk/spl.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2022 NXP
   4  */
   5
   6 #include <common.h>
   7 #include <command.h>
   8 #include <cpu_func.h>
   9 #include <hang.h>
  10 #include <image.h>
  11 #include <init.h>
  12 #include <log.h>
  13 #include <spl.h>
  14 #include <asm/global_data.h>
  15 #include <asm/io.h>
  16 #include <asm/arch/imx93_pins.h>
  17 #include <asm/arch/clock.h>
  18 #include <asm/arch/sys_proto.h>
  19 #include <asm/mach-imx/boot_mode.h>
  20 #include <asm/mach-imx/mxc_i2c.h>
  21 #include <asm/arch-mx7ulp/gpio.h>
  22 #include <asm/mach-imx/syscounter.h>
  23 #include <dm/uclass.h>
  24 #include <dm/device.h>
  25 #include <dm/uclass-internal.h>
  26 #include <dm/device-internal.h>
  27 #include <linux/delay.h>
  28 #include <asm/arch/clock.h>
  29 #include <asm/arch/ccm_regs.h>
  30 #include <asm/arch/ddr.h>
  31 #include <power/pmic.h>
  32 #include <power/pca9450.h>
  33 #include <asm/arch/trdc.h>
  34
  35 DECLARE_GLOBAL_DATA_PTR;
  36
  37 int spl_board_boot_device(enum boot_device boot_dev_spl)
  38 {
  39         return BOOT_DEVICE_BOOTROM;
  40 }
  41
  42 void spl_board_init(void)
  43 {
  44         puts("Normal Boot\n");
  45 }
  46
  47 void spl_dram_init(void)
  48 {
  49         ddr_init(&dram_timing);
  50 }
  51
  52 #if CONFIG_IS_ENABLED(DM_PMIC_PCA9450)
  53 int power_init_board(void)
  54 {
  55         struct udevice *dev;
  56         int ret;
  57
  58         ret = pmic_get("pmic@25", &dev);
  59         if (ret == -ENODEV) {
  60                 puts("No pca9450@25\n");
  61                 return 0;
  62         }
  63         if (ret != 0)
  64                 return ret;
  65
  66         /* BUCKxOUT_DVS0/1 control BUCK123 output */
  67         pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29);
  68
  69         /* enable DVS control through PMIC_STBY_REQ */
  70         pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59);
  71
  72         if (IS_ENABLED(CONFIG_IMX9_LOW_DRIVE_MODE)) {
  73                 /* 0.75v for Low drive mode
  74                  */
  75                 pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x0c);
  76                 pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, 0x0c);
  77         } else {
  78                 /* 0.9v for Over drive mode
  79                  */
  80                 pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x18);
  81                 pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, 0x18);
  82         }
  83
  84         /* set standby voltage to 0.65v */
  85         pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x4);
  86
  87         /* I2C_LT_EN*/
  88         pmic_reg_write(dev, 0xa, 0x3);
  89         return 0;
  90 }
  91 #endif
  92
  93 extern int imx9_probe_mu(void *ctx, struct event *event);
  94 void board_init_f(ulong dummy)
  95 {
  96         int ret;
  97
  98         /* Clear the BSS. */
  99         memset(__bss_start, 0, __bss_end - __bss_start);
 100
 101         timer_init();
 102
 103         arch_cpu_init();
 104
 105         board_early_init_f();
 106
 107         spl_early_init();
 108
 109         preloader_console_init();
 110
 111         ret = imx9_probe_mu(NULL, NULL);
 112         if (ret) {
 113                 printf("Fail to init Sentinel API\n");
 114         } else {
 115                 printf("SOC: 0x%x\n", gd->arch.soc_rev);
 116                 printf("LC: 0x%x\n", gd->arch.lifecycle);
 117         }
 118
 119         power_init_board();
 120
 121         if (!IS_ENABLED(CONFIG_IMX9_LOW_DRIVE_MODE))
 122                 set_arm_clk(get_cpu_speed_grade_hz());
 123
 124         /* Init power of mix */
 125         soc_power_init();
 126
 127         /* Setup TRDC for DDR access */
 128         trdc_init();
 129
 130         /* DDR initialization */
 131         spl_dram_init();
 132
 133         /* Put M33 into CPUWAIT for following kick */
 134         ret = m33_prepare();
 135         if (!ret)
 136                 printf("M33 prepare ok\n");
 137
 138         board_init_r(NULL, 0);
 139 }