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1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright 2020 Compass Electronics Group, LLC
4  */
5
6 #include <common.h>
7 #include <hang.h>
8 #include <image.h>
9 #include <init.h>
10 #include <log.h>
11 #include <asm/io.h>
12 #include <errno.h>
13 #include <asm/global_data.h>
14 #include <asm/io.h>
15 #include <asm/arch/ddr.h>
16 #include <asm/arch/imx8mn_pins.h>
17 #include <asm/mach-imx/boot_mode.h>
18 #include <asm/arch/sys_proto.h>
19 #include <asm/arch/clock.h>
20 #include <asm/mach-imx/iomux-v3.h>
21 #include <asm/mach-imx/gpio.h>
22 #include <asm/mach-imx/mxc_i2c.h>
23 #include <fsl_esdhc_imx.h>
24 #include <mmc.h>
25 #include <linux/delay.h>
26 #include <power/pmic.h>
27 #include <power/bd71837.h>
28 #include <spl.h>
29
30 #include <dm/uclass.h>
31 #include <dm/device.h>
32 #include <dm/uclass-internal.h>
33 #include <dm/device-internal.h>
34
35 DECLARE_GLOBAL_DATA_PTR;
36
37 int spl_board_boot_device(enum boot_device boot_dev_spl)
38 {
39         return BOOT_DEVICE_BOOTROM;
40 }
41
42 void spl_dram_init(void)
43 {
44         ddr_init(&dram_timing);
45 }
46
47 void spl_board_init(void)
48 {
49         struct udevice *dev;
50         int ret;
51
52         debug("Normal Boot\n");
53
54         ret = uclass_get_device_by_name(UCLASS_CLK,
55                                         "clock-controller@30380000",
56                                         &dev);
57         if (ret < 0)
58                 puts("Failed to find clock node. Check device tree\n");
59 }
60
61 #ifdef CONFIG_SPL_LOAD_FIT
62 int board_fit_config_name_match(const char *name)
63 {
64         /* Just empty function now - can't decide what to choose */
65         debug("%s: %s\n", __func__, name);
66
67         return 0;
68 }
69 #endif
70
71 #define PWM1_PAD_CTRL (PAD_CTL_FSEL2 | PAD_CTL_DSE6)
72
73 static iomux_v3_cfg_t const pwm_pads[] = {
74         IMX8MN_PAD_GPIO1_IO01__PWM1_OUT | MUX_PAD_CTRL(PWM1_PAD_CTRL),
75 };
76
77 static int power_init_board(void)
78 {
79         struct udevice *dev;
80         int ret;
81
82         ret = pmic_get("pmic@4b", &dev);
83         if (ret == -ENODEV) {
84                 puts("No pmic\n");
85                 return 0;
86         }
87
88         if (ret != 0)
89                 return ret;
90
91         /* decrease RESET key long push time from the default 10s to 10ms */
92         pmic_reg_write(dev, BD718XX_PWRONCONFIG1, 0x0);
93
94         /* unlock the PMIC regs */
95         pmic_reg_write(dev, BD718XX_REGLOCK, 0x1);
96
97         /* increase VDD_SOC to typical value 0.85v before first DRAM access */
98         pmic_reg_write(dev, BD718XX_BUCK1_VOLT_RUN, 0x0f);
99
100         /* increase VDD_DRAM to 0.975v for 3Ghz DDR */
101         pmic_reg_write(dev, BD718XX_1ST_NODVS_BUCK_VOLT, 0x83);
102
103         /* lock the PMIC regs */
104         pmic_reg_write(dev, BD718XX_REGLOCK, 0x11);
105
106         return 0;
107 }
108
109 int board_early_init_f(void)
110 {
111         /* Claiming pwm pins prevents LCD flicker during startup*/
112         imx_iomux_v3_setup_multiple_pads(pwm_pads, ARRAY_SIZE(pwm_pads));
113
114         init_uart_clk(1);
115
116         return 0;
117 }
118
119 void board_init_f(ulong dummy)
120 {
121         int ret;
122
123         /* Clear the BSS. */
124         memset(__bss_start, 0, __bss_end - __bss_start);
125
126         arch_cpu_init();
127
128         board_early_init_f();
129
130         timer_init();
131
132         ret = spl_init();
133         if (ret) {
134                 debug("spl_init() failed: %d\n", ret);
135                 hang();
136         }
137
138         preloader_console_init();
139
140         enable_tzc380();
141
142         /* LPDDR4 at 1.6GHz requires a voltage adjustment on the PMIC */
143         power_init_board();
144
145         /* DDR initialization */
146         spl_dram_init();
147
148         board_init_r(NULL, 0);
149 }
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