arch/arm/mach-imx/imx8m/soc.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2017-2019, 2021 NXP
   4  *
   5  * Peng Fan <[email protected]>
   6  */
   7
   8 #include <common.h>
   9 #include <cpu_func.h>
  10 #include <event.h>
  11 #include <init.h>
  12 #include <log.h>
  13 #include <asm/arch/imx-regs.h>
  14 #include <asm/global_data.h>
  15 #include <asm/io.h>
  16 #include <asm/arch/clock.h>
  17 #include <asm/arch/sys_proto.h>
  18 #include <asm/mach-imx/hab.h>
  19 #include <asm/mach-imx/boot_mode.h>
  20 #include <asm/mach-imx/syscounter.h>
  21 #include <asm/ptrace.h>
  22 #include <asm/armv8/mmu.h>
  23 #include <dm/uclass.h>
  24 #include <dm/device.h>
  25 #include <efi_loader.h>
  26 #include <env.h>
  27 #include <env_internal.h>
  28 #include <errno.h>
  29 #include <fdt_support.h>
  30 #include <fsl_wdog.h>
  31 #include <imx_sip.h>
  32 #include <linux/bitops.h>
  33
  34 DECLARE_GLOBAL_DATA_PTR;
  35
  36 #if defined(CONFIG_IMX_HAB)
  37 struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
  38         .bank = 1,
  39         .word = 3,
  40 };
  41 #endif
  42
  43 int timer_init(void)
  44 {
  45 #ifdef CONFIG_SPL_BUILD
  46         struct sctr_regs *sctr = (struct sctr_regs *)SYSCNT_CTRL_BASE_ADDR;
  47         unsigned long freq = readl(&sctr->cntfid0);
  48
  49         /* Update with accurate clock frequency */
  50         asm volatile("msr cntfrq_el0, %0" : : "r" (freq) : "memory");
  51
  52         clrsetbits_le32(&sctr->cntcr, SC_CNTCR_FREQ0 | SC_CNTCR_FREQ1,
  53                         SC_CNTCR_FREQ0 | SC_CNTCR_ENABLE | SC_CNTCR_HDBG);
  54 #endif
  55
  56         gd->arch.tbl = 0;
  57         gd->arch.tbu = 0;
  58
  59         return 0;
  60 }
  61
  62 void enable_tzc380(void)
  63 {
  64         struct iomuxc_gpr_base_regs *gpr =
  65                 (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
  66
  67         /* Enable TZASC and lock setting */
  68         setbits_le32(&gpr->gpr[10], GPR_TZASC_EN);
  69         setbits_le32(&gpr->gpr[10], GPR_TZASC_EN_LOCK);
  70
  71         /*
  72          * According to TRM, TZASC_ID_SWAP_BYPASS should be set in
  73          * order to avoid AXI Bus errors when GPU is in use
  74          */
  75         setbits_le32(&gpr->gpr[10], GPR_TZASC_ID_SWAP_BYPASS);
  76
  77         /*
  78          * imx8mn and imx8mp implements the lock bit for
  79          * TZASC_ID_SWAP_BYPASS, enable it to lock settings
  80          */
  81         setbits_le32(&gpr->gpr[10], GPR_TZASC_ID_SWAP_BYPASS_LOCK);
  82
  83         /*
  84          * set Region 0 attribute to allow secure and non-secure
  85          * read/write permission. Found some masters like usb dwc3
  86          * controllers can't work with secure memory.
  87          */
  88         writel(0xf0000000, TZASC_BASE_ADDR + 0x108);
  89 }
  90
  91 void set_wdog_reset(struct wdog_regs *wdog)
  92 {
  93         /*
  94          * Output WDOG_B signal to reset external pmic or POR_B decided by
  95          * the board design. Without external reset, the peripherals/DDR/
  96          * PMIC are not reset, that may cause system working abnormal.
  97          * WDZST bit is write-once only bit. Align this bit in kernel,
  98          * otherwise kernel code will have no chance to set this bit.
  99          */
 100         setbits_le16(&wdog->wcr, WDOG_WDT_MASK | WDOG_WDZST_MASK);
 101 }
 102
 103 #ifdef CONFIG_ARMV8_PSCI
 104 #define PTE_MAP_NS      PTE_BLOCK_NS
 105 #else
 106 #define PTE_MAP_NS      0
 107 #endif
 108
 109 static struct mm_region imx8m_mem_map[] = {
 110         {
 111                 /* ROM */
 112                 .virt = 0x0UL,
 113                 .phys = 0x0UL,
 114                 .size = 0x100000UL,
 115                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 116                          PTE_BLOCK_OUTER_SHARE
 117         }, {
 118                 /* CAAM */
 119                 .virt = 0x100000UL,
 120                 .phys = 0x100000UL,
 121                 .size = 0x8000UL,
 122                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 123                          PTE_BLOCK_NON_SHARE |
 124                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
 125         }, {
 126                 /* OCRAM_S */
 127                 .virt = 0x180000UL,
 128                 .phys = 0x180000UL,
 129                 .size = 0x8000UL,
 130                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 131                          PTE_BLOCK_OUTER_SHARE | PTE_MAP_NS
 132         }, {
 133                 /* TCM */
 134                 .virt = 0x7C0000UL,
 135                 .phys = 0x7C0000UL,
 136                 .size = 0x80000UL,
 137                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 138                          PTE_BLOCK_NON_SHARE |
 139                          PTE_BLOCK_PXN | PTE_BLOCK_UXN | PTE_MAP_NS
 140         }, {
 141                 /* OCRAM */
 142                 .virt = 0x900000UL,
 143                 .phys = 0x900000UL,
 144                 .size = 0x200000UL,
 145                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 146                          PTE_BLOCK_OUTER_SHARE | PTE_MAP_NS
 147         }, {
 148                 /* AIPS */
 149                 .virt = 0xB00000UL,
 150                 .phys = 0xB00000UL,
 151                 .size = 0x3f500000UL,
 152                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 153                          PTE_BLOCK_NON_SHARE |
 154                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
 155         }, {
 156                 /* DRAM1 */
 157                 .virt = 0x40000000UL,
 158                 .phys = 0x40000000UL,
 159                 .size = PHYS_SDRAM_SIZE,
 160                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 161                          PTE_BLOCK_OUTER_SHARE | PTE_MAP_NS
 162 #ifdef PHYS_SDRAM_2_SIZE
 163         }, {
 164                 /* DRAM2 */
 165                 .virt = 0x100000000UL,
 166                 .phys = 0x100000000UL,
 167                 .size = PHYS_SDRAM_2_SIZE,
 168                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 169                          PTE_BLOCK_OUTER_SHARE | PTE_MAP_NS
 170 #endif
 171         }, {
 172                 /* empty entrie to split table entry 5 if needed when TEEs are used */
 173                 0,
 174         }, {
 175                 /* List terminator */
 176                 0,
 177         }
 178 };
 179
 180 struct mm_region *mem_map = imx8m_mem_map;
 181
 182 static unsigned int imx8m_find_dram_entry_in_mem_map(void)
 183 {
 184         int i;
 185
 186         for (i = 0; i < ARRAY_SIZE(imx8m_mem_map); i++)
 187                 if (imx8m_mem_map[i].phys == CFG_SYS_SDRAM_BASE)
 188                         return i;
 189
 190         hang(); /* Entry not found, this must never happen. */
 191 }
 192
 193 void enable_caches(void)
 194 {
 195         /* If OPTEE runs, remove OPTEE memory from MMU table to avoid speculative prefetch
 196          * If OPTEE does not run, still update the MMU table according to dram banks structure
 197          * to set correct dram size from board_phys_sdram_size
 198          */
 199         int i = 0;
 200         /*
 201          * please make sure that entry initial value matches
 202          * imx8m_mem_map for DRAM1
 203          */
 204         int entry = imx8m_find_dram_entry_in_mem_map();
 205         u64 attrs = imx8m_mem_map[entry].attrs;
 206
 207         while (i < CONFIG_NR_DRAM_BANKS &&
 208                entry < ARRAY_SIZE(imx8m_mem_map)) {
 209                 if (gd->bd->bi_dram[i].start == 0)
 210                         break;
 211                 imx8m_mem_map[entry].phys = gd->bd->bi_dram[i].start;
 212                 imx8m_mem_map[entry].virt = gd->bd->bi_dram[i].start;
 213                 imx8m_mem_map[entry].size = gd->bd->bi_dram[i].size;
 214                 imx8m_mem_map[entry].attrs = attrs;
 215                 debug("Added memory mapping (%d): %llx %llx\n", entry,
 216                       imx8m_mem_map[entry].phys, imx8m_mem_map[entry].size);
 217                 i++; entry++;
 218         }
 219
 220         icache_enable();
 221         dcache_enable();
 222 }
 223
 224 __weak int board_phys_sdram_size(phys_size_t *size)
 225 {
 226         if (!size)
 227                 return -EINVAL;
 228
 229         *size = PHYS_SDRAM_SIZE;
 230
 231 #ifdef PHYS_SDRAM_2_SIZE
 232         *size += PHYS_SDRAM_2_SIZE;
 233 #endif
 234         return 0;
 235 }
 236
 237 int dram_init(void)
 238 {
 239         phys_size_t sdram_size;
 240         int ret;
 241
 242         ret = board_phys_sdram_size(&sdram_size);
 243         if (ret)
 244                 return ret;
 245
 246         /* rom_pointer[1] contains the size of TEE occupies */
 247         if (!IS_ENABLED(CONFIG_ARMV8_PSCI) && rom_pointer[1])
 248                 gd->ram_size = sdram_size - rom_pointer[1];
 249         else
 250                 gd->ram_size = sdram_size;
 251
 252         return 0;
 253 }
 254
 255 int dram_init_banksize(void)
 256 {
 257         int bank = 0;
 258         int ret;
 259         phys_size_t sdram_size;
 260         phys_size_t sdram_b1_size, sdram_b2_size;
 261
 262         ret = board_phys_sdram_size(&sdram_size);
 263         if (ret)
 264                 return ret;
 265
 266         /* Bank 1 can't cross over 4GB space */
 267         if (sdram_size > 0xc0000000) {
 268                 sdram_b1_size = 0xc0000000;
 269                 sdram_b2_size = sdram_size - 0xc0000000;
 270         } else {
 271                 sdram_b1_size = sdram_size;
 272                 sdram_b2_size = 0;
 273         }
 274
 275         gd->bd->bi_dram[bank].start = PHYS_SDRAM;
 276         if (!IS_ENABLED(CONFIG_ARMV8_PSCI) && rom_pointer[1]) {
 277                 phys_addr_t optee_start = (phys_addr_t)rom_pointer[0];
 278                 phys_size_t optee_size = (size_t)rom_pointer[1];
 279
 280                 gd->bd->bi_dram[bank].size = optee_start - gd->bd->bi_dram[bank].start;
 281                 if ((optee_start + optee_size) < (PHYS_SDRAM + sdram_b1_size)) {
 282                         if (++bank >= CONFIG_NR_DRAM_BANKS) {
 283                                 puts("CONFIG_NR_DRAM_BANKS is not enough\n");
 284                                 return -1;
 285                         }
 286
 287                         gd->bd->bi_dram[bank].start = optee_start + optee_size;
 288                         gd->bd->bi_dram[bank].size = PHYS_SDRAM +
 289                                 sdram_b1_size - gd->bd->bi_dram[bank].start;
 290                 }
 291         } else {
 292                 gd->bd->bi_dram[bank].size = sdram_b1_size;
 293         }
 294
 295         if (sdram_b2_size) {
 296                 if (++bank >= CONFIG_NR_DRAM_BANKS) {
 297                         puts("CONFIG_NR_DRAM_BANKS is not enough for SDRAM_2\n");
 298                         return -1;
 299                 }
 300                 gd->bd->bi_dram[bank].start = 0x100000000UL;
 301                 gd->bd->bi_dram[bank].size = sdram_b2_size;
 302         }
 303
 304         return 0;
 305 }
 306
 307 phys_size_t get_effective_memsize(void)
 308 {
 309         int ret;
 310         phys_size_t sdram_size;
 311         phys_size_t sdram_b1_size;
 312         ret = board_phys_sdram_size(&sdram_size);
 313         if (!ret) {
 314                 /* Bank 1 can't cross over 4GB space */
 315                 if (sdram_size > 0xc0000000) {
 316                         sdram_b1_size = 0xc0000000;
 317                 } else {
 318                         sdram_b1_size = sdram_size;
 319                 }
 320
 321                 if (!IS_ENABLED(CONFIG_ARMV8_PSCI) && rom_pointer[1]) {
 322                         /* We will relocate u-boot to Top of dram1. Tee position has two cases:
 323                          * 1. At the top of dram1,  Then return the size removed optee size.
 324                          * 2. In the middle of dram1, return the size of dram1.
 325                          */
 326                         if ((rom_pointer[0] + rom_pointer[1]) == (PHYS_SDRAM + sdram_b1_size))
 327                                 return ((phys_addr_t)rom_pointer[0] - PHYS_SDRAM);
 328                 }
 329
 330                 return sdram_b1_size;
 331         } else {
 332                 return PHYS_SDRAM_SIZE;
 333         }
 334 }
 335
 336 phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
 337 {
 338         ulong top_addr;
 339
 340         /*
 341          * Some IPs have their accessible address space restricted by
 342          * the interconnect. Let's make sure U-Boot only ever uses the
 343          * space below the 4G address boundary (which is 3GiB big),
 344          * even when the effective available memory is bigger.
 345          */
 346         top_addr = clamp_val((u64)PHYS_SDRAM + gd->ram_size, 0, 0xffffffff);
 347
 348         /*
 349          * rom_pointer[0] stores the TEE memory start address.
 350          * rom_pointer[1] stores the size TEE uses.
 351          * We need to reserve the memory region for TEE.
 352          */
 353         if (!IS_ENABLED(CONFIG_ARMV8_PSCI) && rom_pointer[0] &&
 354             rom_pointer[1] && top_addr > rom_pointer[0])
 355                 top_addr = rom_pointer[0];
 356
 357         return top_addr;
 358 }
 359
 360 static u32 get_cpu_variant_type(u32 type)
 361 {
 362         struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
 363         struct fuse_bank *bank = &ocotp->bank[1];
 364         struct fuse_bank1_regs *fuse =
 365                 (struct fuse_bank1_regs *)bank->fuse_regs;
 366
 367         u32 value = readl(&fuse->tester4);
 368
 369         if (type == MXC_CPU_IMX8MQ) {
 370                 if ((value & 0x3) == 0x2)
 371                         return MXC_CPU_IMX8MD;
 372                 else if (value & 0x200000)
 373                         return MXC_CPU_IMX8MQL;
 374
 375         } else if (type == MXC_CPU_IMX8MM) {
 376                 switch (value & 0x3) {
 377                 case 2:
 378                         if (value & 0x1c0000)
 379                                 return MXC_CPU_IMX8MMDL;
 380                         else
 381                                 return MXC_CPU_IMX8MMD;
 382                 case 3:
 383                         if (value & 0x1c0000)
 384                                 return MXC_CPU_IMX8MMSL;
 385                         else
 386                                 return MXC_CPU_IMX8MMS;
 387                 default:
 388                         if (value & 0x1c0000)
 389                                 return MXC_CPU_IMX8MML;
 390                         break;
 391                 }
 392         } else if (type == MXC_CPU_IMX8MN) {
 393                 switch (value & 0x3) {
 394                 case 2:
 395                         if (value & 0x1000000) {
 396                                 if (value & 0x10000000)  /* MIPI DSI */
 397                                         return MXC_CPU_IMX8MNUD;
 398                                 else
 399                                         return MXC_CPU_IMX8MNDL;
 400                         } else {
 401                                 return MXC_CPU_IMX8MND;
 402                         }
 403                 case 3:
 404                         if (value & 0x1000000) {
 405                                 if (value & 0x10000000)  /* MIPI DSI */
 406                                         return MXC_CPU_IMX8MNUS;
 407                                 else
 408                                         return MXC_CPU_IMX8MNSL;
 409                         } else {
 410                                 return MXC_CPU_IMX8MNS;
 411                         }
 412                 default:
 413                         if (value & 0x1000000) {
 414                                 if (value & 0x10000000)  /* MIPI DSI */
 415                                         return MXC_CPU_IMX8MNUQ;
 416                                 else
 417                                         return MXC_CPU_IMX8MNL;
 418                         }
 419                         break;
 420                 }
 421         } else if (type == MXC_CPU_IMX8MP) {
 422                 u32 value0 = readl(&fuse->tester3);
 423                 u32 flag = 0;
 424
 425                 if ((value0 & 0xc0000) == 0x80000)
 426                         return MXC_CPU_IMX8MPD;
 427
 428                         /* vpu disabled */
 429                 if ((value0 & 0x43000000) == 0x43000000)
 430                         flag = 1;
 431
 432                 /* npu disabled*/
 433                 if ((value & 0x8) == 0x8)
 434                         flag |= BIT(1);
 435
 436                 /* isp disabled */
 437                 if ((value & 0x3) == 0x3)
 438                         flag |= BIT(2);
 439
 440                 /* gpu disabled */
 441                 if ((value & 0xc0) == 0xc0)
 442                         flag |= BIT(3);
 443
 444                 /* lvds disabled */
 445                 if ((value & 0x180000) == 0x180000)
 446                         flag |= BIT(4);
 447
 448                 /* mipi dsi disabled */
 449                 if ((value & 0x60000) == 0x60000)
 450                         flag |= BIT(5);
 451
 452                 switch (flag) {
 453                 case 0x3f:
 454                         return MXC_CPU_IMX8MPUL;
 455                 case 7:
 456                         return MXC_CPU_IMX8MPL;
 457                 case 2:
 458                         return MXC_CPU_IMX8MP6;
 459                 default:
 460                         break;
 461                 }
 462
 463         }
 464
 465         return type;
 466 }
 467
 468 u32 get_cpu_rev(void)
 469 {
 470         struct anamix_pll *ana_pll = (struct anamix_pll *)ANATOP_BASE_ADDR;
 471         u32 reg = readl(&ana_pll->digprog);
 472         u32 type = (reg >> 16) & 0xff;
 473         u32 major_low = (reg >> 8) & 0xff;
 474         u32 rom_version;
 475
 476         reg &= 0xff;
 477
 478         /* iMX8MP */
 479         if (major_low == 0x43) {
 480                 type = get_cpu_variant_type(MXC_CPU_IMX8MP);
 481         } else if (major_low == 0x42) {
 482                 /* iMX8MN */
 483                 type = get_cpu_variant_type(MXC_CPU_IMX8MN);
 484         } else if (major_low == 0x41) {
 485                 type = get_cpu_variant_type(MXC_CPU_IMX8MM);
 486         } else {
 487                 if (reg == CHIP_REV_1_0) {
 488                         /*
 489                          * For B0 chip, the DIGPROG is not updated,
 490                          * it is still TO1.0. we have to check ROM
 491                          * version or OCOTP_READ_FUSE_DATA.
 492                          * 0xff0055aa is magic number for B1.
 493                          */
 494                         if (readl((void __iomem *)(OCOTP_BASE_ADDR + 0x40)) == 0xff0055aa) {
 495                                 /*
 496                                  * B2 uses same DIGPROG and OCOTP_READ_FUSE_DATA value with B1,
 497                                  * so have to check ROM to distinguish them
 498                                  */
 499                                 rom_version = readl((void __iomem *)ROM_VERSION_B0);
 500                                 rom_version &= 0xff;
 501                                 if (rom_version == CHIP_REV_2_2)
 502                                         reg = CHIP_REV_2_2;
 503                                 else
 504                                         reg = CHIP_REV_2_1;
 505                         } else {
 506                                 rom_version =
 507                                         readl((void __iomem *)ROM_VERSION_A0);
 508                                 if (rom_version != CHIP_REV_1_0) {
 509                                         rom_version = readl((void __iomem *)ROM_VERSION_B0);
 510                                         rom_version &= 0xff;
 511                                         if (rom_version == CHIP_REV_2_0)
 512                                                 reg = CHIP_REV_2_0;
 513                                 }
 514                         }
 515                 }
 516
 517                 type = get_cpu_variant_type(type);
 518         }
 519
 520         return (type << 12) | reg;
 521 }
 522
 523 static void imx_set_wdog_powerdown(bool enable)
 524 {
 525         struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
 526         struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
 527         struct wdog_regs *wdog3 = (struct wdog_regs *)WDOG3_BASE_ADDR;
 528
 529         /* Write to the PDE (Power Down Enable) bit */
 530         writew(enable, &wdog1->wmcr);
 531         writew(enable, &wdog2->wmcr);
 532         writew(enable, &wdog3->wmcr);
 533 }
 534
 535 static int imx8m_check_clock(void *ctx, struct event *event)
 536 {
 537         struct udevice *dev;
 538         int ret;
 539
 540         if (CONFIG_IS_ENABLED(CLK)) {
 541                 ret = uclass_get_device_by_name(UCLASS_CLK,
 542                                                 "clock-controller@30380000",
 543                                                 &dev);
 544                 if (ret < 0) {
 545                         printf("Failed to find clock node. Check device tree\n");
 546                         return ret;
 547                 }
 548         }
 549
 550         return 0;
 551 }
 552 EVENT_SPY(EVT_DM_POST_INIT_F, imx8m_check_clock);
 553
 554 static void imx8m_setup_snvs(void)
 555 {
 556         /* Enable SNVS clock */
 557         clock_enable(CCGR_SNVS, 1);
 558         /* Initialize glitch detect */
 559         writel(SNVS_LPPGDR_INIT, SNVS_BASE_ADDR + SNVS_LPLVDR);
 560         /* Clear interrupt status */
 561         writel(0xffffffff, SNVS_BASE_ADDR + SNVS_LPSR);
 562 }
 563
 564 static void imx8m_setup_csu_tzasc(void)
 565 {
 566         const uintptr_t tzasc_base[4] = {
 567                 0x301f0000, 0x301f0000, 0x301f0000, 0x301f0000
 568         };
 569         int i, j;
 570
 571         if (!IS_ENABLED(CONFIG_ARMV8_PSCI))
 572                 return;
 573
 574         /* CSU */
 575         for (i = 0; i < 64; i++)
 576                 writel(0x00ff00ff, (void *)CSU_BASE_ADDR + (4 * i));
 577
 578         /* TZASC */
 579         for (j = 0; j < 4; j++) {
 580                 writel(0x77777777, (void *)(tzasc_base[j]));
 581                 writel(0x77777777, (void *)(tzasc_base[j]) + 0x4);
 582                 for (i = 0; i <= 0x10; i += 4)
 583                         writel(0, (void *)(tzasc_base[j]) + 0x40 + i);
 584         }
 585 }
 586
 587 int arch_cpu_init(void)
 588 {
 589         struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
 590
 591 #if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
 592         icache_enable();
 593 #endif
 594
 595         /*
 596          * ROM might disable clock for SCTR,
 597          * enable the clock before timer_init.
 598          */
 599         if (IS_ENABLED(CONFIG_SPL_BUILD))
 600                 clock_enable(CCGR_SCTR, 1);
 601         /*
 602          * Init timer at very early state, because sscg pll setting
 603          * will use it
 604          */
 605         timer_init();
 606
 607         if (IS_ENABLED(CONFIG_SPL_BUILD)) {
 608                 clock_init();
 609                 imx_set_wdog_powerdown(false);
 610
 611                 if (is_imx8md() || is_imx8mmd() || is_imx8mmdl() || is_imx8mms() ||
 612                     is_imx8mmsl() || is_imx8mnd() || is_imx8mndl() || is_imx8mns() ||
 613                     is_imx8mnsl() || is_imx8mpd() || is_imx8mnud() || is_imx8mnus()) {
 614                         /* Power down cpu core 1, 2 and 3 for iMX8M Dual core or Single core */
 615                         struct pgc_reg *pgc_core1 = (struct pgc_reg *)(GPC_BASE_ADDR + 0x840);
 616                         struct pgc_reg *pgc_core2 = (struct pgc_reg *)(GPC_BASE_ADDR + 0x880);
 617                         struct pgc_reg *pgc_core3 = (struct pgc_reg *)(GPC_BASE_ADDR + 0x8C0);
 618                         struct gpc_reg *gpc = (struct gpc_reg *)GPC_BASE_ADDR;
 619
 620                         writel(0x1, &pgc_core2->pgcr);
 621                         writel(0x1, &pgc_core3->pgcr);
 622                         if (is_imx8mms() || is_imx8mmsl() || is_imx8mns() || is_imx8mnsl() || is_imx8mnus()) {
 623                                 writel(0x1, &pgc_core1->pgcr);
 624                                 writel(0xE, &gpc->cpu_pgc_dn_trg);
 625                         } else {
 626                                 writel(0xC, &gpc->cpu_pgc_dn_trg);
 627                         }
 628                 }
 629         }
 630
 631         if (is_imx8mq()) {
 632                 clock_enable(CCGR_OCOTP, 1);
 633                 if (readl(&ocotp->ctrl) & 0x200)
 634                         writel(0x200, &ocotp->ctrl_clr);
 635         }
 636
 637         imx8m_setup_snvs();
 638
 639         imx8m_setup_csu_tzasc();
 640
 641         return 0;
 642 }
 643
 644 #if defined(CONFIG_IMX8MN) || defined(CONFIG_IMX8MP)
 645 struct rom_api *g_rom_api = (struct rom_api *)0x980;
 646 #endif
 647
 648 #if defined(CONFIG_IMX8M)
 649 #include <spl.h>
 650 int spl_mmc_emmc_boot_partition(struct mmc *mmc)
 651 {
 652         u32 *rom_log_addr = (u32 *)0x9e0;
 653         u32 *rom_log;
 654         u8 event_id;
 655         int i, part;
 656
 657         part = default_spl_mmc_emmc_boot_partition(mmc);
 658
 659         /* If the ROM event log pointer is not valid. */
 660         if (*rom_log_addr < 0x900000 || *rom_log_addr >= 0xb00000 ||
 661             *rom_log_addr & 0x3)
 662                 return part;
 663
 664         /* Parse the ROM event ID version 2 log */
 665         rom_log = (u32 *)(uintptr_t)(*rom_log_addr);
 666         for (i = 0; i < 128; i++) {
 667                 event_id = rom_log[i] >> 24;
 668                 switch (event_id) {
 669                 case 0x00: /* End of list */
 670                         return part;
 671                 /* Log entries with 1 parameter, skip 1 */
 672                 case 0x80: /* Start to perform the device initialization */
 673                 case 0x81: /* The boot device initialization completes */
 674                 case 0x82: /* Starts to execute boot device driver pre-config */
 675                 case 0x8f: /* The boot device initialization fails */
 676                 case 0x90: /* Start to read data from boot device */
 677                 case 0x91: /* Reading data from boot device completes */
 678                 case 0x9f: /* Reading data from boot device fails */
 679                         i += 1;
 680                         continue;
 681                 /* Log entries with 2 parameters, skip 2 */
 682                 case 0xa0: /* Image authentication result */
 683                 case 0xc0: /* Jump to the boot image soon */
 684                         i += 2;
 685                         continue;
 686                 /* Boot from the secondary boot image */
 687                 case 0x51:
 688                         /*
 689                          * Swap the eMMC boot partitions in case there was a
 690                          * fallback event (i.e. primary image was corrupted
 691                          * and that corruption was recognized by the BootROM),
 692                          * so the SPL loads the rest of the U-Boot from the
 693                          * correct eMMC boot partition, since the BootROM
 694                          * leaves the boot partition set to the corrupted one.
 695                          */
 696                         if (part == 1)
 697                                 part = 2;
 698                         else if (part == 2)
 699                                 part = 1;
 700                         continue;
 701                 default:
 702                         continue;
 703                 }
 704         }
 705
 706         return part;
 707 }
 708 #endif
 709
 710 bool is_usb_boot(void)
 711 {
 712         return get_boot_device() == USB_BOOT;
 713 }
 714
 715 #ifdef CONFIG_OF_SYSTEM_SETUP
 716 bool check_fdt_new_path(void *blob)
 717 {
 718         const char *soc_path = "/soc@0";
 719         int nodeoff;
 720
 721         nodeoff = fdt_path_offset(blob, soc_path);
 722         if (nodeoff < 0)
 723                 return false;
 724
 725         return true;
 726 }
 727
 728 static int disable_fdt_nodes(void *blob, const char *const nodes_path[], int size_array)
 729 {
 730         int i = 0;
 731         int rc;
 732         int nodeoff;
 733         const char *status = "disabled";
 734
 735         for (i = 0; i < size_array; i++) {
 736                 nodeoff = fdt_path_offset(blob, nodes_path[i]);
 737                 if (nodeoff < 0)
 738                         continue; /* Not found, skip it */
 739
 740                 debug("Found %s node\n", nodes_path[i]);
 741
 742 add_status:
 743                 rc = fdt_setprop(blob, nodeoff, "status", status, strlen(status) + 1);
 744                 if (rc) {
 745                         if (rc == -FDT_ERR_NOSPACE) {
 746                                 rc = fdt_increase_size(blob, 512);
 747                                 if (!rc)
 748                                         goto add_status;
 749                         }
 750                         printf("Unable to update property %s:%s, err=%s\n",
 751                                nodes_path[i], "status", fdt_strerror(rc));
 752                 } else {
 753                         printf("Modify %s:%s disabled\n",
 754                                nodes_path[i], "status");
 755                 }
 756         }
 757
 758         return 0;
 759 }
 760
 761 #ifdef CONFIG_IMX8MQ
 762 bool check_dcss_fused(void)
 763 {
 764         struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
 765         struct fuse_bank *bank = &ocotp->bank[1];
 766         struct fuse_bank1_regs *fuse =
 767                 (struct fuse_bank1_regs *)bank->fuse_regs;
 768         u32 value = readl(&fuse->tester4);
 769
 770         if (value & 0x4000000)
 771                 return true;
 772
 773         return false;
 774 }
 775
 776 static int disable_mipi_dsi_nodes(void *blob)
 777 {
 778         static const char * const nodes_path[] = {
 779                 "/mipi_dsi@30A00000",
 780                 "/mipi_dsi_bridge@30A00000",
 781                 "/dsi_phy@30A00300",
 782                 "/soc@0/bus@30800000/mipi_dsi@30a00000",
 783                 "/soc@0/bus@30800000/dphy@30a00300",
 784                 "/soc@0/bus@30800000/mipi-dsi@30a00000",
 785         };
 786
 787         return disable_fdt_nodes(blob, nodes_path, ARRAY_SIZE(nodes_path));
 788 }
 789
 790 static int disable_dcss_nodes(void *blob)
 791 {
 792         static const char * const nodes_path[] = {
 793                 "/dcss@0x32e00000",
 794                 "/dcss@32e00000",
 795                 "/hdmi@32c00000",
 796                 "/hdmi_cec@32c33800",
 797                 "/hdmi_drm@32c00000",
 798                 "/display-subsystem",
 799                 "/sound-hdmi",
 800                 "/sound-hdmi-arc",
 801                 "/soc@0/bus@32c00000/display-controller@32e00000",
 802                 "/soc@0/bus@32c00000/hdmi@32c00000",
 803         };
 804
 805         return disable_fdt_nodes(blob, nodes_path, ARRAY_SIZE(nodes_path));
 806 }
 807
 808 static int check_mipi_dsi_nodes(void *blob)
 809 {
 810         static const char * const lcdif_path[] = {
 811                 "/lcdif@30320000",
 812                 "/soc@0/bus@30000000/lcdif@30320000",
 813                 "/soc@0/bus@30000000/lcd-controller@30320000"
 814         };
 815         static const char * const mipi_dsi_path[] = {
 816                 "/mipi_dsi@30A00000",
 817                 "/soc@0/bus@30800000/mipi_dsi@30a00000"
 818         };
 819         static const char * const lcdif_ep_path[] = {
 820                 "/lcdif@30320000/port@0/mipi-dsi-endpoint",
 821                 "/soc@0/bus@30000000/lcdif@30320000/port@0/endpoint",
 822                 "/soc@0/bus@30000000/lcd-controller@30320000/port@0/endpoint"
 823         };
 824         static const char * const mipi_dsi_ep_path[] = {
 825                 "/mipi_dsi@30A00000/port@1/endpoint",
 826                 "/soc@0/bus@30800000/mipi_dsi@30a00000/ports/port@0/endpoint",
 827                 "/soc@0/bus@30800000/mipi-dsi@30a00000/ports/port@0/endpoint@0"
 828         };
 829
 830         int lookup_node;
 831         int nodeoff;
 832         bool new_path = check_fdt_new_path(blob);
 833         int i = new_path ? 1 : 0;
 834
 835         nodeoff = fdt_path_offset(blob, lcdif_path[i]);
 836         if (nodeoff < 0 || !fdtdec_get_is_enabled(blob, nodeoff)) {
 837                 /*
 838                  * If can't find lcdif node or lcdif node is disabled,
 839                  * then disable all mipi dsi, since they only can input
 840                  * from DCSS
 841                  */
 842                 return disable_mipi_dsi_nodes(blob);
 843         }
 844
 845         nodeoff = fdt_path_offset(blob, mipi_dsi_path[i]);
 846         if (nodeoff < 0 || !fdtdec_get_is_enabled(blob, nodeoff))
 847                 return 0;
 848
 849         nodeoff = fdt_path_offset(blob, lcdif_ep_path[i]);
 850         if (nodeoff < 0) {
 851                 /*
 852                  * If can't find lcdif endpoint, then disable all mipi dsi,
 853                  * since they only can input from DCSS
 854                  */
 855                 return disable_mipi_dsi_nodes(blob);
 856         }
 857
 858         lookup_node = fdtdec_lookup_phandle(blob, nodeoff, "remote-endpoint");
 859         nodeoff = fdt_path_offset(blob, mipi_dsi_ep_path[i]);
 860
 861         if (nodeoff > 0 && nodeoff == lookup_node)
 862                 return 0;
 863
 864         return disable_mipi_dsi_nodes(blob);
 865 }
 866 #endif
 867
 868 int disable_vpu_nodes(void *blob)
 869 {
 870         static const char * const nodes_path_8mq[] = {
 871                 "/vpu@38300000",
 872                 "/soc@0/vpu@38300000"
 873         };
 874
 875         static const char * const nodes_path_8mm[] = {
 876                 "/vpu_g1@38300000",
 877                 "/vpu_g2@38310000",
 878                 "/vpu_h1@38320000"
 879         };
 880
 881         static const char * const nodes_path_8mp[] = {
 882                 "/vpu_g1@38300000",
 883                 "/vpu_g2@38310000",
 884                 "/vpu_vc8000e@38320000"
 885         };
 886
 887         if (is_imx8mq())
 888                 return disable_fdt_nodes(blob, nodes_path_8mq, ARRAY_SIZE(nodes_path_8mq));
 889         else if (is_imx8mm())
 890                 return disable_fdt_nodes(blob, nodes_path_8mm, ARRAY_SIZE(nodes_path_8mm));
 891         else if (is_imx8mp())
 892                 return disable_fdt_nodes(blob, nodes_path_8mp, ARRAY_SIZE(nodes_path_8mp));
 893         else
 894                 return -EPERM;
 895 }
 896
 897 #ifdef CONFIG_IMX8MN_LOW_DRIVE_MODE
 898 static int low_drive_gpu_freq(void *blob)
 899 {
 900         static const char *nodes_path_8mn[] = {
 901                 "/gpu@38000000",
 902                 "/soc@0/gpu@38000000"
 903         };
 904
 905         int nodeoff, cnt, i;
 906         u32 assignedclks[7];
 907
 908         nodeoff = fdt_path_offset(blob, nodes_path_8mn[0]);
 909         if (nodeoff < 0)
 910                 return nodeoff;
 911
 912         cnt = fdtdec_get_int_array_count(blob, nodeoff, "assigned-clock-rates", assignedclks, 7);
 913         if (cnt < 0)
 914                 return cnt;
 915
 916         if (cnt != 7)
 917                 printf("Warning: %s, assigned-clock-rates count %d\n", nodes_path_8mn[0], cnt);
 918         if (cnt < 2)
 919                 return -1;
 920
 921         assignedclks[cnt - 1] = 200000000;
 922         assignedclks[cnt - 2] = 200000000;
 923
 924         for (i = 0; i < cnt; i++) {
 925                 debug("<%u>, ", assignedclks[i]);
 926                 assignedclks[i] = cpu_to_fdt32(assignedclks[i]);
 927         }
 928         debug("\n");
 929
 930         return fdt_setprop(blob, nodeoff, "assigned-clock-rates", &assignedclks, sizeof(assignedclks));
 931 }
 932 #endif
 933
 934 static bool check_remote_endpoint(void *blob, const char *ep1, const char *ep2)
 935 {
 936         int lookup_node;
 937         int nodeoff;
 938
 939         nodeoff = fdt_path_offset(blob, ep1);
 940         if (nodeoff) {
 941                 lookup_node = fdtdec_lookup_phandle(blob, nodeoff, "remote-endpoint");
 942                 nodeoff = fdt_path_offset(blob, ep2);
 943
 944                 if (nodeoff > 0 && nodeoff == lookup_node)
 945                         return true;
 946         }
 947
 948         return false;
 949 }
 950
 951 int disable_dsi_lcdif_nodes(void *blob)
 952 {
 953         int ret;
 954
 955         static const char * const dsi_path_8mp[] = {
 956                 "/soc@0/bus@32c00000/mipi_dsi@32e60000"
 957         };
 958
 959         static const char * const lcdif_path_8mp[] = {
 960                 "/soc@0/bus@32c00000/lcd-controller@32e80000"
 961         };
 962
 963         static const char * const lcdif_ep_path_8mp[] = {
 964                 "/soc@0/bus@32c00000/lcd-controller@32e80000/port@0/endpoint"
 965         };
 966         static const char * const dsi_ep_path_8mp[] = {
 967                 "/soc@0/bus@32c00000/mipi_dsi@32e60000/port@0/endpoint"
 968         };
 969
 970         ret = disable_fdt_nodes(blob, dsi_path_8mp, ARRAY_SIZE(dsi_path_8mp));
 971         if (ret)
 972                 return ret;
 973
 974         if (check_remote_endpoint(blob, dsi_ep_path_8mp[0], lcdif_ep_path_8mp[0])) {
 975                 /* Disable lcdif node */
 976                 return disable_fdt_nodes(blob, lcdif_path_8mp, ARRAY_SIZE(lcdif_path_8mp));
 977         }
 978
 979         return 0;
 980 }
 981
 982 int disable_lvds_lcdif_nodes(void *blob)
 983 {
 984         int ret, i;
 985
 986         static const char * const ldb_path_8mp[] = {
 987                 "/soc@0/bus@32c00000/ldb@32ec005c",
 988                 "/soc@0/bus@32c00000/phy@32ec0128"
 989         };
 990
 991         static const char * const lcdif_path_8mp[] = {
 992                 "/soc@0/bus@32c00000/lcd-controller@32e90000"
 993         };
 994
 995         static const char * const lcdif_ep_path_8mp[] = {
 996                 "/soc@0/bus@32c00000/lcd-controller@32e90000/port@0/endpoint@0",
 997                 "/soc@0/bus@32c00000/lcd-controller@32e90000/port@0/endpoint@1"
 998         };
 999         static const char * const ldb_ep_path_8mp[] = {
1000                 "/soc@0/bus@32c00000/ldb@32ec005c/lvds-channel@0/port@0/endpoint",
1001                 "/soc@0/bus@32c00000/ldb@32ec005c/lvds-channel@1/port@0/endpoint"
1002         };
1003
1004         ret = disable_fdt_nodes(blob, ldb_path_8mp, ARRAY_SIZE(ldb_path_8mp));
1005         if (ret)
1006                 return ret;
1007
1008         for (i = 0; i < ARRAY_SIZE(ldb_ep_path_8mp); i++) {
1009                 if (check_remote_endpoint(blob, ldb_ep_path_8mp[i], lcdif_ep_path_8mp[i])) {
1010                         /* Disable lcdif node */
1011                         return disable_fdt_nodes(blob, lcdif_path_8mp, ARRAY_SIZE(lcdif_path_8mp));
1012                 }
1013         }
1014
1015         return 0;
1016 }
1017
1018 int disable_gpu_nodes(void *blob)
1019 {
1020         static const char * const nodes_path_8mn[] = {
1021                 "/gpu@38000000",
1022                 "/soc@/gpu@38000000"
1023         };
1024
1025         static const char * const nodes_path_8mp[] = {
1026                 "/gpu3d@38000000",
1027                 "/gpu2d@38008000"
1028         };
1029
1030         if (is_imx8mp())
1031                 return disable_fdt_nodes(blob, nodes_path_8mp, ARRAY_SIZE(nodes_path_8mp));
1032         else
1033                 return disable_fdt_nodes(blob, nodes_path_8mn, ARRAY_SIZE(nodes_path_8mn));
1034 }
1035
1036 int disable_npu_nodes(void *blob)
1037 {
1038         static const char * const nodes_path_8mp[] = {
1039                 "/vipsi@38500000"
1040         };
1041
1042         return disable_fdt_nodes(blob, nodes_path_8mp, ARRAY_SIZE(nodes_path_8mp));
1043 }
1044
1045 int disable_isp_nodes(void *blob)
1046 {
1047         static const char * const nodes_path_8mp[] = {
1048                 "/soc@0/bus@32c00000/camera/isp@32e10000",
1049                 "/soc@0/bus@32c00000/camera/isp@32e20000"
1050         };
1051
1052         return disable_fdt_nodes(blob, nodes_path_8mp, ARRAY_SIZE(nodes_path_8mp));
1053 }
1054
1055 int disable_dsp_nodes(void *blob)
1056 {
1057         static const char * const nodes_path_8mp[] = {
1058                 "/dsp@3b6e8000"
1059         };
1060
1061         return disable_fdt_nodes(blob, nodes_path_8mp, ARRAY_SIZE(nodes_path_8mp));
1062 }
1063
1064 static void disable_thermal_cpu_nodes(void *blob, u32 disabled_cores)
1065 {
1066         static const char * const thermal_path[] = {
1067                 "/thermal-zones/cpu-thermal/cooling-maps/map0"
1068         };
1069
1070         int nodeoff, cnt, i, ret, j;
1071         u32 cooling_dev[12];
1072
1073         for (i = 0; i < ARRAY_SIZE(thermal_path); i++) {
1074                 nodeoff = fdt_path_offset(blob, thermal_path[i]);
1075                 if (nodeoff < 0)
1076                         continue; /* Not found, skip it */
1077
1078                 cnt = fdtdec_get_int_array_count(blob, nodeoff, "cooling-device", cooling_dev, 12);
1079                 if (cnt < 0)
1080                         continue;
1081
1082                 if (cnt != 12)
1083                         printf("Warning: %s, cooling-device count %d\n", thermal_path[i], cnt);
1084
1085                 for (j = 0; j < cnt; j++)
1086                         cooling_dev[j] = cpu_to_fdt32(cooling_dev[j]);
1087
1088                 ret = fdt_setprop(blob, nodeoff, "cooling-device", &cooling_dev,
1089                                   sizeof(u32) * (12 - disabled_cores * 3));
1090                 if (ret < 0) {
1091                         printf("Warning: %s, cooling-device setprop failed %d\n",
1092                                thermal_path[i], ret);
1093                         continue;
1094                 }
1095
1096                 printf("Update node %s, cooling-device prop\n", thermal_path[i]);
1097         }
1098 }
1099
1100 static void disable_pmu_cpu_nodes(void *blob, u32 disabled_cores)
1101 {
1102         static const char * const pmu_path[] = {
1103                 "/pmu"
1104         };
1105
1106         int nodeoff, cnt, i, ret, j;
1107         u32 irq_affinity[4];
1108
1109         for (i = 0; i < ARRAY_SIZE(pmu_path); i++) {
1110                 nodeoff = fdt_path_offset(blob, pmu_path[i]);
1111                 if (nodeoff < 0)
1112                         continue; /* Not found, skip it */
1113
1114                 cnt = fdtdec_get_int_array_count(blob, nodeoff, "interrupt-affinity",
1115                                                  irq_affinity, 4);
1116                 if (cnt < 0)
1117                         continue;
1118
1119                 if (cnt != 4)
1120                         printf("Warning: %s, interrupt-affinity count %d\n", pmu_path[i], cnt);
1121
1122                 for (j = 0; j < cnt; j++)
1123                         irq_affinity[j] = cpu_to_fdt32(irq_affinity[j]);
1124
1125                 ret = fdt_setprop(blob, nodeoff, "interrupt-affinity", &irq_affinity,
1126                                  sizeof(u32) * (4 - disabled_cores));
1127                 if (ret < 0) {
1128                         printf("Warning: %s, interrupt-affinity setprop failed %d\n",
1129                                pmu_path[i], ret);
1130                         continue;
1131                 }
1132
1133                 printf("Update node %s, interrupt-affinity prop\n", pmu_path[i]);
1134         }
1135 }
1136
1137 static int disable_cpu_nodes(void *blob, u32 disabled_cores)
1138 {
1139         static const char * const nodes_path[] = {
1140                 "/cpus/cpu@1",
1141                 "/cpus/cpu@2",
1142                 "/cpus/cpu@3",
1143         };
1144         u32 i = 0;
1145         int rc;
1146         int nodeoff;
1147
1148         if (disabled_cores > 3)
1149                 return -EINVAL;
1150
1151         i = 3 - disabled_cores;
1152
1153         for (; i < 3; i++) {
1154                 nodeoff = fdt_path_offset(blob, nodes_path[i]);
1155                 if (nodeoff < 0)
1156                         continue; /* Not found, skip it */
1157
1158                 debug("Found %s node\n", nodes_path[i]);
1159
1160                 rc = fdt_del_node(blob, nodeoff);
1161                 if (rc < 0) {
1162                         printf("Unable to delete node %s, err=%s\n",
1163                                nodes_path[i], fdt_strerror(rc));
1164                 } else {
1165                         printf("Delete node %s\n", nodes_path[i]);
1166                 }
1167         }
1168
1169         disable_thermal_cpu_nodes(blob, disabled_cores);
1170         disable_pmu_cpu_nodes(blob, disabled_cores);
1171
1172         return 0;
1173 }
1174
1175 static int cleanup_nodes_for_efi(void *blob)
1176 {
1177         static const char * const path[][2] = {
1178                 { "/soc@0/bus@32c00000/usb@32e40000", "extcon" },
1179                 { "/soc@0/bus@32c00000/usb@32e50000", "extcon" },
1180                 { "/soc@0/bus@30800000/ethernet@30be0000", "phy-reset-gpios" },
1181                 { "/soc@0/bus@30800000/ethernet@30bf0000", "phy-reset-gpios" }
1182         };
1183         int nodeoff, i, rc;
1184
1185         for (i = 0; i < ARRAY_SIZE(path); i++) {
1186                 nodeoff = fdt_path_offset(blob, path[i][0]);
1187                 if (nodeoff < 0)
1188                         continue; /* Not found, skip it */
1189                 debug("Found %s node\n", path[i][0]);
1190
1191                 rc = fdt_delprop(blob, nodeoff, path[i][1]);
1192                 if (rc == -FDT_ERR_NOTFOUND)
1193                         continue;
1194                 if (rc) {
1195                         printf("Unable to update property %s:%s, err=%s\n",
1196                                path[i][0], path[i][1], fdt_strerror(rc));
1197                         return rc;
1198                 }
1199
1200                 printf("Remove %s:%s\n", path[i][0], path[i][1]);
1201         }
1202
1203         return 0;
1204 }
1205
1206 static int fixup_thermal_trips(void *blob, const char *name)
1207 {
1208         int minc, maxc;
1209         int node, trip;
1210
1211         node = fdt_path_offset(blob, "/thermal-zones");
1212         if (node < 0)
1213                 return node;
1214
1215         node = fdt_subnode_offset(blob, node, name);
1216         if (node < 0)
1217                 return node;
1218
1219         node = fdt_subnode_offset(blob, node, "trips");
1220         if (node < 0)
1221                 return node;
1222
1223         get_cpu_temp_grade(&minc, &maxc);
1224
1225         fdt_for_each_subnode(trip, blob, node) {
1226                 const char *type;
1227                 int temp, ret;
1228
1229                 type = fdt_getprop(blob, trip, "type", NULL);
1230                 if (!type)
1231                         continue;
1232
1233                 temp = 0;
1234                 if (!strcmp(type, "critical"))
1235                         temp = 1000 * maxc;
1236                 else if (!strcmp(type, "passive"))
1237                         temp = 1000 * (maxc - 10);
1238                 if (temp) {
1239                         ret = fdt_setprop_u32(blob, trip, "temperature", temp);
1240                         if (ret)
1241                                 return ret;
1242                 }
1243         }
1244
1245         return 0;
1246 }
1247
1248 int ft_system_setup(void *blob, struct bd_info *bd)
1249 {
1250 #ifdef CONFIG_IMX8MQ
1251         int i = 0;
1252         int rc;
1253         int nodeoff;
1254
1255         if (get_boot_device() == USB_BOOT) {
1256                 disable_dcss_nodes(blob);
1257
1258                 bool new_path = check_fdt_new_path(blob);
1259                 int v = new_path ? 1 : 0;
1260                 static const char * const usb_dwc3_path[] = {
1261                         "/usb@38100000/dwc3",
1262                         "/soc@0/usb@38100000"
1263                 };
1264
1265                 nodeoff = fdt_path_offset(blob, usb_dwc3_path[v]);
1266                 if (nodeoff >= 0) {
1267                         const char *speed = "high-speed";
1268
1269                         debug("Found %s node\n", usb_dwc3_path[v]);
1270
1271 usb_modify_speed:
1272
1273                         rc = fdt_setprop(blob, nodeoff, "maximum-speed", speed, strlen(speed) + 1);
1274                         if (rc) {
1275                                 if (rc == -FDT_ERR_NOSPACE) {
1276                                         rc = fdt_increase_size(blob, 512);
1277                                         if (!rc)
1278                                                 goto usb_modify_speed;
1279                                 }
1280                                 printf("Unable to set property %s:%s, err=%s\n",
1281                                        usb_dwc3_path[v], "maximum-speed", fdt_strerror(rc));
1282                         } else {
1283                                 printf("Modify %s:%s = %s\n",
1284                                        usb_dwc3_path[v], "maximum-speed", speed);
1285                         }
1286                 } else {
1287                         printf("Can't found %s node\n", usb_dwc3_path[v]);
1288                 }
1289         }
1290
1291         /* Disable the CPU idle for A0 chip since the HW does not support it */
1292         if (is_soc_rev(CHIP_REV_1_0)) {
1293                 static const char * const nodes_path[] = {
1294                         "/cpus/cpu@0",
1295                         "/cpus/cpu@1",
1296                         "/cpus/cpu@2",
1297                         "/cpus/cpu@3",
1298                 };
1299
1300                 for (i = 0; i < ARRAY_SIZE(nodes_path); i++) {
1301                         nodeoff = fdt_path_offset(blob, nodes_path[i]);
1302                         if (nodeoff < 0)
1303                                 continue; /* Not found, skip it */
1304
1305                         debug("Found %s node\n", nodes_path[i]);
1306
1307                         rc = fdt_delprop(blob, nodeoff, "cpu-idle-states");
1308                         if (rc == -FDT_ERR_NOTFOUND)
1309                                 continue;
1310                         if (rc) {
1311                                 printf("Unable to update property %s:%s, err=%s\n",
1312                                        nodes_path[i], "status", fdt_strerror(rc));
1313                                 return rc;
1314                         }
1315
1316                         debug("Remove %s:%s\n", nodes_path[i],
1317                                "cpu-idle-states");
1318                 }
1319         }
1320
1321         if (is_imx8mql()) {
1322                 disable_vpu_nodes(blob);
1323                 if (check_dcss_fused()) {
1324                         printf("DCSS is fused\n");
1325                         disable_dcss_nodes(blob);
1326                         check_mipi_dsi_nodes(blob);
1327                 }
1328         }
1329
1330         if (is_imx8md())
1331                 disable_cpu_nodes(blob, 2);
1332
1333 #elif defined(CONFIG_IMX8MM)
1334         if (is_imx8mml() || is_imx8mmdl() ||  is_imx8mmsl())
1335                 disable_vpu_nodes(blob);
1336
1337         if (is_imx8mmd() || is_imx8mmdl())
1338                 disable_cpu_nodes(blob, 2);
1339         else if (is_imx8mms() || is_imx8mmsl())
1340                 disable_cpu_nodes(blob, 3);
1341
1342 #elif defined(CONFIG_IMX8MN)
1343         if (is_imx8mnl() || is_imx8mndl() ||  is_imx8mnsl())
1344                 disable_gpu_nodes(blob);
1345 #ifdef CONFIG_IMX8MN_LOW_DRIVE_MODE
1346         else {
1347                 int ldm_gpu = low_drive_gpu_freq(blob);
1348
1349                 if (ldm_gpu < 0)
1350                         printf("Update GPU node assigned-clock-rates failed\n");
1351                 else
1352                         printf("Update GPU node assigned-clock-rates ok\n");
1353         }
1354 #endif
1355
1356         if (is_imx8mnd() || is_imx8mndl() || is_imx8mnud())
1357                 disable_cpu_nodes(blob, 2);
1358         else if (is_imx8mns() || is_imx8mnsl() || is_imx8mnus())
1359                 disable_cpu_nodes(blob, 3);
1360
1361 #elif defined(CONFIG_IMX8MP)
1362         if (is_imx8mpul()) {
1363                 /* Disable GPU */
1364                 disable_gpu_nodes(blob);
1365
1366                 /* Disable DSI */
1367                 disable_dsi_lcdif_nodes(blob);
1368
1369                 /* Disable LVDS */
1370                 disable_lvds_lcdif_nodes(blob);
1371         }
1372
1373         if (is_imx8mpul() || is_imx8mpl())
1374                 disable_vpu_nodes(blob);
1375
1376         if (is_imx8mpul() || is_imx8mpl() || is_imx8mp6())
1377                 disable_npu_nodes(blob);
1378
1379         if (is_imx8mpul() || is_imx8mpl())
1380                 disable_isp_nodes(blob);
1381
1382         if (is_imx8mpul() || is_imx8mpl() || is_imx8mp6())
1383                 disable_dsp_nodes(blob);
1384
1385         if (is_imx8mpd())
1386                 disable_cpu_nodes(blob, 2);
1387 #endif
1388
1389         cleanup_nodes_for_efi(blob);
1390
1391         if (fixup_thermal_trips(blob, "cpu-thermal"))
1392                 printf("Failed to update cpu-thermal trip(s)");
1393         if (IS_ENABLED(CONFIG_IMX8MP) &&
1394             fixup_thermal_trips(blob, "soc-thermal"))
1395                 printf("Failed to update soc-thermal trip(s)");
1396
1397         return 0;
1398 }
1399 #endif
1400
1401 #if !CONFIG_IS_ENABLED(SYSRESET)
1402 void reset_cpu(void)
1403 {
1404         struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
1405
1406         /* Clear WDA to trigger WDOG_B immediately */
1407         writew((SET_WCR_WT(1) | WCR_WDT | WCR_WDE | WCR_SRS), &wdog->wcr);
1408
1409         while (1) {
1410                 /*
1411                  * spin for .5 seconds before reset
1412                  */
1413         }
1414 }
1415 #endif
1416
1417 #if defined(CONFIG_ARCH_MISC_INIT)
1418 int arch_misc_init(void)
1419 {
1420         if (IS_ENABLED(CONFIG_FSL_CAAM)) {
1421                 struct udevice *dev;
1422                 int ret;
1423
1424                 ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
1425                 if (ret)
1426                         printf("Failed to initialize caam_jr: %d\n", ret);
1427         }
1428
1429         return 0;
1430 }
1431 #endif
1432
1433 #if defined(CONFIG_SPL_BUILD)
1434 #if defined(CONFIG_IMX8MQ) || defined(CONFIG_IMX8MM) || defined(CONFIG_IMX8MN)
1435 bool serror_need_skip = true;
1436
1437 void do_error(struct pt_regs *pt_regs)
1438 {
1439         /*
1440          * If stack is still in ROM reserved OCRAM not switch to SPL,
1441          * it is the ROM SError
1442          */
1443         ulong sp;
1444
1445         asm volatile("mov %0, sp" : "=r"(sp) : );
1446
1447         if (serror_need_skip && sp < 0x910000 && sp >= 0x900000) {
1448                 /* Check for ERR050342, imx8mq HDCP enabled parts */
1449                 if (is_imx8mq() && !(readl(OCOTP_BASE_ADDR + 0x450) & 0x08000000)) {
1450                         serror_need_skip = false;
1451                         return; /* Do nothing skip the SError in ROM */
1452                 }
1453
1454                 /* Check for ERR050350, field return mode for imx8mq, mm and mn */
1455                 if (readl(OCOTP_BASE_ADDR + 0x630) & 0x1) {
1456                         serror_need_skip = false;
1457                         return; /* Do nothing skip the SError in ROM */
1458                 }
1459         }
1460
1461         efi_restore_gd();
1462         printf("\"Error\" handler, esr 0x%08lx\n", pt_regs->esr);
1463         show_regs(pt_regs);
1464         panic("Resetting CPU ...\n");
1465 }
1466 #endif
1467 #endif
1468
1469 #if defined(CONFIG_IMX8MN) || defined(CONFIG_IMX8MP)
1470 enum env_location arch_env_get_location(enum env_operation op, int prio)
1471 {
1472         enum boot_device dev = get_boot_device();
1473
1474         if (prio)
1475                 return ENVL_UNKNOWN;
1476
1477         switch (dev) {
1478         case USB_BOOT:
1479                 if (IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH))
1480                         return ENVL_SPI_FLASH;
1481                 if (IS_ENABLED(CONFIG_ENV_IS_IN_NAND))
1482                         return ENVL_NAND;
1483                 if (IS_ENABLED(CONFIG_ENV_IS_IN_MMC))
1484                         return ENVL_MMC;
1485                 if (IS_ENABLED(CONFIG_ENV_IS_NOWHERE))
1486                         return ENVL_NOWHERE;
1487                 return ENVL_UNKNOWN;
1488         case QSPI_BOOT:
1489         case SPI_NOR_BOOT:
1490                 if (IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH))
1491                         return ENVL_SPI_FLASH;
1492                 return ENVL_NOWHERE;
1493         case NAND_BOOT:
1494                 if (IS_ENABLED(CONFIG_ENV_IS_IN_NAND))
1495                         return ENVL_NAND;
1496                 return ENVL_NOWHERE;
1497         case SD1_BOOT:
1498         case SD2_BOOT:
1499         case SD3_BOOT:
1500         case MMC1_BOOT:
1501         case MMC2_BOOT:
1502         case MMC3_BOOT:
1503                 if (IS_ENABLED(CONFIG_ENV_IS_IN_MMC))
1504                         return ENVL_MMC;
1505                 else if (IS_ENABLED(CONFIG_ENV_IS_IN_EXT4))
1506                         return ENVL_EXT4;
1507                 else if (IS_ENABLED(CONFIG_ENV_IS_IN_FAT))
1508                         return ENVL_FAT;
1509                 return ENVL_NOWHERE;
1510         default:
1511                 return ENVL_NOWHERE;
1512         }
1513 }
1514
1515 #endif
1516
1517 #ifdef CONFIG_IMX_BOOTAUX
1518 const struct rproc_att hostmap[] = {
1519         /* aux core , host core,  size */
1520         { 0x00000000, 0x007e0000, 0x00020000 },
1521         /* OCRAM_S */
1522         { 0x00180000, 0x00180000, 0x00008000 },
1523         /* OCRAM */
1524         { 0x00900000, 0x00900000, 0x00020000 },
1525         /* OCRAM */
1526         { 0x00920000, 0x00920000, 0x00020000 },
1527         /* QSPI Code - alias */
1528         { 0x08000000, 0x08000000, 0x08000000 },
1529         /* DDR (Code) - alias */
1530         { 0x10000000, 0x80000000, 0x0FFE0000 },
1531         /* TCML */
1532         { 0x1FFE0000, 0x007E0000, 0x00040000 },
1533         /* OCRAM_S */
1534         { 0x20180000, 0x00180000, 0x00008000 },
1535         /* OCRAM */
1536         { 0x20200000, 0x00900000, 0x00040000 },
1537         /* DDR (Data) */
1538         { 0x40000000, 0x40000000, 0x80000000 },
1539         { /* sentinel */ }
1540 };
1541
1542 const struct rproc_att *imx_bootaux_get_hostmap(void)
1543 {
1544         return hostmap;
1545 }
1546 #endif