1 // SPDX-License-Identifier: GPL-2.0+
14 #include <asm/arch/pwm.h>
15 #include <asm/arch/gpio.h>
16 #include <power/regulator.h>
18 DECLARE_GLOBAL_DATA_PTR;
20 #define OSC_24MHZ 24000000
22 struct sunxi_pwm_priv {
23 struct sunxi_pwm *regs;
28 static const u32 prescaler_table[] = {
47 static int sunxi_pwm_config_pinmux(void)
49 #ifdef CONFIG_MACH_SUN50I
50 sunxi_gpio_set_cfgpin(SUNXI_GPD(22), SUNXI_GPD_PWM);
55 static int sunxi_pwm_set_invert(struct udevice *dev, uint channel,
58 struct sunxi_pwm_priv *priv = dev_get_priv(dev);
60 debug("%s: polarity=%u\n", __func__, polarity);
61 priv->invert = polarity;
66 static int sunxi_pwm_set_config(struct udevice *dev, uint channel,
67 uint period_ns, uint duty_ns)
69 struct sunxi_pwm_priv *priv = dev_get_priv(dev);
70 struct sunxi_pwm *regs = priv->regs;
71 int best_prescaler = 0;
72 u32 v, best_period = 0, duty;
73 u64 best_scaled_freq = 0;
74 const u32 nsecs_per_sec = 1000000000U;
76 debug("%s: period_ns=%u, duty_ns=%u\n", __func__, period_ns, duty_ns);
78 for (int prescaler = 0; prescaler <= SUNXI_PWM_CTRL_PRESCALE0_MASK;
82 if (!prescaler_table[prescaler])
84 scaled_freq = lldiv(OSC_24MHZ, prescaler_table[prescaler]);
85 period = lldiv(scaled_freq * period_ns, nsecs_per_sec);
86 if ((period - 1 <= SUNXI_PWM_CH0_PERIOD_MAX) &&
87 best_period < period) {
89 best_scaled_freq = scaled_freq;
90 best_prescaler = prescaler;
94 if (best_period - 1 > SUNXI_PWM_CH0_PERIOD_MAX) {
95 debug("%s: failed to find prescaler value\n", __func__);
99 duty = lldiv(best_scaled_freq * duty_ns, nsecs_per_sec);
101 if (priv->prescaler != best_prescaler) {
102 /* Mask clock to update prescaler */
103 v = readl(®s->ctrl);
104 v &= ~SUNXI_PWM_CTRL_CLK_GATE;
105 writel(v, ®s->ctrl);
106 v &= ~SUNXI_PWM_CTRL_PRESCALE0_MASK;
107 v |= (best_prescaler & SUNXI_PWM_CTRL_PRESCALE0_MASK);
108 writel(v, ®s->ctrl);
109 v |= SUNXI_PWM_CTRL_CLK_GATE;
110 writel(v, ®s->ctrl);
111 priv->prescaler = best_prescaler;
114 writel(SUNXI_PWM_CH0_PERIOD_PRD(best_period) |
115 SUNXI_PWM_CH0_PERIOD_DUTY(duty), ®s->ch0_period);
117 debug("%s: prescaler: %d, period: %d, duty: %d\n",
118 __func__, priv->prescaler,
124 static int sunxi_pwm_set_enable(struct udevice *dev, uint channel, bool enable)
126 struct sunxi_pwm_priv *priv = dev_get_priv(dev);
127 struct sunxi_pwm *regs = priv->regs;
130 debug("%s: Enable '%s'\n", __func__, dev->name);
132 v = readl(®s->ctrl);
134 v &= ~SUNXI_PWM_CTRL_ENABLE0;
135 writel(v, ®s->ctrl);
139 sunxi_pwm_config_pinmux();
142 v &= ~SUNXI_PWM_CTRL_CH0_ACT_STA;
144 v |= SUNXI_PWM_CTRL_CH0_ACT_STA;
145 v |= SUNXI_PWM_CTRL_ENABLE0;
146 writel(v, ®s->ctrl);
151 static int sunxi_pwm_ofdata_to_platdata(struct udevice *dev)
153 struct sunxi_pwm_priv *priv = dev_get_priv(dev);
155 priv->regs = (struct sunxi_pwm *)devfdt_get_addr(dev);
160 static int sunxi_pwm_probe(struct udevice *dev)
165 static const struct pwm_ops sunxi_pwm_ops = {
166 .set_invert = sunxi_pwm_set_invert,
167 .set_config = sunxi_pwm_set_config,
168 .set_enable = sunxi_pwm_set_enable,
171 static const struct udevice_id sunxi_pwm_ids[] = {
172 { .compatible = "allwinner,sun5i-a13-pwm" },
173 { .compatible = "allwinner,sun50i-a64-pwm" },
177 U_BOOT_DRIVER(sunxi_pwm) = {
180 .of_match = sunxi_pwm_ids,
181 .ops = &sunxi_pwm_ops,
182 .ofdata_to_platdata = sunxi_pwm_ofdata_to_platdata,
183 .probe = sunxi_pwm_probe,
184 .priv_auto_alloc_size = sizeof(struct sunxi_pwm_priv),