drivers/video/dw_mipi_dsi.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2016, Fuzhou Rockchip Electronics Co., Ltd
   4  * Copyright (C) 2019, STMicroelectronics - All Rights Reserved
   5  * Author(s): Philippe Cornu <[email protected]> for STMicroelectronics.
   6  *            Yannick Fertre <[email protected]> for STMicroelectronics.
   7  *
   8  * This generic Synopsys DesignWare MIPI DSI host driver is inspired from
   9  * the Linux Kernel driver drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c.
  10  */
  11
  12 #include <common.h>
  13 #include <clk.h>
  14 #include <dsi_host.h>
  15 #include <dm.h>
  16 #include <errno.h>
  17 #include <panel.h>
  18 #include <video.h>
  19 #include <asm/io.h>
  20 #include <asm/arch/gpio.h>
  21 #include <dm/device-internal.h>
  22 #include <dm/device_compat.h>
  23 #include <linux/bitops.h>
  24 #include <linux/delay.h>
  25 #include <linux/iopoll.h>
  26 #include <video_bridge.h>
  27
  28 #define HWVER_131                       0x31333100      /* IP version 1.31 */
  29
  30 #define DSI_VERSION                     0x00
  31 #define VERSION                         GENMASK(31, 8)
  32
  33 #define DSI_PWR_UP                      0x04
  34 #define RESET                           0
  35 #define POWERUP                         BIT(0)
  36
  37 #define DSI_CLKMGR_CFG                  0x08
  38 #define TO_CLK_DIVISION(div)            (((div) & 0xff) << 8)
  39 #define TX_ESC_CLK_DIVISION(div)        ((div) & 0xff)
  40
  41 #define DSI_DPI_VCID                    0x0c
  42 #define DPI_VCID(vcid)                  ((vcid) & 0x3)
  43
  44 #define DSI_DPI_COLOR_CODING            0x10
  45 #define LOOSELY18_EN                    BIT(8)
  46 #define DPI_COLOR_CODING_16BIT_1        0x0
  47 #define DPI_COLOR_CODING_16BIT_2        0x1
  48 #define DPI_COLOR_CODING_16BIT_3        0x2
  49 #define DPI_COLOR_CODING_18BIT_1        0x3
  50 #define DPI_COLOR_CODING_18BIT_2        0x4
  51 #define DPI_COLOR_CODING_24BIT          0x5
  52
  53 #define DSI_DPI_CFG_POL                 0x14
  54 #define COLORM_ACTIVE_LOW               BIT(4)
  55 #define SHUTD_ACTIVE_LOW                BIT(3)
  56 #define HSYNC_ACTIVE_LOW                BIT(2)
  57 #define VSYNC_ACTIVE_LOW                BIT(1)
  58 #define DATAEN_ACTIVE_LOW               BIT(0)
  59
  60 #define DSI_DPI_LP_CMD_TIM              0x18
  61 #define OUTVACT_LPCMD_TIME(p)           (((p) & 0xff) << 16)
  62 #define INVACT_LPCMD_TIME(p)            ((p) & 0xff)
  63
  64 #define DSI_DBI_VCID                    0x1c
  65 #define DSI_DBI_CFG                     0x20
  66 #define DSI_DBI_PARTITIONING_EN         0x24
  67 #define DSI_DBI_CMDSIZE                 0x28
  68
  69 #define DSI_PCKHDL_CFG                  0x2c
  70 #define CRC_RX_EN                       BIT(4)
  71 #define ECC_RX_EN                       BIT(3)
  72 #define BTA_EN                          BIT(2)
  73 #define EOTP_RX_EN                      BIT(1)
  74 #define EOTP_TX_EN                      BIT(0)
  75
  76 #define DSI_GEN_VCID                    0x30
  77
  78 #define DSI_MODE_CFG                    0x34
  79 #define ENABLE_VIDEO_MODE               0
  80 #define ENABLE_CMD_MODE                 BIT(0)
  81
  82 #define DSI_VID_MODE_CFG                0x38
  83 #define ENABLE_LOW_POWER                (0x3f << 8)
  84 #define ENABLE_LOW_POWER_MASK           (0x3f << 8)
  85 #define VID_MODE_TYPE_NON_BURST_SYNC_PULSES     0x0
  86 #define VID_MODE_TYPE_NON_BURST_SYNC_EVENTS     0x1
  87 #define VID_MODE_TYPE_BURST                     0x2
  88 #define VID_MODE_TYPE_MASK                      0x3
  89
  90 #define DSI_VID_PKT_SIZE                0x3c
  91 #define VID_PKT_SIZE(p)                 ((p) & 0x3fff)
  92
  93 #define DSI_VID_NUM_CHUNKS              0x40
  94 #define VID_NUM_CHUNKS(c)               ((c) & 0x1fff)
  95
  96 #define DSI_VID_NULL_SIZE               0x44
  97 #define VID_NULL_SIZE(b)                ((b) & 0x1fff)
  98
  99 #define DSI_VID_HSA_TIME                0x48
 100 #define DSI_VID_HBP_TIME                0x4c
 101 #define DSI_VID_HLINE_TIME              0x50
 102 #define DSI_VID_VSA_LINES               0x54
 103 #define DSI_VID_VBP_LINES               0x58
 104 #define DSI_VID_VFP_LINES               0x5c
 105 #define DSI_VID_VACTIVE_LINES           0x60
 106 #define DSI_EDPI_CMD_SIZE               0x64
 107
 108 #define DSI_CMD_MODE_CFG                0x68
 109 #define MAX_RD_PKT_SIZE_LP              BIT(24)
 110 #define DCS_LW_TX_LP                    BIT(19)
 111 #define DCS_SR_0P_TX_LP                 BIT(18)
 112 #define DCS_SW_1P_TX_LP                 BIT(17)
 113 #define DCS_SW_0P_TX_LP                 BIT(16)
 114 #define GEN_LW_TX_LP                    BIT(14)
 115 #define GEN_SR_2P_TX_LP                 BIT(13)
 116 #define GEN_SR_1P_TX_LP                 BIT(12)
 117 #define GEN_SR_0P_TX_LP                 BIT(11)
 118 #define GEN_SW_2P_TX_LP                 BIT(10)
 119 #define GEN_SW_1P_TX_LP                 BIT(9)
 120 #define GEN_SW_0P_TX_LP                 BIT(8)
 121 #define ACK_RQST_EN                     BIT(1)
 122 #define TEAR_FX_EN                      BIT(0)
 123
 124 #define CMD_MODE_ALL_LP                 (MAX_RD_PKT_SIZE_LP | \
 125                                          DCS_LW_TX_LP | \
 126                                          DCS_SR_0P_TX_LP | \
 127                                          DCS_SW_1P_TX_LP | \
 128                                          DCS_SW_0P_TX_LP | \
 129                                          GEN_LW_TX_LP | \
 130                                          GEN_SR_2P_TX_LP | \
 131                                          GEN_SR_1P_TX_LP | \
 132                                          GEN_SR_0P_TX_LP | \
 133                                          GEN_SW_2P_TX_LP | \
 134                                          GEN_SW_1P_TX_LP | \
 135                                          GEN_SW_0P_TX_LP)
 136
 137 #define DSI_GEN_HDR                     0x6c
 138 #define DSI_GEN_PLD_DATA                0x70
 139
 140 #define DSI_CMD_PKT_STATUS              0x74
 141 #define GEN_RD_CMD_BUSY                 BIT(6)
 142 #define GEN_PLD_R_FULL                  BIT(5)
 143 #define GEN_PLD_R_EMPTY                 BIT(4)
 144 #define GEN_PLD_W_FULL                  BIT(3)
 145 #define GEN_PLD_W_EMPTY                 BIT(2)
 146 #define GEN_CMD_FULL                    BIT(1)
 147 #define GEN_CMD_EMPTY                   BIT(0)
 148
 149 #define DSI_TO_CNT_CFG                  0x78
 150 #define HSTX_TO_CNT(p)                  (((p) & 0xffff) << 16)
 151 #define LPRX_TO_CNT(p)                  ((p) & 0xffff)
 152
 153 #define DSI_HS_RD_TO_CNT                0x7c
 154 #define DSI_LP_RD_TO_CNT                0x80
 155 #define DSI_HS_WR_TO_CNT                0x84
 156 #define DSI_LP_WR_TO_CNT                0x88
 157 #define DSI_BTA_TO_CNT                  0x8c
 158
 159 #define DSI_LPCLK_CTRL                  0x94
 160 #define AUTO_CLKLANE_CTRL               BIT(1)
 161 #define PHY_TXREQUESTCLKHS              BIT(0)
 162
 163 #define DSI_PHY_TMR_LPCLK_CFG           0x98
 164 #define PHY_CLKHS2LP_TIME(lbcc)         (((lbcc) & 0x3ff) << 16)
 165 #define PHY_CLKLP2HS_TIME(lbcc)         ((lbcc) & 0x3ff)
 166
 167 #define DSI_PHY_TMR_CFG                 0x9c
 168 #define PHY_HS2LP_TIME(lbcc)            (((lbcc) & 0xff) << 24)
 169 #define PHY_LP2HS_TIME(lbcc)            (((lbcc) & 0xff) << 16)
 170 #define MAX_RD_TIME(lbcc)               ((lbcc) & 0x7fff)
 171 #define PHY_HS2LP_TIME_V131(lbcc)       (((lbcc) & 0x3ff) << 16)
 172 #define PHY_LP2HS_TIME_V131(lbcc)       ((lbcc) & 0x3ff)
 173
 174 #define DSI_PHY_RSTZ                    0xa0
 175 #define PHY_DISFORCEPLL                 0
 176 #define PHY_ENFORCEPLL                  BIT(3)
 177 #define PHY_DISABLECLK                  0
 178 #define PHY_ENABLECLK                   BIT(2)
 179 #define PHY_RSTZ                        0
 180 #define PHY_UNRSTZ                      BIT(1)
 181 #define PHY_SHUTDOWNZ                   0
 182 #define PHY_UNSHUTDOWNZ                 BIT(0)
 183
 184 #define DSI_PHY_IF_CFG                  0xa4
 185 #define PHY_STOP_WAIT_TIME(cycle)       (((cycle) & 0xff) << 8)
 186 #define N_LANES(n)                      (((n) - 1) & 0x3)
 187
 188 #define DSI_PHY_ULPS_CTRL               0xa8
 189 #define DSI_PHY_TX_TRIGGERS             0xac
 190
 191 #define DSI_PHY_STATUS                  0xb0
 192 #define PHY_STOP_STATE_CLK_LANE         BIT(2)
 193 #define PHY_LOCK                        BIT(0)
 194
 195 #define DSI_PHY_TST_CTRL0               0xb4
 196 #define PHY_TESTCLK                     BIT(1)
 197 #define PHY_UNTESTCLK                   0
 198 #define PHY_TESTCLR                     BIT(0)
 199 #define PHY_UNTESTCLR                   0
 200
 201 #define DSI_PHY_TST_CTRL1               0xb8
 202 #define PHY_TESTEN                      BIT(16)
 203 #define PHY_UNTESTEN                    0
 204 #define PHY_TESTDOUT(n)                 (((n) & 0xff) << 8)
 205 #define PHY_TESTDIN(n)                  ((n) & 0xff)
 206
 207 #define DSI_INT_ST0                     0xbc
 208 #define DSI_INT_ST1                     0xc0
 209 #define DSI_INT_MSK0                    0xc4
 210 #define DSI_INT_MSK1                    0xc8
 211
 212 #define DSI_PHY_TMR_RD_CFG              0xf4
 213 #define MAX_RD_TIME_V131(lbcc)          ((lbcc) & 0x7fff)
 214
 215 #define PHY_STATUS_TIMEOUT_US           10000
 216 #define CMD_PKT_STATUS_TIMEOUT_US       20000
 217
 218 #define MSEC_PER_SEC                    1000
 219
 220 struct dw_mipi_dsi {
 221         struct mipi_dsi_host dsi_host;
 222         struct mipi_dsi_device *device;
 223         void __iomem *base;
 224         unsigned int lane_mbps; /* per lane */
 225         u32 channel;
 226         unsigned int max_data_lanes;
 227         const struct mipi_dsi_phy_ops *phy_ops;
 228 };
 229
 230 static int dsi_mode_vrefresh(struct display_timing *timings)
 231 {
 232         int refresh = 0;
 233         unsigned int calc_val;
 234         u32 htotal = timings->hactive.typ + timings->hfront_porch.typ +
 235                      timings->hback_porch.typ + timings->hsync_len.typ;
 236         u32 vtotal = timings->vactive.typ + timings->vfront_porch.typ +
 237                      timings->vback_porch.typ + timings->vsync_len.typ;
 238
 239         if (htotal > 0 && vtotal > 0) {
 240                 calc_val = timings->pixelclock.typ;
 241                 calc_val /= htotal;
 242                 refresh = (calc_val + vtotal / 2) / vtotal;
 243         }
 244
 245         return refresh;
 246 }
 247
 248 /*
 249  * The controller should generate 2 frames before
 250  * preparing the peripheral.
 251  */
 252 static void dw_mipi_dsi_wait_for_two_frames(struct display_timing *timings)
 253 {
 254         int refresh, two_frames;
 255
 256         refresh = dsi_mode_vrefresh(timings);
 257         two_frames = DIV_ROUND_UP(MSEC_PER_SEC, refresh) * 2;
 258         mdelay(two_frames);
 259 }
 260
 261 static inline struct dw_mipi_dsi *host_to_dsi(struct mipi_dsi_host *host)
 262 {
 263         return container_of(host, struct dw_mipi_dsi, dsi_host);
 264 }
 265
 266 static inline void dsi_write(struct dw_mipi_dsi *dsi, u32 reg, u32 val)
 267 {
 268         writel(val, dsi->base + reg);
 269 }
 270
 271 static inline u32 dsi_read(struct dw_mipi_dsi *dsi, u32 reg)
 272 {
 273         return readl(dsi->base + reg);
 274 }
 275
 276 static int dw_mipi_dsi_host_attach(struct mipi_dsi_host *host,
 277                                    struct mipi_dsi_device *device)
 278 {
 279         struct dw_mipi_dsi *dsi = host_to_dsi(host);
 280
 281         if (device->lanes > dsi->max_data_lanes) {
 282                 dev_err(device->dev,
 283                         "the number of data lanes(%u) is too many\n",
 284                         device->lanes);
 285                 return -EINVAL;
 286         }
 287
 288         dsi->channel = device->channel;
 289
 290         return 0;
 291 }
 292
 293 static void dw_mipi_message_config(struct dw_mipi_dsi *dsi,
 294                                    const struct mipi_dsi_msg *msg)
 295 {
 296         bool lpm = msg->flags & MIPI_DSI_MSG_USE_LPM;
 297         u32 val = 0;
 298
 299         if (msg->flags & MIPI_DSI_MSG_REQ_ACK)
 300                 val |= ACK_RQST_EN;
 301         if (lpm)
 302                 val |= CMD_MODE_ALL_LP;
 303
 304         dsi_write(dsi, DSI_LPCLK_CTRL, lpm ? 0 : PHY_TXREQUESTCLKHS);
 305         dsi_write(dsi, DSI_CMD_MODE_CFG, val);
 306 }
 307
 308 static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi *dsi, u32 hdr_val)
 309 {
 310         int ret;
 311         u32 val, mask;
 312
 313         ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
 314                                  val, !(val & GEN_CMD_FULL),
 315                                  CMD_PKT_STATUS_TIMEOUT_US);
 316         if (ret) {
 317                 dev_err(dsi->dev, "failed to get available command FIFO\n");
 318                 return ret;
 319         }
 320
 321         dsi_write(dsi, DSI_GEN_HDR, hdr_val);
 322
 323         mask = GEN_CMD_EMPTY | GEN_PLD_W_EMPTY;
 324         ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
 325                                  val, (val & mask) == mask,
 326                                  CMD_PKT_STATUS_TIMEOUT_US);
 327         if (ret) {
 328                 dev_err(dsi->dev, "failed to write command FIFO\n");
 329                 return ret;
 330         }
 331
 332         return 0;
 333 }
 334
 335 static int dw_mipi_dsi_write(struct dw_mipi_dsi *dsi,
 336                              const struct mipi_dsi_packet *packet)
 337 {
 338         const u8 *tx_buf = packet->payload;
 339         int len = packet->payload_length, pld_data_bytes = sizeof(u32), ret;
 340         __le32 word;
 341         u32 val;
 342
 343         while (len) {
 344                 if (len < pld_data_bytes) {
 345                         word = 0;
 346                         memcpy(&word, tx_buf, len);
 347                         dsi_write(dsi, DSI_GEN_PLD_DATA, le32_to_cpu(word));
 348                         len = 0;
 349                 } else {
 350                         memcpy(&word, tx_buf, pld_data_bytes);
 351                         dsi_write(dsi, DSI_GEN_PLD_DATA, le32_to_cpu(word));
 352                         tx_buf += pld_data_bytes;
 353                         len -= pld_data_bytes;
 354                 }
 355
 356                 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
 357                                          val, !(val & GEN_PLD_W_FULL),
 358                                          CMD_PKT_STATUS_TIMEOUT_US);
 359                 if (ret) {
 360                         dev_err(dsi->dev,
 361                                 "failed to get available write payload FIFO\n");
 362                         return ret;
 363                 }
 364         }
 365
 366         word = 0;
 367         memcpy(&word, packet->header, sizeof(packet->header));
 368         return dw_mipi_dsi_gen_pkt_hdr_write(dsi, le32_to_cpu(word));
 369 }
 370
 371 static int dw_mipi_dsi_read(struct dw_mipi_dsi *dsi,
 372                             const struct mipi_dsi_msg *msg)
 373 {
 374         int i, j, ret, len = msg->rx_len;
 375         u8 *buf = msg->rx_buf;
 376         u32 val;
 377
 378         /* Wait end of the read operation */
 379         ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
 380                                  val, !(val & GEN_RD_CMD_BUSY),
 381                                  CMD_PKT_STATUS_TIMEOUT_US);
 382         if (ret) {
 383                 dev_err(dsi->dev, "Timeout during read operation\n");
 384                 return ret;
 385         }
 386
 387         for (i = 0; i < len; i += 4) {
 388                 /* Read fifo must not be empty before all bytes are read */
 389                 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
 390                                          val, !(val & GEN_PLD_R_EMPTY),
 391                                          CMD_PKT_STATUS_TIMEOUT_US);
 392                 if (ret) {
 393                         dev_err(dsi->dev, "Read payload FIFO is empty\n");
 394                         return ret;
 395                 }
 396
 397                 val = dsi_read(dsi, DSI_GEN_PLD_DATA);
 398                 for (j = 0; j < 4 && j + i < len; j++)
 399                         buf[i + j] = val >> (8 * j);
 400         }
 401
 402         return ret;
 403 }
 404
 405 static ssize_t dw_mipi_dsi_host_transfer(struct mipi_dsi_host *host,
 406                                          const struct mipi_dsi_msg *msg)
 407 {
 408         struct dw_mipi_dsi *dsi = host_to_dsi(host);
 409         struct mipi_dsi_packet packet;
 410         int ret, nb_bytes;
 411
 412         ret = mipi_dsi_create_packet(&packet, msg);
 413         if (ret) {
 414                 dev_err(dsi->dev, "failed to create packet: %d\n", ret);
 415                 return ret;
 416         }
 417
 418         dw_mipi_message_config(dsi, msg);
 419
 420         ret = dw_mipi_dsi_write(dsi, &packet);
 421         if (ret)
 422                 return ret;
 423
 424         if (msg->rx_buf && msg->rx_len) {
 425                 ret = dw_mipi_dsi_read(dsi, msg);
 426                 if (ret)
 427                         return ret;
 428                 nb_bytes = msg->rx_len;
 429         } else {
 430                 nb_bytes = packet.size;
 431         }
 432
 433         return nb_bytes;
 434 }
 435
 436 static const struct mipi_dsi_host_ops dw_mipi_dsi_host_ops = {
 437         .attach = dw_mipi_dsi_host_attach,
 438         .transfer = dw_mipi_dsi_host_transfer,
 439 };
 440
 441 static void dw_mipi_dsi_video_mode_config(struct dw_mipi_dsi *dsi)
 442 {
 443         struct mipi_dsi_device *device = dsi->device;
 444         u32 val;
 445
 446         /*
 447          * TODO dw drv improvements
 448          * enabling low power is panel-dependent, we should use the
 449          * panel configuration here...
 450          */
 451         val = ENABLE_LOW_POWER;
 452
 453         if (device->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
 454                 val |= VID_MODE_TYPE_BURST;
 455         else if (device->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
 456                 val |= VID_MODE_TYPE_NON_BURST_SYNC_PULSES;
 457         else
 458                 val |= VID_MODE_TYPE_NON_BURST_SYNC_EVENTS;
 459
 460         dsi_write(dsi, DSI_VID_MODE_CFG, val);
 461 }
 462
 463 static void dw_mipi_dsi_set_mode(struct dw_mipi_dsi *dsi,
 464                                  unsigned long mode_flags)
 465 {
 466         const struct mipi_dsi_phy_ops *phy_ops = dsi->phy_ops;
 467
 468         dsi_write(dsi, DSI_PWR_UP, RESET);
 469
 470         if (mode_flags & MIPI_DSI_MODE_VIDEO) {
 471                 dsi_write(dsi, DSI_MODE_CFG, ENABLE_VIDEO_MODE);
 472                 dw_mipi_dsi_video_mode_config(dsi);
 473                 dsi_write(dsi, DSI_LPCLK_CTRL, PHY_TXREQUESTCLKHS);
 474         } else {
 475                 dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);
 476         }
 477
 478         if (phy_ops->post_set_mode)
 479                 phy_ops->post_set_mode(dsi->device, mode_flags);
 480
 481         dsi_write(dsi, DSI_PWR_UP, POWERUP);
 482 }
 483
 484 static void dw_mipi_dsi_init_pll(struct dw_mipi_dsi *dsi)
 485 {
 486         /*
 487          * The maximum permitted escape clock is 20MHz and it is derived from
 488          * lanebyteclk, which is running at "lane_mbps / 8".  Thus we want:
 489          *
 490          *     (lane_mbps >> 3) / esc_clk_division < 20
 491          * which is:
 492          *     (lane_mbps >> 3) / 20 > esc_clk_division
 493          */
 494         u32 esc_clk_division = (dsi->lane_mbps >> 3) / 20 + 1;
 495
 496         dsi_write(dsi, DSI_PWR_UP, RESET);
 497
 498         /*
 499          * TODO dw drv improvements
 500          * timeout clock division should be computed with the
 501          * high speed transmission counter timeout and byte lane...
 502          */
 503         dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVISION(10) |
 504                   TX_ESC_CLK_DIVISION(esc_clk_division));
 505 }
 506
 507 static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi,
 508                                    struct display_timing *timings)
 509 {
 510         struct mipi_dsi_device *device = dsi->device;
 511         u32 val = 0, color = 0;
 512
 513         switch (device->format) {
 514         case MIPI_DSI_FMT_RGB888:
 515                 color = DPI_COLOR_CODING_24BIT;
 516                 break;
 517         case MIPI_DSI_FMT_RGB666:
 518                 color = DPI_COLOR_CODING_18BIT_2 | LOOSELY18_EN;
 519                 break;
 520         case MIPI_DSI_FMT_RGB666_PACKED:
 521                 color = DPI_COLOR_CODING_18BIT_1;
 522                 break;
 523         case MIPI_DSI_FMT_RGB565:
 524                 color = DPI_COLOR_CODING_16BIT_1;
 525                 break;
 526         }
 527
 528         if (device->mode_flags & DISPLAY_FLAGS_VSYNC_HIGH)
 529                 val |= VSYNC_ACTIVE_LOW;
 530         if (device->mode_flags & DISPLAY_FLAGS_HSYNC_HIGH)
 531                 val |= HSYNC_ACTIVE_LOW;
 532
 533         dsi_write(dsi, DSI_DPI_VCID, DPI_VCID(dsi->channel));
 534         dsi_write(dsi, DSI_DPI_COLOR_CODING, color);
 535         dsi_write(dsi, DSI_DPI_CFG_POL, val);
 536         /*
 537          * TODO dw drv improvements
 538          * largest packet sizes during hfp or during vsa/vpb/vfp
 539          * should be computed according to byte lane, lane number and only
 540          * if sending lp cmds in high speed is enable (PHY_TXREQUESTCLKHS)
 541          */
 542         dsi_write(dsi, DSI_DPI_LP_CMD_TIM, OUTVACT_LPCMD_TIME(4)
 543                   | INVACT_LPCMD_TIME(4));
 544 }
 545
 546 static void dw_mipi_dsi_packet_handler_config(struct dw_mipi_dsi *dsi)
 547 {
 548         dsi_write(dsi, DSI_PCKHDL_CFG, CRC_RX_EN | ECC_RX_EN | BTA_EN);
 549 }
 550
 551 static void dw_mipi_dsi_video_packet_config(struct dw_mipi_dsi *dsi,
 552                                             struct display_timing *timings)
 553 {
 554         /*
 555          * TODO dw drv improvements
 556          * only burst mode is supported here. For non-burst video modes,
 557          * we should compute DSI_VID_PKT_SIZE, DSI_VCCR.NUMC &
 558          * DSI_VNPCR.NPSIZE... especially because this driver supports
 559          * non-burst video modes, see dw_mipi_dsi_video_mode_config()...
 560          */
 561         dsi_write(dsi, DSI_VID_PKT_SIZE, VID_PKT_SIZE(timings->hactive.typ));
 562 }
 563
 564 static void dw_mipi_dsi_command_mode_config(struct dw_mipi_dsi *dsi)
 565 {
 566         const struct mipi_dsi_phy_ops *phy_ops = dsi->phy_ops;
 567
 568         /*
 569          * TODO dw drv improvements
 570          * compute high speed transmission counter timeout according
 571          * to the timeout clock division (TO_CLK_DIVISION) and byte lane...
 572          */
 573         dsi_write(dsi, DSI_TO_CNT_CFG, HSTX_TO_CNT(1000) | LPRX_TO_CNT(1000));
 574         /*
 575          * TODO dw drv improvements
 576          * the Bus-Turn-Around Timeout Counter should be computed
 577          * according to byte lane...
 578          */
 579         dsi_write(dsi, DSI_BTA_TO_CNT, 0xd00);
 580         dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);
 581
 582         if (phy_ops->post_set_mode)
 583                 phy_ops->post_set_mode(dsi->device, 0);
 584 }
 585
 586 /* Get lane byte clock cycles. */
 587 static u32 dw_mipi_dsi_get_hcomponent_lbcc(struct dw_mipi_dsi *dsi,
 588                                            struct display_timing *timings,
 589                                            u32 hcomponent)
 590 {
 591         u32 frac, lbcc;
 592
 593         lbcc = hcomponent * dsi->lane_mbps * MSEC_PER_SEC / 8;
 594
 595         frac = lbcc % (timings->pixelclock.typ / 1000);
 596         lbcc = lbcc / (timings->pixelclock.typ / 1000);
 597         if (frac)
 598                 lbcc++;
 599
 600         return lbcc;
 601 }
 602
 603 static void dw_mipi_dsi_line_timer_config(struct dw_mipi_dsi *dsi,
 604                                           struct display_timing *timings)
 605 {
 606         u32 htotal, hsa, hbp, lbcc;
 607
 608         htotal = timings->hactive.typ + timings->hfront_porch.typ +
 609                  timings->hback_porch.typ + timings->hsync_len.typ;
 610
 611         hsa = timings->hback_porch.typ;
 612         hbp = timings->hsync_len.typ;
 613
 614         /*
 615          * TODO dw drv improvements
 616          * computations below may be improved...
 617          */
 618         lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, timings, htotal);
 619         dsi_write(dsi, DSI_VID_HLINE_TIME, lbcc);
 620
 621         lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, timings, hsa);
 622         dsi_write(dsi, DSI_VID_HSA_TIME, lbcc);
 623
 624         lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, timings, hbp);
 625         dsi_write(dsi, DSI_VID_HBP_TIME, lbcc);
 626 }
 627
 628 static void dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi,
 629                                                struct display_timing *timings)
 630 {
 631         u32 vactive, vsa, vfp, vbp;
 632
 633         vactive = timings->vactive.typ;
 634         vsa =  timings->vback_porch.typ;
 635         vfp =  timings->vfront_porch.typ;
 636         vbp = timings->vsync_len.typ;
 637
 638         dsi_write(dsi, DSI_VID_VACTIVE_LINES, vactive);
 639         dsi_write(dsi, DSI_VID_VSA_LINES, vsa);
 640         dsi_write(dsi, DSI_VID_VFP_LINES, vfp);
 641         dsi_write(dsi, DSI_VID_VBP_LINES, vbp);
 642 }
 643
 644 static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi)
 645 {
 646         u32 hw_version;
 647
 648         /*
 649          * TODO dw drv improvements
 650          * data & clock lane timers should be computed according to panel
 651          * blankings and to the automatic clock lane control mode...
 652          * note: DSI_PHY_TMR_CFG.MAX_RD_TIME should be in line with
 653          * DSI_CMD_MODE_CFG.MAX_RD_PKT_SIZE_LP (see CMD_MODE_ALL_LP)
 654          */
 655
 656         hw_version = dsi_read(dsi, DSI_VERSION) & VERSION;
 657
 658         if (hw_version >= HWVER_131) {
 659                 dsi_write(dsi, DSI_PHY_TMR_CFG, PHY_HS2LP_TIME_V131(0x40) |
 660                           PHY_LP2HS_TIME_V131(0x40));
 661                 dsi_write(dsi, DSI_PHY_TMR_RD_CFG, MAX_RD_TIME_V131(10000));
 662         } else {
 663                 dsi_write(dsi, DSI_PHY_TMR_CFG, PHY_HS2LP_TIME(0x40) |
 664                           PHY_LP2HS_TIME(0x40) | MAX_RD_TIME(10000));
 665         }
 666
 667         dsi_write(dsi, DSI_PHY_TMR_LPCLK_CFG, PHY_CLKHS2LP_TIME(0x40)
 668                   | PHY_CLKLP2HS_TIME(0x40));
 669 }
 670
 671 static void dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi *dsi)
 672 {
 673         struct mipi_dsi_device *device = dsi->device;
 674
 675         /*
 676          * TODO dw drv improvements
 677          * stop wait time should be the maximum between host dsi
 678          * and panel stop wait times
 679          */
 680         dsi_write(dsi, DSI_PHY_IF_CFG, PHY_STOP_WAIT_TIME(0x20) |
 681                   N_LANES(device->lanes));
 682 }
 683
 684 static void dw_mipi_dsi_dphy_init(struct dw_mipi_dsi *dsi)
 685 {
 686         /* Clear PHY state */
 687         dsi_write(dsi, DSI_PHY_RSTZ, PHY_DISFORCEPLL | PHY_DISABLECLK
 688                   | PHY_RSTZ | PHY_SHUTDOWNZ);
 689         dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR);
 690         dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLR);
 691         dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR);
 692 }
 693
 694 static void dw_mipi_dsi_dphy_enable(struct dw_mipi_dsi *dsi)
 695 {
 696         u32 val;
 697         int ret;
 698
 699         dsi_write(dsi, DSI_PHY_RSTZ, PHY_ENFORCEPLL | PHY_ENABLECLK |
 700                   PHY_UNRSTZ | PHY_UNSHUTDOWNZ);
 701
 702         ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS, val,
 703                                  val & PHY_LOCK, PHY_STATUS_TIMEOUT_US);
 704         if (ret)
 705                 dev_warn(dsi->dev, "failed to wait phy lock state\n");
 706
 707         ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS,
 708                                  val, val & PHY_STOP_STATE_CLK_LANE,
 709                                  PHY_STATUS_TIMEOUT_US);
 710         if (ret)
 711                 dev_warn(dsi->dev, "failed to wait phy clk lane stop state\n");
 712 }
 713
 714 static void dw_mipi_dsi_clear_err(struct dw_mipi_dsi *dsi)
 715 {
 716         dsi_read(dsi, DSI_INT_ST0);
 717         dsi_read(dsi, DSI_INT_ST1);
 718         dsi_write(dsi, DSI_INT_MSK0, 0);
 719         dsi_write(dsi, DSI_INT_MSK1, 0);
 720 }
 721
 722 static void dw_mipi_dsi_bridge_set(struct dw_mipi_dsi *dsi,
 723                                    struct display_timing *timings)
 724 {
 725         const struct mipi_dsi_phy_ops *phy_ops = dsi->phy_ops;
 726         struct mipi_dsi_device *device = dsi->device;
 727         int ret;
 728
 729         ret = phy_ops->get_lane_mbps(dsi->device, timings, device->lanes,
 730                                      device->format, &dsi->lane_mbps);
 731         if (ret)
 732                 dev_warn(dsi->dev, "Phy get_lane_mbps() failed\n");
 733
 734         dw_mipi_dsi_init_pll(dsi);
 735         dw_mipi_dsi_dpi_config(dsi, timings);
 736         dw_mipi_dsi_packet_handler_config(dsi);
 737         dw_mipi_dsi_video_mode_config(dsi);
 738         dw_mipi_dsi_video_packet_config(dsi, timings);
 739         dw_mipi_dsi_command_mode_config(dsi);
 740         dw_mipi_dsi_line_timer_config(dsi, timings);
 741         dw_mipi_dsi_vertical_timing_config(dsi, timings);
 742
 743         dw_mipi_dsi_dphy_init(dsi);
 744         dw_mipi_dsi_dphy_timing_config(dsi);
 745         dw_mipi_dsi_dphy_interface_config(dsi);
 746
 747         dw_mipi_dsi_clear_err(dsi);
 748
 749         ret = phy_ops->init(dsi->device);
 750         if (ret)
 751                 dev_warn(dsi->dev, "Phy init() failed\n");
 752
 753         dw_mipi_dsi_dphy_enable(dsi);
 754
 755         dw_mipi_dsi_wait_for_two_frames(timings);
 756
 757         /* Switch to cmd mode for panel-bridge pre_enable & panel prepare */
 758         dw_mipi_dsi_set_mode(dsi, 0);
 759 }
 760
 761 static int dw_mipi_dsi_init(struct udevice *dev,
 762                             struct mipi_dsi_device *device,
 763                             struct display_timing *timings,
 764                             unsigned int max_data_lanes,
 765                             const struct mipi_dsi_phy_ops *phy_ops)
 766 {
 767         struct dw_mipi_dsi *dsi = dev_get_priv(dev);
 768         struct clk clk;
 769         int ret;
 770
 771         if (!phy_ops->init || !phy_ops->get_lane_mbps) {
 772                 dev_err(device->dev, "Phy not properly configured\n");
 773                 return -ENODEV;
 774         }
 775
 776         dsi->phy_ops = phy_ops;
 777         dsi->max_data_lanes = max_data_lanes;
 778         dsi->device = device;
 779         dsi->dsi_host.ops = &dw_mipi_dsi_host_ops;
 780         device->host = &dsi->dsi_host;
 781
 782         dsi->base = (void *)dev_read_addr(device->dev);
 783         if ((fdt_addr_t)dsi->base == FDT_ADDR_T_NONE) {
 784                 dev_err(device->dev, "dsi dt register address error\n");
 785                 return -EINVAL;
 786         }
 787
 788         ret = clk_get_by_name(device->dev, "px_clk", &clk);
 789         if (ret) {
 790                 dev_err(device->dev, "peripheral clock get error %d\n", ret);
 791                 return ret;
 792         }
 793
 794         /*  get the pixel clock set by the clock framework */
 795         timings->pixelclock.typ = clk_get_rate(&clk);
 796
 797         dw_mipi_dsi_bridge_set(dsi, timings);
 798
 799         return 0;
 800 }
 801
 802 static int dw_mipi_dsi_enable(struct udevice *dev)
 803 {
 804         struct dw_mipi_dsi *dsi = dev_get_priv(dev);
 805
 806         /* Switch to video mode for panel-bridge enable & panel enable */
 807         dw_mipi_dsi_set_mode(dsi, MIPI_DSI_MODE_VIDEO);
 808
 809         return 0;
 810 }
 811
 812 struct dsi_host_ops dw_mipi_dsi_ops = {
 813         .init = dw_mipi_dsi_init,
 814         .enable = dw_mipi_dsi_enable,
 815 };
 816
 817 static int dw_mipi_dsi_probe(struct udevice *dev)
 818 {
 819         return 0;
 820 }
 821
 822 U_BOOT_DRIVER(dw_mipi_dsi) = {
 823         .name                   = "dw_mipi_dsi",
 824         .id                     = UCLASS_DSI_HOST,
 825         .probe                  = dw_mipi_dsi_probe,
 826         .ops                    = &dw_mipi_dsi_ops,
 827         .priv_auto_alloc_size   = sizeof(struct dw_mipi_dsi),
 828 };
 829
 830 MODULE_AUTHOR("Chris Zhong <[email protected]>");
 831 MODULE_AUTHOR("Philippe Cornu <[email protected]>");
 832 MODULE_AUTHOR("Yannick Fertré <[email protected]>");
 833 MODULE_DESCRIPTION("DW MIPI DSI host controller driver");
 834 MODULE_LICENSE("GPL");
 835 MODULE_ALIAS("platform:dw-mipi-dsi");