arch/arm/dts/k3-am62a7-r5-sk.dts

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * AM62A7 SK dts file for R5 SPL
   4  * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
   5  */
   6
   7 #include "k3-am62a7-sk.dts"
   8 #include "k3-am62a-ddr-1866mhz-32bit.dtsi"
   9 #include "k3-am62a-ddr.dtsi"
  10
  11 #include "k3-am62a7-sk-u-boot.dtsi"
  12
  13 / {
  14         aliases {
  15                 remoteproc0 = &sysctrler;
  16                 remoteproc1 = &a53_0;
  17                 serial0 = &wkup_uart0;
  18                 serial3 = &main_uart1;
  19         };
  20
  21         chosen {
  22                 stdout-path = "serial2:115200n8";
  23                 tick-timer = &timer1;
  24         };
  25
  26         memory@80000000 {
  27                 device_type = "memory";
  28                 /* 4G RAM */
  29                 reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
  30                       <0x00000008 0x80000000 0x00000000 0x80000000>;
  31                 bootph-pre-ram;
  32         };
  33
  34         reserved-memory {
  35                 #address-cells = <2>;
  36                 #size-cells = <2>;
  37                 ranges;
  38
  39                 secure_ddr: optee@9e800000 {
  40                         reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
  41                         alignment = <0x1000>;
  42                         no-map;
  43                 };
  44         };
  45
  46         a53_0: a53@0 {
  47                 compatible = "ti,am654-rproc";
  48                 reg = <0x00 0x00a90000 0x00 0x10>;
  49                 power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
  50                                 <&k3_pds 135 TI_SCI_PD_EXCLUSIVE>,
  51                                 <&k3_pds 166 TI_SCI_PD_EXCLUSIVE>;
  52                 resets = <&k3_reset 135 0>;
  53                 clocks = <&k3_clks 61 0>;
  54                 assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
  55                 assigned-clock-parents = <&k3_clks 61 2>;
  56                 assigned-clock-rates = <200000000>, <1200000000>;
  57                 ti,sci = <&dmsc>;
  58                 ti,sci-proc-id = <32>;
  59                 ti,sci-host-id = <10>;
  60                 bootph-pre-ram;
  61         };
  62
  63         dm_tifs: dm-tifs {
  64                 compatible = "ti,j721e-dm-sci";
  65                 ti,host-id = <36>;
  66                 ti,secure-host;
  67                 mbox-names = "rx", "tx";
  68                 mboxes= <&secure_proxy_main 22>,
  69                         <&secure_proxy_main 23>;
  70                 bootph-pre-ram;
  71         };
  72 };
  73
  74 &dmsc {
  75         mboxes= <&secure_proxy_main 0>,
  76                 <&secure_proxy_main 1>,
  77                 <&secure_proxy_main 0>;
  78         mbox-names = "rx", "tx", "notify";
  79         ti,host-id = <35>;
  80         ti,secure-host;
  81 };
  82
  83 &cbass_main {
  84         sa3_secproxy: secproxy@44880000 {
  85                 compatible = "ti,am654-secure-proxy";
  86                 #mbox-cells = <1>;
  87                 reg = <0x00 0x44880000 0x00 0x20000>,
  88                       <0x0 0x44860000 0x0 0x20000>,
  89                       <0x0 0x43600000 0x0 0x10000>;
  90                 reg-names = "rt", "scfg", "target_data";
  91                 bootph-pre-ram;
  92         };
  93
  94         sysctrler: sysctrler {
  95                 compatible = "ti,am654-system-controller";
  96                 mboxes= <&secure_proxy_main 1>,
  97                         <&secure_proxy_main 0>,
  98                         <&sa3_secproxy 0>;
  99                 mbox-names = "tx", "rx", "boot_notify";
 100                 bootph-pre-ram;
 101         };
 102 };
 103
 104 &mcu_pmx0 {
 105         status = "okay";
 106         bootph-pre-ram;
 107
 108         wkup_uart0_pins_default: wkup-uart0-pins-default {
 109                 pinctrl-single,pins = <
 110                         AM62X_MCU_IOPAD(0x02c, PIN_INPUT, 0)    /* (C6) WKUP_UART0_CTSn */
 111                         AM62X_MCU_IOPAD(0x030, PIN_OUTPUT, 0)   /* (A4) WKUP_UART0_RTSn */
 112                         AM62X_MCU_IOPAD(0x024, PIN_INPUT, 0)    /* (B4) WKUP_UART0_RXD */
 113                         AM62X_MCU_IOPAD(0x028, PIN_OUTPUT, 0)   /* (C5) WKUP_UART0_TXD */
 114                 >;
 115                 bootph-pre-ram;
 116         };
 117 };
 118
 119 &main_pmx0 {
 120         bootph-pre-ram;
 121         main_uart1_pins_default: main-uart1-pins-default {
 122                 pinctrl-single,pins = <
 123                         AM62X_IOPAD(0x194, PIN_INPUT, 2)        /* (B19) MCASP0_AXR3.UART1_CTSn */
 124                         AM62X_IOPAD(0x198, PIN_OUTPUT, 2)       /* (A19) MCASP0_AXR2.UART1_RTSn */
 125                         AM62X_IOPAD(0x1ac, PIN_INPUT, 2)        /* (E19) MCASP0_AFSR.UART1_RXD */
 126                         AM62X_IOPAD(0x1b0, PIN_OUTPUT, 2)       /* (A20) MCASP0_ACLKR.UART1_TXD */
 127                 >;
 128                 bootph-pre-ram;
 129         };
 130 };
 131
 132 /* WKUP UART0 is used for DM firmware logs */
 133 &wkup_uart0 {
 134         pinctrl-names = "default";
 135         pinctrl-0 = <&wkup_uart0_pins_default>;
 136         status = "okay";
 137         bootph-pre-ram;
 138 };
 139
 140 /* Main UART1 is used for TIFS firmware logs */
 141 &main_uart1 {
 142         pinctrl-names = "default";
 143         pinctrl-0 = <&main_uart1_pins_default>;
 144         status = "okay";
 145         bootph-pre-ram;
 146 };