board/atmel/sama5d2_xplained/sama5d2_xplained.c

   1 /*
   2  * Copyright (C) 2015 Atmel Corporation
   3  *                    Wenyou.Yang <[email protected]>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <atmel_hlcdc.h>
  10 #include <debug_uart.h>
  11 #include <dm.h>
  12 #include <i2c.h>
  13 #include <lcd.h>
  14 #include <mmc.h>
  15 #include <spi.h>
  16 #include <version.h>
  17 #include <asm/io.h>
  18 #include <asm/arch/at91_common.h>
  19 #include <asm/arch/atmel_pio4.h>
  20 #include <asm/arch/atmel_mpddrc.h>
  21 #include <asm/arch/atmel_sdhci.h>
  22 #include <asm/arch/clk.h>
  23 #include <asm/arch/gpio.h>
  24 #include <asm/arch/sama5d2.h>
  25
  26 DECLARE_GLOBAL_DATA_PTR;
  27
  28 static void board_usb_hw_init(void)
  29 {
  30         atmel_pio4_set_pio_output(AT91_PIO_PORTB, 10, 1);
  31 }
  32
  33 #ifdef CONFIG_LCD
  34 vidinfo_t panel_info = {
  35         .vl_col = 480,
  36         .vl_row = 272,
  37         .vl_clk = 9000000,
  38         .vl_bpix = LCD_BPP,
  39         .vl_tft = 1,
  40         .vl_hsync_len = 41,
  41         .vl_left_margin = 2,
  42         .vl_right_margin = 2,
  43         .vl_vsync_len = 11,
  44         .vl_upper_margin = 2,
  45         .vl_lower_margin = 2,
  46         .mmio = ATMEL_BASE_LCDC,
  47 };
  48
  49 /* No power up/down pin for the LCD pannel */
  50 void lcd_enable(void)   { /* Empty! */ }
  51 void lcd_disable(void)  { /* Empty! */ }
  52
  53 unsigned int has_lcdc(void)
  54 {
  55         return 1;
  56 }
  57
  58 static void board_lcd_hw_init(void)
  59 {
  60         atmel_pio4_set_a_periph(AT91_PIO_PORTC, 28, 0); /* LCDPWM */
  61         atmel_pio4_set_a_periph(AT91_PIO_PORTC, 29, 0); /* LCDDISP */
  62         atmel_pio4_set_a_periph(AT91_PIO_PORTC, 30, 0); /* LCDVSYNC */
  63         atmel_pio4_set_a_periph(AT91_PIO_PORTC, 31, 0); /* LCDHSYNC */
  64         atmel_pio4_set_a_periph(AT91_PIO_PORTD,  0, 0); /* LCDPCK */
  65         atmel_pio4_set_a_periph(AT91_PIO_PORTD,  1, 0); /* LCDDEN */
  66
  67         /* LCDDAT0 */
  68         /* LCDDAT1 */
  69         atmel_pio4_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDDAT2 */
  70         atmel_pio4_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDDAT3 */
  71         atmel_pio4_set_a_periph(AT91_PIO_PORTC, 12, 0); /* LCDDAT4 */
  72         atmel_pio4_set_a_periph(AT91_PIO_PORTC, 13, 0); /* LCDDAT5 */
  73         atmel_pio4_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDDAT6 */
  74         atmel_pio4_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDDAT7 */
  75
  76         /* LCDDAT8 */
  77         /* LCDDAT9 */
  78         atmel_pio4_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDDAT10 */
  79         atmel_pio4_set_a_periph(AT91_PIO_PORTC, 17, 0); /* LCDDAT11 */
  80         atmel_pio4_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDDAT12 */
  81         atmel_pio4_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDDAT13 */
  82         atmel_pio4_set_a_periph(AT91_PIO_PORTC, 20, 0); /* LCDDAT14 */
  83         atmel_pio4_set_a_periph(AT91_PIO_PORTC, 21, 0); /* LCDDAT15 */
  84
  85         /* LCDD16 */
  86         /* LCDD17 */
  87         atmel_pio4_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDDAT18 */
  88         atmel_pio4_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDDAT19 */
  89         atmel_pio4_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDDAT20 */
  90         atmel_pio4_set_a_periph(AT91_PIO_PORTC, 25, 0); /* LCDDAT21 */
  91         atmel_pio4_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDDAT22 */
  92         atmel_pio4_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDDAT23 */
  93
  94         at91_periph_clk_enable(ATMEL_ID_LCDC);
  95 }
  96
  97 #ifdef CONFIG_LCD_INFO
  98 void lcd_show_board_info(void)
  99 {
 100         ulong dram_size;
 101         int i;
 102         char temp[32];
 103
 104         lcd_printf("%s\n", U_BOOT_VERSION);
 105         lcd_printf("2015 ATMEL Corp\n");
 106         lcd_printf("%s CPU at %s MHz\n", get_cpu_name(),
 107                    strmhz(temp, get_cpu_clk_rate()));
 108
 109         dram_size = 0;
 110         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
 111                 dram_size += gd->bd->bi_dram[i].size;
 112
 113         lcd_printf("%ld MB SDRAM\n", dram_size >> 20);
 114 }
 115 #endif /* CONFIG_LCD_INFO */
 116 #endif /* CONFIG_LCD */
 117
 118 static void board_uart1_hw_init(void)
 119 {
 120         atmel_pio4_set_a_periph(AT91_PIO_PORTD, 2, 1);  /* URXD1 */
 121         atmel_pio4_set_a_periph(AT91_PIO_PORTD, 3, 0);  /* UTXD1 */
 122
 123         at91_periph_clk_enable(ATMEL_ID_UART1);
 124 }
 125
 126 #ifdef CONFIG_DEBUG_UART_BOARD_INIT
 127 void board_debug_uart_init(void)
 128 {
 129         board_uart1_hw_init();
 130 }
 131 #endif
 132
 133 #ifdef CONFIG_BOARD_EARLY_INIT_F
 134 int board_early_init_f(void)
 135 {
 136 #ifdef CONFIG_DEBUG_UART
 137         debug_uart_init();
 138 #else
 139         board_uart1_hw_init();
 140 #endif
 141
 142         return 0;
 143 }
 144 #endif
 145
 146 int board_init(void)
 147 {
 148         /* address of boot parameters */
 149         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 150
 151 #ifdef CONFIG_LCD
 152         board_lcd_hw_init();
 153 #endif
 154 #ifdef CONFIG_CMD_USB
 155         board_usb_hw_init();
 156 #endif
 157
 158         return 0;
 159 }
 160
 161 int dram_init(void)
 162 {
 163         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
 164                                     CONFIG_SYS_SDRAM_SIZE);
 165         return 0;
 166 }
 167
 168 #ifdef CONFIG_CMD_I2C
 169 static int set_ethaddr_from_eeprom(void)
 170 {
 171         const int ETH_ADDR_LEN = 6;
 172         unsigned char ethaddr[ETH_ADDR_LEN];
 173         const char *ETHADDR_NAME = "ethaddr";
 174         struct udevice *bus, *dev;
 175
 176         if (getenv(ETHADDR_NAME))
 177                 return 0;
 178
 179         if (uclass_get_device_by_seq(UCLASS_I2C, 1, &bus)) {
 180                 printf("Cannot find I2C bus 1\n");
 181                 return -1;
 182         }
 183
 184         if (dm_i2c_probe(bus, AT24MAC_ADDR, 0, &dev)) {
 185                 printf("Failed to probe I2C chip\n");
 186                 return -1;
 187         }
 188
 189         if (dm_i2c_read(dev, AT24MAC_REG, ethaddr, ETH_ADDR_LEN)) {
 190                 printf("Failed to read ethernet address from EEPROM\n");
 191                 return -1;
 192         }
 193
 194         if (!is_valid_ethaddr(ethaddr)) {
 195                 printf("The ethernet address read from EEPROM is not valid!\n");
 196                 return -1;
 197         }
 198
 199         return eth_setenv_enetaddr(ETHADDR_NAME, ethaddr);
 200 }
 201 #else
 202 static int set_ethaddr_from_eeprom(void)
 203 {
 204         return 0;
 205 }
 206 #endif
 207
 208 #ifdef CONFIG_MISC_INIT_R
 209 int misc_init_r(void)
 210 {
 211         set_ethaddr_from_eeprom();
 212
 213         return 0;
 214 }
 215 #endif
 216
 217 /* SPL */
 218 #ifdef CONFIG_SPL_BUILD
 219 void spl_board_init(void)
 220 {
 221 }
 222
 223 static void ddrc_conf(struct atmel_mpddrc_config *ddrc)
 224 {
 225         ddrc->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR3_SDRAM);
 226
 227         ddrc->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
 228                     ATMEL_MPDDRC_CR_NR_ROW_14 |
 229                     ATMEL_MPDDRC_CR_CAS_DDR_CAS5 |
 230                     ATMEL_MPDDRC_CR_DIC_DS |
 231                     ATMEL_MPDDRC_CR_DIS_DLL |
 232                     ATMEL_MPDDRC_CR_NB_8BANKS |
 233                     ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
 234                     ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
 235
 236         ddrc->rtr = 0x511;
 237
 238         ddrc->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
 239                       3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
 240                       4 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
 241                       9 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
 242                       3 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
 243                       4 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
 244                       4 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
 245                       4 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
 246
 247         ddrc->tpr1 = (27 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET |
 248                       29 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
 249                       0 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
 250                       3 << ATMEL_MPDDRC_TPR1_TXP_OFFSET);
 251
 252         ddrc->tpr2 = (0 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET |
 253                       0 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
 254                       0 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
 255                       4 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
 256                       7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET);
 257 }
 258
 259 void mem_init(void)
 260 {
 261         struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
 262         struct atmel_mpddr *mpddrc = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC;
 263         struct atmel_mpddrc_config ddrc_config;
 264         u32 reg;
 265
 266         ddrc_conf(&ddrc_config);
 267
 268         at91_periph_clk_enable(ATMEL_ID_MPDDRC);
 269         writel(AT91_PMC_DDR, &pmc->scer);
 270
 271         reg = readl(&mpddrc->io_calibr);
 272         reg &= ~ATMEL_MPDDRC_IO_CALIBR_RDIV;
 273         reg |= ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_55;
 274         reg &= ~ATMEL_MPDDRC_IO_CALIBR_TZQIO;
 275         reg |= ATMEL_MPDDRC_IO_CALIBR_TZQIO_(100);
 276         writel(reg, &mpddrc->io_calibr);
 277
 278         writel(ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_TWO_CYCLE,
 279                &mpddrc->rd_data_path);
 280
 281         ddr3_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddrc_config);
 282
 283         writel(0x3, &mpddrc->cal_mr4);
 284         writel(64, &mpddrc->tim_cal);
 285 }
 286
 287 void at91_pmc_init(void)
 288 {
 289         struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
 290         u32 tmp;
 291
 292         tmp = AT91_PMC_PLLAR_29 |
 293               AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
 294               AT91_PMC_PLLXR_MUL(82) |
 295               AT91_PMC_PLLXR_DIV(1);
 296         at91_plla_init(tmp);
 297
 298         writel(0x0 << 8, &pmc->pllicpr);
 299
 300         tmp = AT91_PMC_MCKR_H32MXDIV |
 301               AT91_PMC_MCKR_PLLADIV_2 |
 302               AT91_PMC_MCKR_MDIV_3 |
 303               AT91_PMC_MCKR_CSS_PLLA;
 304         at91_mck_init(tmp);
 305 }
 306 #endif