1 /* Configuration header file for Gaisler Research AB's Template
2 * design (GPL Open Source SPARC/LEON3 96MHz) for Altera NIOS
3 * Development board Stratix II edition, with the FPGA device
6 * (C) Copyright 2003-2005
12 * SPDX-License-Identifier: GPL-2.0+
18 #define CONFIG_DISPLAY_BOARDINFO
21 * High Level Configuration Options
25 /* Altera NIOS Development board, Stratix II board */
26 #define CONFIG_GR_EP2S60 1
28 /* CPU / AMBA BUS configuration */
29 #define CONFIG_SYS_CLK_FREQ 96000000 /* 96MHz */
31 /* Define this is the GR-2S60-MEZZ mezzanine is available and you
32 * want to use the USB and GRETH functionality of the board
42 * Serial console configuration
44 #define CONFIG_BAUDRATE 38400 /* ... at 38400 bps */
45 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
48 #define CONFIG_DOS_PARTITION
49 #define CONFIG_MAC_PARTITION
50 #define CONFIG_ISO_PARTITION
55 #define CONFIG_CMD_REGINFO
56 #define CONFIG_CMD_DIAG
57 #define CONFIG_CMD_IRQ
61 #define CONFIG_USB_UHCI
62 /* Enable needed helper functions */
63 #define CONFIG_SYS_STDIO_DEREGISTER /* needs stdio_deregister */
70 #define CONFIG_PREBOOT "echo;" \
71 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
74 #undef CONFIG_BOOTARGS
76 #define CONFIG_EXTRA_ENV_SETTINGS \
78 "nfsargs=setenv bootargs console=ttyS0,38400 root=/dev/nfs rw " \
79 "nfsroot=${serverip}:${rootpath}\0" \
80 "ramargs=setenv bootargs console=ttyS0,${baudrate} root=/dev/ram rw\0" \
81 "addip=setenv bootargs ${bootargs} " \
82 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
83 ":${hostname}:${netdev}:off panic=1\0" \
84 "flash_nfs=run nfsargs addip;" \
85 "bootm ${kernel_addr}\0" \
86 "flash_self=run ramargs addip;" \
87 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
88 "net_nfs=tftp 40000000 ${bootfile};run nfsargs addip;bootm\0" \
89 "scratch=40800000\0" \
90 "getkernel=tftpboot $(scratch) $(bootfile)\0" \
91 "bootargs=console=ttyS0,38400 root=/dev/nfs rw nfsroot=192.168.0.20:/export/rootfs ip=192.168.0.207:192.168.0.20:192.168.0.1:255.255.255.0:ml401:eth0\0" \
94 #define CONFIG_NETMASK 255.255.255.0
95 #define CONFIG_GATEWAYIP 192.168.0.1
96 #define CONFIG_SERVERIP 192.168.0.20
97 #define CONFIG_IPADDR 192.168.0.207
98 #define CONFIG_ROOTPATH "/export/rootfs"
99 #define CONFIG_HOSTNAME ml401
100 #define CONFIG_BOOTFILE "/uImage"
102 #define CONFIG_BOOTCOMMAND "run flash_self"
107 * |--------------------------------|
108 * | 0x00000000 Text & Data & BSS | *
110 * | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~| *
111 * | UNUSED / Growth | * 256kb
112 * |--------------------------------|
113 * | 0x00050000 Base custom area | *
115 * | | * Rest of Flash
116 * |~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~|
117 * | END-0x00008000 Environment | * 32kb
118 * |--------------------------------|
123 * |--------------------------------|
124 * | UNUSED / scratch area |
129 * |--------------------------------|
130 * | Monitor .Text / .DATA / .BSS | * 512kb
132 * |--------------------------------|
133 * | Monitor Malloc | * 128kb (contains relocated environment)
134 * |--------------------------------|
135 * | Monitor/kernel STACK | * 64kb
136 * |--------------------------------|
137 * | Page Table for MMU systems | * 2k
138 * |--------------------------------|
139 * | PROM Code accessed from Linux | * 6kb-128b
140 * |--------------------------------|
141 * | Global data (avail from kernel)| * 128b
142 * |--------------------------------|
147 * Flash configuration (8,16 or 32 MB)
148 * TEXT base always at 0xFFF00000
149 * ENV_ADDR always at 0xFFF40000
150 * FLASH_BASE at 0xFC000000 for 64 MB
151 * 0xFE000000 for 32 MB
152 * 0xFF000000 for 16 MB
153 * 0xFF800000 for 8 MB
155 /*#define CONFIG_SYS_NO_FLASH 1*/
156 #define CONFIG_SYS_FLASH_BASE 0x00000000
157 #define CONFIG_SYS_FLASH_SIZE 0x00400000 /* FPGA Bit file is in top of FLASH, we only ues the bottom 4Mb */
159 #define PHYS_FLASH_SECT_SIZE 0x00010000 /* 64 KB sectors */
160 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */
161 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
163 #define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
164 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
165 #define CONFIG_SYS_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */
166 #define CONFIG_SYS_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */
167 #define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
170 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT
171 #define CONFIG_FLASH_CFI_DRIVER
172 #define CONFIG_SYS_FLASH_CFI
173 /* Bypass cache when reading regs from flash memory */
174 #define CONFIG_SYS_FLASH_CFI_BYPASS_READ
175 /* Buffered writes (32byte/go) instead of single accesses */
176 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
179 * Environment settings
181 /*#define CONFIG_ENV_IS_NOWHERE 1*/
182 #define CONFIG_ENV_IS_IN_FLASH 1
183 /* CONFIG_ENV_ADDR need to be at sector boundary */
184 #define CONFIG_ENV_SIZE 0x8000
185 #define CONFIG_ENV_SECT_SIZE 0x20000
186 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+CONFIG_SYS_FLASH_SIZE-CONFIG_ENV_SECT_SIZE)
187 #define CONFIG_ENV_OVERWRITE 1
192 #define CONFIG_SYS_SDRAM_BASE 0x40000000
193 #define CONFIG_SYS_SDRAM_SIZE 0x02000000
194 #define CONFIG_SYS_SDRAM_END (CONFIG_SYS_SDRAM_BASE+CONFIG_SYS_SDRAM_SIZE)
196 /* no SRAM available */
197 #undef CONFIG_SYS_SRAM_BASE
198 #undef CONFIG_SYS_SRAM_SIZE
200 #define CONFIG_SYS_RAM_BASE CONFIG_SYS_SDRAM_BASE
201 #define CONFIG_SYS_RAM_SIZE CONFIG_SYS_SDRAM_SIZE
202 #define CONFIG_SYS_RAM_END CONFIG_SYS_SDRAM_END
204 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_SDRAM_END - GENERATED_GBL_DATA_SIZE)
206 #define CONFIG_SYS_PROM_SIZE (8192-GENERATED_GBL_DATA_SIZE)
207 #define CONFIG_SYS_PROM_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET-CONFIG_SYS_PROM_SIZE)
209 #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_PROM_OFFSET-32)
210 #define CONFIG_SYS_STACK_SIZE (0x10000-32)
212 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
213 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
214 # define CONFIG_SYS_RAMBOOT 1
217 #define CONFIG_SYS_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */
218 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
219 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
221 #define CONFIG_SYS_MALLOC_END (CONFIG_SYS_INIT_SP_OFFSET-CONFIG_SYS_STACK_SIZE)
222 #define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MALLOC_END-CONFIG_SYS_MALLOC_LEN)
224 /* relocated monitor area */
225 #define CONFIG_SYS_RELOC_MONITOR_MAX_END CONFIG_SYS_MALLOC_BASE
226 #define CONFIG_SYS_RELOC_MONITOR_BASE (CONFIG_SYS_RELOC_MONITOR_MAX_END-CONFIG_SYS_MONITOR_LEN)
228 /* make un relocated address from relocated address */
229 #define UN_RELOC(address) (address-(CONFIG_SYS_RELOC_MONITOR_BASE-CONFIG_SYS_TEXT_BASE))
232 * Ethernet configuration uses on board SMC91C111, however if a mezzanine
233 * with a PHY is attached the GRETH can be used on this board.
234 * Define USE_GRETH in order to use the mezzanine provided PHY with the
235 * onchip GRETH network MAC, note that this is not supported by the
240 /* USE SMC91C111 MAC */
241 #define CONFIG_SMC91111 1
242 #define CONFIG_SMC91111_BASE 0x20000300 /* chip select 3 */
243 #define CONFIG_SMC_USE_32_BIT 1 /* 32 bit bus */
244 #undef CONFIG_SMC_91111_EXT_PHY /* we use internal phy */
245 /*#define CONFIG_SHOW_ACTIVITY*/
246 #define CONFIG_NET_RETRY_COUNT 10 /* # of retries */
250 /* USE GRETH Ethernet Driver */
251 #define CONFIG_GRETH 1
254 #define CONFIG_PHY_ADDR 0x00
257 * Miscellaneous configurable options
259 #define CONFIG_SYS_LONGHELP /* undef to save memory */
260 #if defined(CONFIG_CMD_KGDB)
261 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
263 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
265 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
266 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
267 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
269 #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
270 #define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
272 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
274 /*-----------------------------------------------------------------------
276 *-----------------------------------------------------------------------
278 #define CONFIG_USB_CLOCK 0x0001BBBB
279 #define CONFIG_USB_CONFIG 0x00005000
281 /***** Gaisler GRLIB IP-Cores Config ********/
283 #define CONFIG_SYS_GRLIB_SDRAM 0
285 /* No SDRAM Configuration */
286 #undef CONFIG_SYS_GRLIB_GAISLER_SDCTRL1
288 /* See, GRLIB Docs (grip.pdf) on how to set up
289 * These the memory controller registers.
291 #define CONFIG_SYS_GRLIB_ESA_MCTRL1
292 #define CONFIG_SYS_GRLIB_ESA_MCTRL1_CFG1 (0x10f800ff | (1<<11))
293 #define CONFIG_SYS_GRLIB_ESA_MCTRL1_CFG2 0x00000000
294 #define CONFIG_SYS_GRLIB_ESA_MCTRL1_CFG3 0x00000000
296 /* GRLIB FT-MCTRL configuration */
297 #define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1
298 #define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1_CFG1 (0x10f800ff | (1<<11))
299 #define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1_CFG2 0x00000000
300 #define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1_CFG3 0x00000000
303 #define CONFIG_SYS_GRLIB_GAISLER_DDRSPA1
304 #define CONFIG_SYS_GRLIB_GAISLER_DDRSPA1_CTRL 0xa900830a
306 /* no DDR2 Controller */
307 #undef CONFIG_SYS_GRLIB_GAISLER_DDR2SPA1
309 /* default kernel command line */
310 #define CONFIG_DEFAULT_KERNEL_COMMAND_LINE "console=ttyS0,38400\0\0"
312 #endif /* __CONFIG_H */