drivers/ram/rockchip/sdram_rk3399.c

   1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
   2 /*
   3  * (C) Copyright 2016-2017 Rockchip Inc.
   4  *
   5  * Adapted from coreboot.
   6  */
   7
   8 #include <common.h>
   9 #include <clk.h>
  10 #include <dm.h>
  11 #include <dt-structs.h>
  12 #include <ram.h>
  13 #include <regmap.h>
  14 #include <syscon.h>
  15 #include <asm/io.h>
  16 #include <asm/arch-rockchip/clock.h>
  17 #include <asm/arch-rockchip/cru_rk3399.h>
  18 #include <asm/arch-rockchip/grf_rk3399.h>
  19 #include <asm/arch-rockchip/hardware.h>
  20 #include <asm/arch-rockchip/sdram_common.h>
  21 #include <asm/arch-rockchip/sdram_rk3399.h>
  22 #include <linux/err.h>
  23 #include <time.h>
  24
  25 #define PRESET_SGRF_HOLD(n)     ((0x1 << (6 + 16)) | ((n) << 6))
  26 #define PRESET_GPIO0_HOLD(n)    ((0x1 << (7 + 16)) | ((n) << 7))
  27 #define PRESET_GPIO1_HOLD(n)    ((0x1 << (8 + 16)) | ((n) << 8))
  28
  29 #define PHY_DRV_ODT_HI_Z        0x0
  30 #define PHY_DRV_ODT_240         0x1
  31 #define PHY_DRV_ODT_120         0x8
  32 #define PHY_DRV_ODT_80          0x9
  33 #define PHY_DRV_ODT_60          0xc
  34 #define PHY_DRV_ODT_48          0xd
  35 #define PHY_DRV_ODT_40          0xe
  36 #define PHY_DRV_ODT_34_3        0xf
  37
  38 struct chan_info {
  39         struct rk3399_ddr_pctl_regs *pctl;
  40         struct rk3399_ddr_pi_regs *pi;
  41         struct rk3399_ddr_publ_regs *publ;
  42         struct rk3399_msch_regs *msch;
  43 };
  44
  45 struct dram_info {
  46 #if defined(CONFIG_TPL_BUILD) || \
  47         (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
  48         struct chan_info chan[2];
  49         struct clk ddr_clk;
  50         struct rk3399_cru *cru;
  51         struct rk3399_pmucru *pmucru;
  52         struct rk3399_pmusgrf_regs *pmusgrf;
  53         struct rk3399_ddr_cic_regs *cic;
  54 #endif
  55         struct ram_info info;
  56         struct rk3399_pmugrf_regs *pmugrf;
  57 };
  58
  59 #if defined(CONFIG_TPL_BUILD) || \
  60         (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
  61
  62 struct rockchip_dmc_plat {
  63 #if CONFIG_IS_ENABLED(OF_PLATDATA)
  64         struct dtd_rockchip_rk3399_dmc dtplat;
  65 #else
  66         struct rk3399_sdram_params sdram_params;
  67 #endif
  68         struct regmap *map;
  69 };
  70
  71 static void copy_to_reg(u32 *dest, const u32 *src, u32 n)
  72 {
  73         int i;
  74
  75         for (i = 0; i < n / sizeof(u32); i++) {
  76                 writel(*src, dest);
  77                 src++;
  78                 dest++;
  79         }
  80 }
  81
  82 static void phy_dll_bypass_set(struct rk3399_ddr_publ_regs *ddr_publ_regs,
  83                                u32 freq)
  84 {
  85         u32 *denali_phy = ddr_publ_regs->denali_phy;
  86
  87         /* From IP spec, only freq small than 125 can enter dll bypass mode */
  88         if (freq <= 125) {
  89                 /* phy_sw_master_mode_X PHY_86/214/342/470 4bits offset_8 */
  90                 setbits_le32(&denali_phy[86], (0x3 << 2) << 8);
  91                 setbits_le32(&denali_phy[214], (0x3 << 2) << 8);
  92                 setbits_le32(&denali_phy[342], (0x3 << 2) << 8);
  93                 setbits_le32(&denali_phy[470], (0x3 << 2) << 8);
  94
  95                 /* phy_adrctl_sw_master_mode PHY_547/675/803 4bits offset_16 */
  96                 setbits_le32(&denali_phy[547], (0x3 << 2) << 16);
  97                 setbits_le32(&denali_phy[675], (0x3 << 2) << 16);
  98                 setbits_le32(&denali_phy[803], (0x3 << 2) << 16);
  99         } else {
 100                 /* phy_sw_master_mode_X PHY_86/214/342/470 4bits offset_8 */
 101                 clrbits_le32(&denali_phy[86], (0x3 << 2) << 8);
 102                 clrbits_le32(&denali_phy[214], (0x3 << 2) << 8);
 103                 clrbits_le32(&denali_phy[342], (0x3 << 2) << 8);
 104                 clrbits_le32(&denali_phy[470], (0x3 << 2) << 8);
 105
 106                 /* phy_adrctl_sw_master_mode PHY_547/675/803 4bits offset_16 */
 107                 clrbits_le32(&denali_phy[547], (0x3 << 2) << 16);
 108                 clrbits_le32(&denali_phy[675], (0x3 << 2) << 16);
 109                 clrbits_le32(&denali_phy[803], (0x3 << 2) << 16);
 110         }
 111 }
 112
 113 static void set_memory_map(const struct chan_info *chan, u32 channel,
 114                            const struct rk3399_sdram_params *params)
 115 {
 116         const struct rk3399_sdram_channel *sdram_ch = &params->ch[channel];
 117         u32 *denali_ctl = chan->pctl->denali_ctl;
 118         u32 *denali_pi = chan->pi->denali_pi;
 119         u32 cs_map;
 120         u32 reduc;
 121         u32 row;
 122
 123         /* Get row number from ddrconfig setting */
 124         if (sdram_ch->ddrconfig < 2 || sdram_ch->ddrconfig == 4)
 125                 row = 16;
 126         else if (sdram_ch->ddrconfig == 3)
 127                 row = 14;
 128         else
 129                 row = 15;
 130
 131         cs_map = (sdram_ch->rank > 1) ? 3 : 1;
 132         reduc = (sdram_ch->bw == 2) ? 0 : 1;
 133
 134         /* Set the dram configuration to ctrl */
 135         clrsetbits_le32(&denali_ctl[191], 0xF, (12 - sdram_ch->col));
 136         clrsetbits_le32(&denali_ctl[190], (0x3 << 16) | (0x7 << 24),
 137                         ((3 - sdram_ch->bk) << 16) |
 138                         ((16 - row) << 24));
 139
 140         clrsetbits_le32(&denali_ctl[196], 0x3 | (1 << 16),
 141                         cs_map | (reduc << 16));
 142
 143         /* PI_199 PI_COL_DIFF:RW:0:4 */
 144         clrsetbits_le32(&denali_pi[199], 0xF, (12 - sdram_ch->col));
 145
 146         /* PI_155 PI_ROW_DIFF:RW:24:3 PI_BANK_DIFF:RW:16:2 */
 147         clrsetbits_le32(&denali_pi[155], (0x3 << 16) | (0x7 << 24),
 148                         ((3 - sdram_ch->bk) << 16) |
 149                         ((16 - row) << 24));
 150         /* PI_41 PI_CS_MAP:RW:24:4 */
 151         clrsetbits_le32(&denali_pi[41], 0xf << 24, cs_map << 24);
 152         if (sdram_ch->rank == 1 && params->base.dramtype == DDR3)
 153                 writel(0x2EC7FFFF, &denali_pi[34]);
 154 }
 155
 156 static void set_ds_odt(const struct chan_info *chan,
 157                        const struct rk3399_sdram_params *params)
 158 {
 159         u32 *denali_phy = chan->publ->denali_phy;
 160
 161         u32 tsel_idle_en, tsel_wr_en, tsel_rd_en;
 162         u32 tsel_idle_select_p, tsel_wr_select_dq_p, tsel_rd_select_p;
 163         u32 ca_tsel_wr_select_p, tsel_wr_select_ca_n;
 164         u32 tsel_idle_select_n, tsel_wr_select_dq_n, tsel_rd_select_n;
 165         u32 reg_value;
 166
 167         if (params->base.dramtype == LPDDR4) {
 168                 tsel_rd_select_p = PHY_DRV_ODT_HI_Z;
 169                 tsel_wr_select_dq_p = PHY_DRV_ODT_40;
 170                 ca_tsel_wr_select_p = PHY_DRV_ODT_40;
 171                 tsel_idle_select_p = PHY_DRV_ODT_HI_Z;
 172
 173                 tsel_rd_select_n = PHY_DRV_ODT_240;
 174                 tsel_wr_select_dq_n = PHY_DRV_ODT_40;
 175                 tsel_wr_select_ca_n = PHY_DRV_ODT_40;
 176                 tsel_idle_select_n = PHY_DRV_ODT_240;
 177         } else if (params->base.dramtype == LPDDR3) {
 178                 tsel_rd_select_p = PHY_DRV_ODT_240;
 179                 tsel_wr_select_dq_p = PHY_DRV_ODT_34_3;
 180                 ca_tsel_wr_select_p = PHY_DRV_ODT_48;
 181                 tsel_idle_select_p = PHY_DRV_ODT_240;
 182
 183                 tsel_rd_select_n = PHY_DRV_ODT_HI_Z;
 184                 tsel_wr_select_dq_n = PHY_DRV_ODT_34_3;
 185                 tsel_wr_select_ca_n = PHY_DRV_ODT_48;
 186                 tsel_idle_select_n = PHY_DRV_ODT_HI_Z;
 187         } else {
 188                 tsel_rd_select_p = PHY_DRV_ODT_240;
 189                 tsel_wr_select_dq_p = PHY_DRV_ODT_34_3;
 190                 ca_tsel_wr_select_p = PHY_DRV_ODT_34_3;
 191                 tsel_idle_select_p = PHY_DRV_ODT_240;
 192
 193                 tsel_rd_select_n = PHY_DRV_ODT_240;
 194                 tsel_wr_select_dq_n = PHY_DRV_ODT_34_3;
 195                 tsel_wr_select_ca_n = PHY_DRV_ODT_34_3;
 196                 tsel_idle_select_n = PHY_DRV_ODT_240;
 197         }
 198
 199         if (params->base.odt == 1)
 200                 tsel_rd_en = 1;
 201         else
 202                 tsel_rd_en = 0;
 203
 204         tsel_wr_en = 0;
 205         tsel_idle_en = 0;
 206
 207         /*
 208          * phy_dq_tsel_select_X 24bits DENALI_PHY_6/134/262/390 offset_0
 209          * sets termination values for read/idle cycles and drive strength
 210          * for write cycles for DQ/DM
 211          */
 212         reg_value = tsel_rd_select_n | (tsel_rd_select_p << 0x4) |
 213                     (tsel_wr_select_dq_n << 8) | (tsel_wr_select_dq_p << 12) |
 214                     (tsel_idle_select_n << 16) | (tsel_idle_select_p << 20);
 215         clrsetbits_le32(&denali_phy[6], 0xffffff, reg_value);
 216         clrsetbits_le32(&denali_phy[134], 0xffffff, reg_value);
 217         clrsetbits_le32(&denali_phy[262], 0xffffff, reg_value);
 218         clrsetbits_le32(&denali_phy[390], 0xffffff, reg_value);
 219
 220         /*
 221          * phy_dqs_tsel_select_X 24bits DENALI_PHY_7/135/263/391 offset_0
 222          * sets termination values for read/idle cycles and drive strength
 223          * for write cycles for DQS
 224          */
 225         clrsetbits_le32(&denali_phy[7], 0xffffff, reg_value);
 226         clrsetbits_le32(&denali_phy[135], 0xffffff, reg_value);
 227         clrsetbits_le32(&denali_phy[263], 0xffffff, reg_value);
 228         clrsetbits_le32(&denali_phy[391], 0xffffff, reg_value);
 229
 230         /* phy_adr_tsel_select_ 8bits DENALI_PHY_544/672/800 offset_0 */
 231         reg_value = tsel_wr_select_ca_n | (ca_tsel_wr_select_p << 0x4);
 232         clrsetbits_le32(&denali_phy[544], 0xff, reg_value);
 233         clrsetbits_le32(&denali_phy[672], 0xff, reg_value);
 234         clrsetbits_le32(&denali_phy[800], 0xff, reg_value);
 235
 236         /* phy_pad_addr_drive 8bits DENALI_PHY_928 offset_0 */
 237         clrsetbits_le32(&denali_phy[928], 0xff, reg_value);
 238
 239         /* phy_pad_rst_drive 8bits DENALI_PHY_937 offset_0 */
 240         clrsetbits_le32(&denali_phy[937], 0xff, reg_value);
 241
 242         /* phy_pad_cke_drive 8bits DENALI_PHY_935 offset_0 */
 243         clrsetbits_le32(&denali_phy[935], 0xff, reg_value);
 244
 245         /* phy_pad_cs_drive 8bits DENALI_PHY_939 offset_0 */
 246         clrsetbits_le32(&denali_phy[939], 0xff, reg_value);
 247
 248         /* phy_pad_clk_drive 8bits DENALI_PHY_929 offset_0 */
 249         clrsetbits_le32(&denali_phy[929], 0xff, reg_value);
 250
 251         /* phy_pad_fdbk_drive 23bit DENALI_PHY_924/925 */
 252         clrsetbits_le32(&denali_phy[924], 0xff,
 253                         tsel_wr_select_dq_n | (tsel_wr_select_dq_p << 4));
 254         clrsetbits_le32(&denali_phy[925], 0xff,
 255                         tsel_rd_select_n | (tsel_rd_select_p << 4));
 256
 257         /* phy_dq_tsel_enable_X 3bits DENALI_PHY_5/133/261/389 offset_16 */
 258         reg_value = (tsel_rd_en | (tsel_wr_en << 1) | (tsel_idle_en << 2))
 259                 << 16;
 260         clrsetbits_le32(&denali_phy[5], 0x7 << 16, reg_value);
 261         clrsetbits_le32(&denali_phy[133], 0x7 << 16, reg_value);
 262         clrsetbits_le32(&denali_phy[261], 0x7 << 16, reg_value);
 263         clrsetbits_le32(&denali_phy[389], 0x7 << 16, reg_value);
 264
 265         /* phy_dqs_tsel_enable_X 3bits DENALI_PHY_6/134/262/390 offset_24 */
 266         reg_value = (tsel_rd_en | (tsel_wr_en << 1) | (tsel_idle_en << 2))
 267                 << 24;
 268         clrsetbits_le32(&denali_phy[6], 0x7 << 24, reg_value);
 269         clrsetbits_le32(&denali_phy[134], 0x7 << 24, reg_value);
 270         clrsetbits_le32(&denali_phy[262], 0x7 << 24, reg_value);
 271         clrsetbits_le32(&denali_phy[390], 0x7 << 24, reg_value);
 272
 273         /* phy_adr_tsel_enable_ 1bit DENALI_PHY_518/646/774 offset_8 */
 274         reg_value = tsel_wr_en << 8;
 275         clrsetbits_le32(&denali_phy[518], 0x1 << 8, reg_value);
 276         clrsetbits_le32(&denali_phy[646], 0x1 << 8, reg_value);
 277         clrsetbits_le32(&denali_phy[774], 0x1 << 8, reg_value);
 278
 279         /* phy_pad_addr_term tsel 1bit DENALI_PHY_933 offset_17 */
 280         reg_value = tsel_wr_en << 17;
 281         clrsetbits_le32(&denali_phy[933], 0x1 << 17, reg_value);
 282         /*
 283          * pad_rst/cke/cs/clk_term tsel 1bits
 284          * DENALI_PHY_938/936/940/934 offset_17
 285          */
 286         clrsetbits_le32(&denali_phy[938], 0x1 << 17, reg_value);
 287         clrsetbits_le32(&denali_phy[936], 0x1 << 17, reg_value);
 288         clrsetbits_le32(&denali_phy[940], 0x1 << 17, reg_value);
 289         clrsetbits_le32(&denali_phy[934], 0x1 << 17, reg_value);
 290
 291         /* phy_pad_fdbk_term 1bit DENALI_PHY_930 offset_17 */
 292         clrsetbits_le32(&denali_phy[930], 0x1 << 17, reg_value);
 293 }
 294
 295 static int phy_io_config(const struct chan_info *chan,
 296                          const struct rk3399_sdram_params *params)
 297 {
 298         u32 *denali_phy = chan->publ->denali_phy;
 299         u32 vref_mode_dq, vref_value_dq, vref_mode_ac, vref_value_ac;
 300         u32 mode_sel;
 301         u32 reg_value;
 302         u32 drv_value, odt_value;
 303         u32 speed;
 304
 305         /* vref setting */
 306         if (params->base.dramtype == LPDDR4) {
 307                 /* LPDDR4 */
 308                 vref_mode_dq = 0x6;
 309                 vref_value_dq = 0x1f;
 310                 vref_mode_ac = 0x6;
 311                 vref_value_ac = 0x1f;
 312         } else if (params->base.dramtype == LPDDR3) {
 313                 if (params->base.odt == 1) {
 314                         vref_mode_dq = 0x5;  /* LPDDR3 ODT */
 315                         drv_value = (readl(&denali_phy[6]) >> 12) & 0xf;
 316                         odt_value = (readl(&denali_phy[6]) >> 4) & 0xf;
 317                         if (drv_value == PHY_DRV_ODT_48) {
 318                                 switch (odt_value) {
 319                                 case PHY_DRV_ODT_240:
 320                                         vref_value_dq = 0x16;
 321                                         break;
 322                                 case PHY_DRV_ODT_120:
 323                                         vref_value_dq = 0x26;
 324                                         break;
 325                                 case PHY_DRV_ODT_60:
 326                                         vref_value_dq = 0x36;
 327                                         break;
 328                                 default:
 329                                         debug("Invalid ODT value.\n");
 330                                         return -EINVAL;
 331                                 }
 332                         } else if (drv_value == PHY_DRV_ODT_40) {
 333                                 switch (odt_value) {
 334                                 case PHY_DRV_ODT_240:
 335                                         vref_value_dq = 0x19;
 336                                         break;
 337                                 case PHY_DRV_ODT_120:
 338                                         vref_value_dq = 0x23;
 339                                         break;
 340                                 case PHY_DRV_ODT_60:
 341                                         vref_value_dq = 0x31;
 342                                         break;
 343                                 default:
 344                                         debug("Invalid ODT value.\n");
 345                                         return -EINVAL;
 346                                 }
 347                         } else if (drv_value == PHY_DRV_ODT_34_3) {
 348                                 switch (odt_value) {
 349                                 case PHY_DRV_ODT_240:
 350                                         vref_value_dq = 0x17;
 351                                         break;
 352                                 case PHY_DRV_ODT_120:
 353                                         vref_value_dq = 0x20;
 354                                         break;
 355                                 case PHY_DRV_ODT_60:
 356                                         vref_value_dq = 0x2e;
 357                                         break;
 358                                 default:
 359                                         debug("Invalid ODT value.\n");
 360                                         return -EINVAL;
 361                                 }
 362                         } else {
 363                                 debug("Invalid DRV value.\n");
 364                                 return -EINVAL;
 365                         }
 366                 } else {
 367                         vref_mode_dq = 0x2;  /* LPDDR3 */
 368                         vref_value_dq = 0x1f;
 369                 }
 370                 vref_mode_ac = 0x2;
 371                 vref_value_ac = 0x1f;
 372         } else if (params->base.dramtype == DDR3) {
 373                 /* DDR3L */
 374                 vref_mode_dq = 0x1;
 375                 vref_value_dq = 0x1f;
 376                 vref_mode_ac = 0x1;
 377                 vref_value_ac = 0x1f;
 378         } else {
 379                 debug("Unknown DRAM type.\n");
 380                 return -EINVAL;
 381         }
 382
 383         reg_value = (vref_mode_dq << 9) | (0x1 << 8) | vref_value_dq;
 384
 385         /* PHY_913 PHY_PAD_VREF_CTRL_DQ_0 12bits offset_8 */
 386         clrsetbits_le32(&denali_phy[913], 0xfff << 8, reg_value << 8);
 387         /* PHY_914 PHY_PAD_VREF_CTRL_DQ_1 12bits offset_0 */
 388         clrsetbits_le32(&denali_phy[914], 0xfff, reg_value);
 389         /* PHY_914 PHY_PAD_VREF_CTRL_DQ_2 12bits offset_16 */
 390         clrsetbits_le32(&denali_phy[914], 0xfff << 16, reg_value << 16);
 391         /* PHY_915 PHY_PAD_VREF_CTRL_DQ_3 12bits offset_0 */
 392         clrsetbits_le32(&denali_phy[915], 0xfff, reg_value);
 393
 394         reg_value = (vref_mode_ac << 9) | (0x1 << 8) | vref_value_ac;
 395
 396         /* PHY_915 PHY_PAD_VREF_CTRL_AC 12bits offset_16 */
 397         clrsetbits_le32(&denali_phy[915], 0xfff << 16, reg_value << 16);
 398
 399         if (params->base.dramtype == LPDDR4)
 400                 mode_sel = 0x6;
 401         else if (params->base.dramtype == LPDDR3)
 402                 mode_sel = 0x0;
 403         else if (params->base.dramtype == DDR3)
 404                 mode_sel = 0x1;
 405         else
 406                 return -EINVAL;
 407
 408         /* PHY_924 PHY_PAD_FDBK_DRIVE */
 409         clrsetbits_le32(&denali_phy[924], 0x7 << 15, mode_sel << 15);
 410         /* PHY_926 PHY_PAD_DATA_DRIVE */
 411         clrsetbits_le32(&denali_phy[926], 0x7 << 6, mode_sel << 6);
 412         /* PHY_927 PHY_PAD_DQS_DRIVE */
 413         clrsetbits_le32(&denali_phy[927], 0x7 << 6, mode_sel << 6);
 414         /* PHY_928 PHY_PAD_ADDR_DRIVE */
 415         clrsetbits_le32(&denali_phy[928], 0x7 << 14, mode_sel << 14);
 416         /* PHY_929 PHY_PAD_CLK_DRIVE */
 417         clrsetbits_le32(&denali_phy[929], 0x7 << 14, mode_sel << 14);
 418         /* PHY_935 PHY_PAD_CKE_DRIVE */
 419         clrsetbits_le32(&denali_phy[935], 0x7 << 14, mode_sel << 14);
 420         /* PHY_937 PHY_PAD_RST_DRIVE */
 421         clrsetbits_le32(&denali_phy[937], 0x7 << 14, mode_sel << 14);
 422         /* PHY_939 PHY_PAD_CS_DRIVE */
 423         clrsetbits_le32(&denali_phy[939], 0x7 << 14, mode_sel << 14);
 424
 425         /* speed setting */
 426         if (params->base.ddr_freq < 400)
 427                 speed = 0x0;
 428         else if (params->base.ddr_freq < 800)
 429                 speed = 0x1;
 430         else if (params->base.ddr_freq < 1200)
 431                 speed = 0x2;
 432         else
 433                 speed = 0x3;
 434
 435         /* PHY_924 PHY_PAD_FDBK_DRIVE */
 436         clrsetbits_le32(&denali_phy[924], 0x3 << 21, speed << 21);
 437         /* PHY_926 PHY_PAD_DATA_DRIVE */
 438         clrsetbits_le32(&denali_phy[926], 0x3 << 9, speed << 9);
 439         /* PHY_927 PHY_PAD_DQS_DRIVE */
 440         clrsetbits_le32(&denali_phy[927], 0x3 << 9, speed << 9);
 441         /* PHY_928 PHY_PAD_ADDR_DRIVE */
 442         clrsetbits_le32(&denali_phy[928], 0x3 << 17, speed << 17);
 443         /* PHY_929 PHY_PAD_CLK_DRIVE */
 444         clrsetbits_le32(&denali_phy[929], 0x3 << 17, speed << 17);
 445         /* PHY_935 PHY_PAD_CKE_DRIVE */
 446         clrsetbits_le32(&denali_phy[935], 0x3 << 17, speed << 17);
 447         /* PHY_937 PHY_PAD_RST_DRIVE */
 448         clrsetbits_le32(&denali_phy[937], 0x3 << 17, speed << 17);
 449         /* PHY_939 PHY_PAD_CS_DRIVE */
 450         clrsetbits_le32(&denali_phy[939], 0x3 << 17, speed << 17);
 451
 452         return 0;
 453 }
 454
 455 static int pctl_cfg(const struct chan_info *chan, u32 channel,
 456                     const struct rk3399_sdram_params *params)
 457 {
 458         u32 *denali_ctl = chan->pctl->denali_ctl;
 459         u32 *denali_pi = chan->pi->denali_pi;
 460         u32 *denali_phy = chan->publ->denali_phy;
 461         const u32 *params_ctl = params->pctl_regs.denali_ctl;
 462         const u32 *params_phy = params->phy_regs.denali_phy;
 463         u32 tmp, tmp1, tmp2;
 464         u32 pwrup_srefresh_exit;
 465         int ret;
 466         const ulong timeout_ms = 200;
 467
 468         /*
 469          * work around controller bug:
 470          * Do not program DRAM_CLASS until NO_PHY_IND_TRAIN_INT is programmed
 471          */
 472         copy_to_reg(&denali_ctl[1], &params_ctl[1],
 473                     sizeof(struct rk3399_ddr_pctl_regs) - 4);
 474         writel(params_ctl[0], &denali_ctl[0]);
 475
 476         copy_to_reg(denali_pi, &params->pi_regs.denali_pi[0],
 477                     sizeof(struct rk3399_ddr_pi_regs));
 478
 479         /* rank count need to set for init */
 480         set_memory_map(chan, channel, params);
 481
 482         writel(params->phy_regs.denali_phy[910], &denali_phy[910]);
 483         writel(params->phy_regs.denali_phy[911], &denali_phy[911]);
 484         writel(params->phy_regs.denali_phy[912], &denali_phy[912]);
 485
 486         pwrup_srefresh_exit = readl(&denali_ctl[68]) & PWRUP_SREFRESH_EXIT;
 487         clrbits_le32(&denali_ctl[68], PWRUP_SREFRESH_EXIT);
 488
 489         /* PHY_DLL_RST_EN */
 490         clrsetbits_le32(&denali_phy[957], 0x3 << 24, 1 << 24);
 491
 492         setbits_le32(&denali_pi[0], START);
 493         setbits_le32(&denali_ctl[0], START);
 494
 495         /* Waiting for phy DLL lock */
 496         while (1) {
 497                 tmp = readl(&denali_phy[920]);
 498                 tmp1 = readl(&denali_phy[921]);
 499                 tmp2 = readl(&denali_phy[922]);
 500                 if ((((tmp >> 16) & 0x1) == 0x1) &&
 501                     (((tmp1 >> 16) & 0x1) == 0x1) &&
 502                     (((tmp1 >> 0) & 0x1) == 0x1) &&
 503                     (((tmp2 >> 0) & 0x1) == 0x1))
 504                         break;
 505         }
 506
 507         copy_to_reg(&denali_phy[896], &params_phy[896], (958 - 895) * 4);
 508         copy_to_reg(&denali_phy[0], &params_phy[0], (90 - 0 + 1) * 4);
 509         copy_to_reg(&denali_phy[128], &params_phy[128], (218 - 128 + 1) * 4);
 510         copy_to_reg(&denali_phy[256], &params_phy[256], (346 - 256 + 1) * 4);
 511         copy_to_reg(&denali_phy[384], &params_phy[384], (474 - 384 + 1) * 4);
 512         copy_to_reg(&denali_phy[512], &params_phy[512], (549 - 512 + 1) * 4);
 513         copy_to_reg(&denali_phy[640], &params_phy[640], (677 - 640 + 1) * 4);
 514         copy_to_reg(&denali_phy[768], &params_phy[768], (805 - 768 + 1) * 4);
 515         set_ds_odt(chan, params);
 516
 517         /*
 518          * phy_dqs_tsel_wr_timing_X 8bits DENALI_PHY_84/212/340/468 offset_8
 519          * dqs_tsel_wr_end[7:4] add Half cycle
 520          */
 521         tmp = (readl(&denali_phy[84]) >> 8) & 0xff;
 522         clrsetbits_le32(&denali_phy[84], 0xff << 8, (tmp + 0x10) << 8);
 523         tmp = (readl(&denali_phy[212]) >> 8) & 0xff;
 524         clrsetbits_le32(&denali_phy[212], 0xff << 8, (tmp + 0x10) << 8);
 525         tmp = (readl(&denali_phy[340]) >> 8) & 0xff;
 526         clrsetbits_le32(&denali_phy[340], 0xff << 8, (tmp + 0x10) << 8);
 527         tmp = (readl(&denali_phy[468]) >> 8) & 0xff;
 528         clrsetbits_le32(&denali_phy[468], 0xff << 8, (tmp + 0x10) << 8);
 529
 530         /*
 531          * phy_dqs_tsel_wr_timing_X 8bits DENALI_PHY_83/211/339/467 offset_8
 532          * dq_tsel_wr_end[7:4] add Half cycle
 533          */
 534         tmp = (readl(&denali_phy[83]) >> 16) & 0xff;
 535         clrsetbits_le32(&denali_phy[83], 0xff << 16, (tmp + 0x10) << 16);
 536         tmp = (readl(&denali_phy[211]) >> 16) & 0xff;
 537         clrsetbits_le32(&denali_phy[211], 0xff << 16, (tmp + 0x10) << 16);
 538         tmp = (readl(&denali_phy[339]) >> 16) & 0xff;
 539         clrsetbits_le32(&denali_phy[339], 0xff << 16, (tmp + 0x10) << 16);
 540         tmp = (readl(&denali_phy[467]) >> 16) & 0xff;
 541         clrsetbits_le32(&denali_phy[467], 0xff << 16, (tmp + 0x10) << 16);
 542
 543         ret = phy_io_config(chan, params);
 544         if (ret)
 545                 return ret;
 546
 547         /* PHY_DLL_RST_EN */
 548         clrsetbits_le32(&denali_phy[957], 0x3 << 24, 0x2 << 24);
 549
 550         /* Waiting for PHY and DRAM init complete */
 551         tmp = get_timer(0);
 552         do {
 553                 if (get_timer(tmp) > timeout_ms) {
 554                         pr_err("DRAM (%s): phy failed to lock within  %ld ms\n",
 555                                __func__, timeout_ms);
 556                         return -ETIME;
 557                 }
 558         } while (!(readl(&denali_ctl[203]) & (1 << 3)));
 559         debug("DRAM (%s): phy locked after %ld ms\n", __func__, get_timer(tmp));
 560
 561         clrsetbits_le32(&denali_ctl[68], PWRUP_SREFRESH_EXIT,
 562                         pwrup_srefresh_exit);
 563         return 0;
 564 }
 565
 566 static void select_per_cs_training_index(const struct chan_info *chan,
 567                                          u32 rank)
 568 {
 569         u32 *denali_phy = chan->publ->denali_phy;
 570
 571         /* PHY_84 PHY_PER_CS_TRAINING_EN_0 1bit offset_16 */
 572         if ((readl(&denali_phy[84]) >> 16) & 1) {
 573                 /*
 574                  * PHY_8/136/264/392
 575                  * phy_per_cs_training_index_X 1bit offset_24
 576                  */
 577                 clrsetbits_le32(&denali_phy[8], 0x1 << 24, rank << 24);
 578                 clrsetbits_le32(&denali_phy[136], 0x1 << 24, rank << 24);
 579                 clrsetbits_le32(&denali_phy[264], 0x1 << 24, rank << 24);
 580                 clrsetbits_le32(&denali_phy[392], 0x1 << 24, rank << 24);
 581         }
 582 }
 583
 584 static void override_write_leveling_value(const struct chan_info *chan)
 585 {
 586         u32 *denali_ctl = chan->pctl->denali_ctl;
 587         u32 *denali_phy = chan->publ->denali_phy;
 588         u32 byte;
 589
 590         /* PHY_896 PHY_FREQ_SEL_MULTICAST_EN 1bit offset_0 */
 591         setbits_le32(&denali_phy[896], 1);
 592
 593         /*
 594          * PHY_8/136/264/392
 595          * phy_per_cs_training_multicast_en_X 1bit offset_16
 596          */
 597         clrsetbits_le32(&denali_phy[8], 0x1 << 16, 1 << 16);
 598         clrsetbits_le32(&denali_phy[136], 0x1 << 16, 1 << 16);
 599         clrsetbits_le32(&denali_phy[264], 0x1 << 16, 1 << 16);
 600         clrsetbits_le32(&denali_phy[392], 0x1 << 16, 1 << 16);
 601
 602         for (byte = 0; byte < 4; byte++)
 603                 clrsetbits_le32(&denali_phy[63 + (128 * byte)], 0xffff << 16,
 604                                 0x200 << 16);
 605
 606         /* PHY_896 PHY_FREQ_SEL_MULTICAST_EN 1bit offset_0 */
 607         clrbits_le32(&denali_phy[896], 1);
 608
 609         /* CTL_200 ctrlupd_req 1bit offset_8 */
 610         clrsetbits_le32(&denali_ctl[200], 0x1 << 8, 0x1 << 8);
 611 }
 612
 613 static int data_training_ca(const struct chan_info *chan, u32 channel,
 614                             const struct rk3399_sdram_params *params)
 615 {
 616         u32 *denali_pi = chan->pi->denali_pi;
 617         u32 *denali_phy = chan->publ->denali_phy;
 618         u32 i, tmp;
 619         u32 obs_0, obs_1, obs_2, obs_err = 0;
 620         u32 rank = params->ch[channel].rank;
 621
 622         for (i = 0; i < rank; i++) {
 623                 select_per_cs_training_index(chan, i);
 624
 625                 /* PI_100 PI_CALVL_EN:RW:8:2 */
 626                 clrsetbits_le32(&denali_pi[100], 0x3 << 8, 0x2 << 8);
 627
 628                 /* PI_92 PI_CALVL_REQ:WR:16:1,PI_CALVL_CS:RW:24:2 */
 629                 clrsetbits_le32(&denali_pi[92],
 630                                 (0x1 << 16) | (0x3 << 24),
 631                                 (0x1 << 16) | (i << 24));
 632
 633                 /* Waiting for training complete */
 634                 while (1) {
 635                         /* PI_174 PI_INT_STATUS:RD:8:18 */
 636                         tmp = readl(&denali_pi[174]) >> 8;
 637                         /*
 638                          * check status obs
 639                          * PHY_532/660/789 phy_adr_calvl_obs1_:0:32
 640                          */
 641                         obs_0 = readl(&denali_phy[532]);
 642                         obs_1 = readl(&denali_phy[660]);
 643                         obs_2 = readl(&denali_phy[788]);
 644                         if (((obs_0 >> 30) & 0x3) ||
 645                             ((obs_1 >> 30) & 0x3) ||
 646                             ((obs_2 >> 30) & 0x3))
 647                                 obs_err = 1;
 648                         if ((((tmp >> 11) & 0x1) == 0x1) &&
 649                             (((tmp >> 13) & 0x1) == 0x1) &&
 650                             (((tmp >> 5) & 0x1) == 0x0) &&
 651                             obs_err == 0)
 652                                 break;
 653                         else if ((((tmp >> 5) & 0x1) == 0x1) ||
 654                                  (obs_err == 1))
 655                                 return -EIO;
 656                 }
 657
 658                 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
 659                 writel(0x00003f7c, (&denali_pi[175]));
 660         }
 661
 662         clrbits_le32(&denali_pi[100], 0x3 << 8);
 663
 664         return 0;
 665 }
 666
 667 static int data_training_wl(const struct chan_info *chan, u32 channel,
 668                             const struct rk3399_sdram_params *params)
 669 {
 670         u32 *denali_pi = chan->pi->denali_pi;
 671         u32 *denali_phy = chan->publ->denali_phy;
 672         u32 i, tmp;
 673         u32 obs_0, obs_1, obs_2, obs_3, obs_err = 0;
 674         u32 rank = params->ch[channel].rank;
 675
 676         for (i = 0; i < rank; i++) {
 677                 select_per_cs_training_index(chan, i);
 678
 679                 /* PI_60 PI_WRLVL_EN:RW:8:2 */
 680                 clrsetbits_le32(&denali_pi[60], 0x3 << 8, 0x2 << 8);
 681
 682                 /* PI_59 PI_WRLVL_REQ:WR:8:1,PI_WRLVL_CS:RW:16:2 */
 683                 clrsetbits_le32(&denali_pi[59],
 684                                 (0x1 << 8) | (0x3 << 16),
 685                                 (0x1 << 8) | (i << 16));
 686
 687                 /* Waiting for training complete */
 688                 while (1) {
 689                         /* PI_174 PI_INT_STATUS:RD:8:18 */
 690                         tmp = readl(&denali_pi[174]) >> 8;
 691
 692                         /*
 693                          * check status obs, if error maybe can not
 694                          * get leveling done PHY_40/168/296/424
 695                          * phy_wrlvl_status_obs_X:0:13
 696                          */
 697                         obs_0 = readl(&denali_phy[40]);
 698                         obs_1 = readl(&denali_phy[168]);
 699                         obs_2 = readl(&denali_phy[296]);
 700                         obs_3 = readl(&denali_phy[424]);
 701                         if (((obs_0 >> 12) & 0x1) ||
 702                             ((obs_1 >> 12) & 0x1) ||
 703                             ((obs_2 >> 12) & 0x1) ||
 704                             ((obs_3 >> 12) & 0x1))
 705                                 obs_err = 1;
 706                         if ((((tmp >> 10) & 0x1) == 0x1) &&
 707                             (((tmp >> 13) & 0x1) == 0x1) &&
 708                             (((tmp >> 4) & 0x1) == 0x0) &&
 709                             obs_err == 0)
 710                                 break;
 711                         else if ((((tmp >> 4) & 0x1) == 0x1) ||
 712                                  (obs_err == 1))
 713                                 return -EIO;
 714                 }
 715
 716                 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
 717                 writel(0x00003f7c, (&denali_pi[175]));
 718         }
 719
 720         override_write_leveling_value(chan);
 721         clrbits_le32(&denali_pi[60], 0x3 << 8);
 722
 723         return 0;
 724 }
 725
 726 static int data_training_rg(const struct chan_info *chan, u32 channel,
 727                             const struct rk3399_sdram_params *params)
 728 {
 729         u32 *denali_pi = chan->pi->denali_pi;
 730         u32 *denali_phy = chan->publ->denali_phy;
 731         u32 i, tmp;
 732         u32 obs_0, obs_1, obs_2, obs_3, obs_err = 0;
 733         u32 rank = params->ch[channel].rank;
 734
 735         for (i = 0; i < rank; i++) {
 736                 select_per_cs_training_index(chan, i);
 737
 738                 /* PI_80 PI_RDLVL_GATE_EN:RW:24:2 */
 739                 clrsetbits_le32(&denali_pi[80], 0x3 << 24, 0x2 << 24);
 740
 741                 /*
 742                  * PI_74 PI_RDLVL_GATE_REQ:WR:16:1
 743                  * PI_RDLVL_CS:RW:24:2
 744                  */
 745                 clrsetbits_le32(&denali_pi[74],
 746                                 (0x1 << 16) | (0x3 << 24),
 747                                 (0x1 << 16) | (i << 24));
 748
 749                 /* Waiting for training complete */
 750                 while (1) {
 751                         /* PI_174 PI_INT_STATUS:RD:8:18 */
 752                         tmp = readl(&denali_pi[174]) >> 8;
 753
 754                         /*
 755                          * check status obs
 756                          * PHY_43/171/299/427
 757                          *     PHY_GTLVL_STATUS_OBS_x:16:8
 758                          */
 759                         obs_0 = readl(&denali_phy[43]);
 760                         obs_1 = readl(&denali_phy[171]);
 761                         obs_2 = readl(&denali_phy[299]);
 762                         obs_3 = readl(&denali_phy[427]);
 763                         if (((obs_0 >> (16 + 6)) & 0x3) ||
 764                             ((obs_1 >> (16 + 6)) & 0x3) ||
 765                             ((obs_2 >> (16 + 6)) & 0x3) ||
 766                             ((obs_3 >> (16 + 6)) & 0x3))
 767                                 obs_err = 1;
 768                         if ((((tmp >> 9) & 0x1) == 0x1) &&
 769                             (((tmp >> 13) & 0x1) == 0x1) &&
 770                             (((tmp >> 3) & 0x1) == 0x0) &&
 771                             obs_err == 0)
 772                                 break;
 773                         else if ((((tmp >> 3) & 0x1) == 0x1) ||
 774                                  (obs_err == 1))
 775                                 return -EIO;
 776                 }
 777
 778                 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
 779                 writel(0x00003f7c, (&denali_pi[175]));
 780         }
 781
 782         clrbits_le32(&denali_pi[80], 0x3 << 24);
 783
 784         return 0;
 785 }
 786
 787 static int data_training_rl(const struct chan_info *chan, u32 channel,
 788                             const struct rk3399_sdram_params *params)
 789 {
 790         u32 *denali_pi = chan->pi->denali_pi;
 791         u32 i, tmp;
 792         u32 rank = params->ch[channel].rank;
 793
 794         for (i = 0; i < rank; i++) {
 795                 select_per_cs_training_index(chan, i);
 796
 797                 /* PI_80 PI_RDLVL_EN:RW:16:2 */
 798                 clrsetbits_le32(&denali_pi[80], 0x3 << 16, 0x2 << 16);
 799
 800                 /* PI_74 PI_RDLVL_REQ:WR:8:1,PI_RDLVL_CS:RW:24:2 */
 801                 clrsetbits_le32(&denali_pi[74],
 802                                 (0x1 << 8) | (0x3 << 24),
 803                                 (0x1 << 8) | (i << 24));
 804
 805                 /* Waiting for training complete */
 806                 while (1) {
 807                         /* PI_174 PI_INT_STATUS:RD:8:18 */
 808                         tmp = readl(&denali_pi[174]) >> 8;
 809
 810                         /*
 811                          * make sure status obs not report error bit
 812                          * PHY_46/174/302/430
 813                          *     phy_rdlvl_status_obs_X:16:8
 814                          */
 815                         if ((((tmp >> 8) & 0x1) == 0x1) &&
 816                             (((tmp >> 13) & 0x1) == 0x1) &&
 817                             (((tmp >> 2) & 0x1) == 0x0))
 818                                 break;
 819                         else if (((tmp >> 2) & 0x1) == 0x1)
 820                                 return -EIO;
 821                 }
 822
 823                 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
 824                 writel(0x00003f7c, (&denali_pi[175]));
 825         }
 826
 827         clrbits_le32(&denali_pi[80], 0x3 << 16);
 828
 829         return 0;
 830 }
 831
 832 static int data_training_wdql(const struct chan_info *chan, u32 channel,
 833                               const struct rk3399_sdram_params *params)
 834 {
 835         u32 *denali_pi = chan->pi->denali_pi;
 836         u32 i, tmp;
 837         u32 rank = params->ch[channel].rank;
 838
 839         for (i = 0; i < rank; i++) {
 840                 select_per_cs_training_index(chan, i);
 841
 842                 /*
 843                  * disable PI_WDQLVL_VREF_EN before wdq leveling?
 844                  * PI_181 PI_WDQLVL_VREF_EN:RW:8:1
 845                  */
 846                 clrbits_le32(&denali_pi[181], 0x1 << 8);
 847
 848                 /* PI_124 PI_WDQLVL_EN:RW:16:2 */
 849                 clrsetbits_le32(&denali_pi[124], 0x3 << 16, 0x2 << 16);
 850
 851                 /* PI_121 PI_WDQLVL_REQ:WR:8:1,PI_WDQLVL_CS:RW:16:2 */
 852                 clrsetbits_le32(&denali_pi[121],
 853                                 (0x1 << 8) | (0x3 << 16),
 854                                 (0x1 << 8) | (i << 16));
 855
 856                 /* Waiting for training complete */
 857                 while (1) {
 858                         /* PI_174 PI_INT_STATUS:RD:8:18 */
 859                         tmp = readl(&denali_pi[174]) >> 8;
 860                         if ((((tmp >> 12) & 0x1) == 0x1) &&
 861                             (((tmp >> 13) & 0x1) == 0x1) &&
 862                             (((tmp >> 6) & 0x1) == 0x0))
 863                                 break;
 864                         else if (((tmp >> 6) & 0x1) == 0x1)
 865                                 return -EIO;
 866                 }
 867
 868                 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
 869                 writel(0x00003f7c, (&denali_pi[175]));
 870         }
 871
 872         clrbits_le32(&denali_pi[124], 0x3 << 16);
 873
 874         return 0;
 875 }
 876
 877 static int data_training(const struct chan_info *chan, u32 channel,
 878                          const struct rk3399_sdram_params *params,
 879                          u32 training_flag)
 880 {
 881         u32 *denali_phy = chan->publ->denali_phy;
 882
 883         /* PHY_927 PHY_PAD_DQS_DRIVE  RPULL offset_22 */
 884         setbits_le32(&denali_phy[927], (1 << 22));
 885
 886         if (training_flag == PI_FULL_TRAINING) {
 887                 if (params->base.dramtype == LPDDR4) {
 888                         training_flag = PI_CA_TRAINING | PI_WRITE_LEVELING |
 889                                         PI_READ_GATE_TRAINING |
 890                                         PI_READ_LEVELING | PI_WDQ_LEVELING;
 891                 } else if (params->base.dramtype == LPDDR3) {
 892                         training_flag = PI_CA_TRAINING | PI_WRITE_LEVELING |
 893                                         PI_READ_GATE_TRAINING;
 894                 } else if (params->base.dramtype == DDR3) {
 895                         training_flag = PI_WRITE_LEVELING |
 896                                         PI_READ_GATE_TRAINING |
 897                                         PI_READ_LEVELING;
 898                 }
 899         }
 900
 901         /* ca training(LPDDR4,LPDDR3 support) */
 902         if ((training_flag & PI_CA_TRAINING) == PI_CA_TRAINING)
 903                 data_training_ca(chan, channel, params);
 904
 905         /* write leveling(LPDDR4,LPDDR3,DDR3 support) */
 906         if ((training_flag & PI_WRITE_LEVELING) == PI_WRITE_LEVELING)
 907                 data_training_wl(chan, channel, params);
 908
 909         /* read gate training(LPDDR4,LPDDR3,DDR3 support) */
 910         if ((training_flag & PI_READ_GATE_TRAINING) == PI_READ_GATE_TRAINING)
 911                 data_training_rg(chan, channel, params);
 912
 913         /* read leveling(LPDDR4,LPDDR3,DDR3 support) */
 914         if ((training_flag & PI_READ_LEVELING) == PI_READ_LEVELING)
 915                 data_training_rl(chan, channel, params);
 916
 917         /* wdq leveling(LPDDR4 support) */
 918         if ((training_flag & PI_WDQ_LEVELING) == PI_WDQ_LEVELING)
 919                 data_training_wdql(chan, channel, params);
 920
 921         /* PHY_927 PHY_PAD_DQS_DRIVE  RPULL offset_22 */
 922         clrbits_le32(&denali_phy[927], (1 << 22));
 923
 924         return 0;
 925 }
 926
 927 static void set_ddrconfig(const struct chan_info *chan,
 928                           const struct rk3399_sdram_params *params,
 929                           unsigned char channel, u32 ddrconfig)
 930 {
 931         /* only need to set ddrconfig */
 932         struct rk3399_msch_regs *ddr_msch_regs = chan->msch;
 933         unsigned int cs0_cap = 0;
 934         unsigned int cs1_cap = 0;
 935
 936         cs0_cap = (1 << (params->ch[channel].cs0_row
 937                         + params->ch[channel].col
 938                         + params->ch[channel].bk
 939                         + params->ch[channel].bw - 20));
 940         if (params->ch[channel].rank > 1)
 941                 cs1_cap = cs0_cap >> (params->ch[channel].cs0_row
 942                                 - params->ch[channel].cs1_row);
 943         if (params->ch[channel].row_3_4) {
 944                 cs0_cap = cs0_cap * 3 / 4;
 945                 cs1_cap = cs1_cap * 3 / 4;
 946         }
 947
 948         writel(ddrconfig | (ddrconfig << 8), &ddr_msch_regs->ddrconf);
 949         writel(((cs0_cap / 32) & 0xff) | (((cs1_cap / 32) & 0xff) << 8),
 950                &ddr_msch_regs->ddrsize);
 951 }
 952
 953 static void dram_all_config(struct dram_info *dram,
 954                             const struct rk3399_sdram_params *params)
 955 {
 956         u32 sys_reg = 0;
 957         unsigned int channel, idx;
 958
 959         sys_reg |= params->base.dramtype << SYS_REG_DDRTYPE_SHIFT;
 960         sys_reg |= (params->base.num_channels - 1) << SYS_REG_NUM_CH_SHIFT;
 961
 962         for (channel = 0, idx = 0;
 963              (idx < params->base.num_channels) && (channel < 2);
 964              channel++) {
 965                 const struct rk3399_sdram_channel *info = &params->ch[channel];
 966                 struct rk3399_msch_regs *ddr_msch_regs;
 967                 const struct rk3399_msch_timings *noc_timing;
 968
 969                 if (params->ch[channel].col == 0)
 970                         continue;
 971                 idx++;
 972                 sys_reg |= info->row_3_4 << SYS_REG_ROW_3_4_SHIFT(channel);
 973                 sys_reg |= 1 << SYS_REG_CHINFO_SHIFT(channel);
 974                 sys_reg |= (info->rank - 1) << SYS_REG_RANK_SHIFT(channel);
 975                 sys_reg |= (info->col - 9) << SYS_REG_COL_SHIFT(channel);
 976                 sys_reg |= info->bk == 3 ? 0 : 1 << SYS_REG_BK_SHIFT(channel);
 977                 sys_reg |= (info->cs0_row - 13) <<
 978                             SYS_REG_CS0_ROW_SHIFT(channel);
 979                 sys_reg |= (info->cs1_row - 13) <<
 980                             SYS_REG_CS1_ROW_SHIFT(channel);
 981                 sys_reg |= (2 >> info->bw) << SYS_REG_BW_SHIFT(channel);
 982                 sys_reg |= (2 >> info->dbw) << SYS_REG_DBW_SHIFT(channel);
 983
 984                 ddr_msch_regs = dram->chan[channel].msch;
 985                 noc_timing = &params->ch[channel].noc_timings;
 986                 writel(noc_timing->ddrtiminga0,
 987                        &ddr_msch_regs->ddrtiminga0);
 988                 writel(noc_timing->ddrtimingb0,
 989                        &ddr_msch_regs->ddrtimingb0);
 990                 writel(noc_timing->ddrtimingc0,
 991                        &ddr_msch_regs->ddrtimingc0);
 992                 writel(noc_timing->devtodev0,
 993                        &ddr_msch_regs->devtodev0);
 994                 writel(noc_timing->ddrmode,
 995                        &ddr_msch_regs->ddrmode);
 996
 997                 /* rank 1 memory clock disable (dfi_dram_clk_disable = 1) */
 998                 if (params->ch[channel].rank == 1)
 999                         setbits_le32(&dram->chan[channel].pctl->denali_ctl[276],
1000                                      1 << 17);
1001         }
1002
1003         writel(sys_reg, &dram->pmugrf->os_reg2);
1004         rk_clrsetreg(&dram->pmusgrf->soc_con4, 0x1f << 10,
1005                      params->base.stride << 10);
1006
1007         /* reboot hold register set */
1008         writel(PRESET_SGRF_HOLD(0) | PRESET_GPIO0_HOLD(1) |
1009                 PRESET_GPIO1_HOLD(1),
1010                 &dram->pmucru->pmucru_rstnhold_con[1]);
1011         clrsetbits_le32(&dram->cru->glb_rst_con, 0x3, 0x3);
1012 }
1013
1014 static int switch_to_phy_index1(struct dram_info *dram,
1015                                 const struct rk3399_sdram_params *params)
1016 {
1017         u32 channel;
1018         u32 *denali_phy;
1019         u32 ch_count = params->base.num_channels;
1020         int ret;
1021         int i = 0;
1022
1023         writel(RK_CLRSETBITS(0x03 << 4 | 1 << 2 | 1,
1024                              1 << 4 | 1 << 2 | 1),
1025                         &dram->cic->cic_ctrl0);
1026         while (!(readl(&dram->cic->cic_status0) & (1 << 2))) {
1027                 mdelay(10);
1028                 i++;
1029                 if (i > 10) {
1030                         debug("index1 frequency change overtime\n");
1031                         return -ETIME;
1032                 }
1033         }
1034
1035         i = 0;
1036         writel(RK_CLRSETBITS(1 << 1, 1 << 1), &dram->cic->cic_ctrl0);
1037         while (!(readl(&dram->cic->cic_status0) & (1 << 0))) {
1038                 mdelay(10);
1039                 i++;
1040                 if (i > 10) {
1041                         debug("index1 frequency done overtime\n");
1042                         return -ETIME;
1043                 }
1044         }
1045
1046         for (channel = 0; channel < ch_count; channel++) {
1047                 denali_phy = dram->chan[channel].publ->denali_phy;
1048                 clrsetbits_le32(&denali_phy[896], (0x3 << 8) | 1, 1 << 8);
1049                 ret = data_training(&dram->chan[channel], channel,
1050                                     params, PI_FULL_TRAINING);
1051                 if (ret) {
1052                         debug("index1 training failed\n");
1053                         return ret;
1054                 }
1055         }
1056
1057         return 0;
1058 }
1059
1060 static int sdram_init(struct dram_info *dram,
1061                       const struct rk3399_sdram_params *params)
1062 {
1063         unsigned char dramtype = params->base.dramtype;
1064         unsigned int ddr_freq = params->base.ddr_freq;
1065         int channel;
1066         int ret;
1067
1068         debug("Starting SDRAM initialization...\n");
1069
1070         if ((dramtype == DDR3 && ddr_freq > 933) ||
1071             (dramtype == LPDDR3 && ddr_freq > 933) ||
1072             (dramtype == LPDDR4 && ddr_freq > 800)) {
1073                 debug("SDRAM frequency is to high!");
1074                 return -E2BIG;
1075         }
1076
1077         for (channel = 0; channel < 2; channel++) {
1078                 const struct chan_info *chan = &dram->chan[channel];
1079                 struct rk3399_ddr_publ_regs *publ = chan->publ;
1080
1081                 phy_dll_bypass_set(publ, ddr_freq);
1082
1083                 if (channel >= params->base.num_channels)
1084                         continue;
1085
1086                 ret = pctl_cfg(chan, channel, params);
1087                 if (ret < 0) {
1088                         printf("%s: pctl config failed\n", __func__);
1089                         return ret;
1090                 }
1091
1092                 /* LPDDR2/LPDDR3 need to wait DAI complete, max 10us */
1093                 if (dramtype == LPDDR3)
1094                         udelay(10);
1095
1096                 if (data_training(chan, channel, params, PI_FULL_TRAINING)) {
1097                         printf("SDRAM initialization failed, reset\n");
1098                         return -EIO;
1099                 }
1100
1101                 set_ddrconfig(chan, params, channel,
1102                               params->ch[channel].ddrconfig);
1103         }
1104         dram_all_config(dram, params);
1105         switch_to_phy_index1(dram, params);
1106
1107         debug("Finish SDRAM initialization...\n");
1108         return 0;
1109 }
1110
1111 static int rk3399_dmc_ofdata_to_platdata(struct udevice *dev)
1112 {
1113 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
1114         struct rockchip_dmc_plat *plat = dev_get_platdata(dev);
1115         int ret;
1116
1117         ret = dev_read_u32_array(dev, "rockchip,sdram-params",
1118                                  (u32 *)&plat->sdram_params,
1119                                  sizeof(plat->sdram_params) / sizeof(u32));
1120         if (ret) {
1121                 printf("%s: Cannot read rockchip,sdram-params %d\n",
1122                        __func__, ret);
1123                 return ret;
1124         }
1125         ret = regmap_init_mem(dev_ofnode(dev), &plat->map);
1126         if (ret)
1127                 printf("%s: regmap failed %d\n", __func__, ret);
1128
1129 #endif
1130         return 0;
1131 }
1132
1133 #if CONFIG_IS_ENABLED(OF_PLATDATA)
1134 static int conv_of_platdata(struct udevice *dev)
1135 {
1136         struct rockchip_dmc_plat *plat = dev_get_platdata(dev);
1137         struct dtd_rockchip_rk3399_dmc *dtplat = &plat->dtplat;
1138         int ret;
1139
1140         ret = regmap_init_mem_platdata(dev, dtplat->reg,
1141                                        ARRAY_SIZE(dtplat->reg) / 2,
1142                                        &plat->map);
1143         if (ret)
1144                 return ret;
1145
1146         return 0;
1147 }
1148 #endif
1149
1150 static int rk3399_dmc_init(struct udevice *dev)
1151 {
1152         struct dram_info *priv = dev_get_priv(dev);
1153         struct rockchip_dmc_plat *plat = dev_get_platdata(dev);
1154         int ret;
1155 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
1156         struct rk3399_sdram_params *params = &plat->sdram_params;
1157 #else
1158         struct dtd_rockchip_rk3399_dmc *dtplat = &plat->dtplat;
1159         struct rk3399_sdram_params *params =
1160                                         (void *)dtplat->rockchip_sdram_params;
1161
1162         ret = conv_of_platdata(dev);
1163         if (ret)
1164                 return ret;
1165 #endif
1166
1167         priv->cic = syscon_get_first_range(ROCKCHIP_SYSCON_CIC);
1168         priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
1169         priv->pmusgrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUSGRF);
1170         priv->pmucru = rockchip_get_pmucru();
1171         priv->cru = rockchip_get_cru();
1172         priv->chan[0].pctl = regmap_get_range(plat->map, 0);
1173         priv->chan[0].pi = regmap_get_range(plat->map, 1);
1174         priv->chan[0].publ = regmap_get_range(plat->map, 2);
1175         priv->chan[0].msch = regmap_get_range(plat->map, 3);
1176         priv->chan[1].pctl = regmap_get_range(plat->map, 4);
1177         priv->chan[1].pi = regmap_get_range(plat->map, 5);
1178         priv->chan[1].publ = regmap_get_range(plat->map, 6);
1179         priv->chan[1].msch = regmap_get_range(plat->map, 7);
1180
1181         debug("con reg %p %p %p %p %p %p %p %p\n",
1182               priv->chan[0].pctl, priv->chan[0].pi,
1183               priv->chan[0].publ, priv->chan[0].msch,
1184               priv->chan[1].pctl, priv->chan[1].pi,
1185               priv->chan[1].publ, priv->chan[1].msch);
1186         debug("cru %p, cic %p, grf %p, sgrf %p, pmucru %p\n", priv->cru,
1187               priv->cic, priv->pmugrf, priv->pmusgrf, priv->pmucru);
1188
1189 #if CONFIG_IS_ENABLED(OF_PLATDATA)
1190         ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &priv->ddr_clk);
1191 #else
1192         ret = clk_get_by_index(dev, 0, &priv->ddr_clk);
1193 #endif
1194         if (ret) {
1195                 printf("%s clk get failed %d\n", __func__, ret);
1196                 return ret;
1197         }
1198
1199         ret = clk_set_rate(&priv->ddr_clk, params->base.ddr_freq * MHz);
1200         if (ret < 0) {
1201                 printf("%s clk set failed %d\n", __func__, ret);
1202                 return ret;
1203         }
1204
1205         ret = sdram_init(priv, params);
1206         if (ret < 0) {
1207                 printf("%s DRAM init failed %d\n", __func__, ret);
1208                 return ret;
1209         }
1210
1211         return 0;
1212 }
1213 #endif
1214
1215 static int rk3399_dmc_probe(struct udevice *dev)
1216 {
1217 #if defined(CONFIG_TPL_BUILD) || \
1218         (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
1219         if (rk3399_dmc_init(dev))
1220                 return 0;
1221 #else
1222         struct dram_info *priv = dev_get_priv(dev);
1223
1224         priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
1225         debug("%s: pmugrf = %p\n", __func__, priv->pmugrf);
1226         priv->info.base = CONFIG_SYS_SDRAM_BASE;
1227         priv->info.size =
1228                 rockchip_sdram_size((phys_addr_t)&priv->pmugrf->os_reg2);
1229 #endif
1230         return 0;
1231 }
1232
1233 static int rk3399_dmc_get_info(struct udevice *dev, struct ram_info *info)
1234 {
1235         struct dram_info *priv = dev_get_priv(dev);
1236
1237         *info = priv->info;
1238
1239         return 0;
1240 }
1241
1242 static struct ram_ops rk3399_dmc_ops = {
1243         .get_info = rk3399_dmc_get_info,
1244 };
1245
1246 static const struct udevice_id rk3399_dmc_ids[] = {
1247         { .compatible = "rockchip,rk3399-dmc" },
1248         { }
1249 };
1250
1251 U_BOOT_DRIVER(dmc_rk3399) = {
1252         .name = "rockchip_rk3399_dmc",
1253         .id = UCLASS_RAM,
1254         .of_match = rk3399_dmc_ids,
1255         .ops = &rk3399_dmc_ops,
1256 #if defined(CONFIG_TPL_BUILD) || \
1257         (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
1258         .ofdata_to_platdata = rk3399_dmc_ofdata_to_platdata,
1259 #endif
1260         .probe = rk3399_dmc_probe,
1261         .priv_auto_alloc_size = sizeof(struct dram_info),
1262 #if defined(CONFIG_TPL_BUILD) || \
1263         (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
1264         .platdata_auto_alloc_size = sizeof(struct rockchip_dmc_plat),
1265 #endif
1266 };