drivers/ufs/ufs-qcom.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2013-2016, Linux Foundation. All rights reserved.
   4  * Copyright (C) 2023-2024 Linaro Limited
   5  * Authors:
   6  * - Bhupesh Sharma <[email protected]>
   7  * - Neil Armstrong <[email protected]>
   8  *
   9  * Based on Linux driver
  10  */
  11
  12 #include <asm/io.h>
  13 #include <clk.h>
  14 #include <dm.h>
  15 #include <dm/device_compat.h>
  16 #include <generic-phy.h>
  17 #include <ufs.h>
  18 #include <asm/gpio.h>
  19
  20 #include <linux/bitops.h>
  21 #include <linux/delay.h>
  22 #include <linux/err.h>
  23
  24 #include "ufs.h"
  25 #include "ufs-qcom.h"
  26
  27 #define ceil(freq, div) ((freq) % (div) == 0 ? ((freq) / (div)) : ((freq) / (div) + 1))
  28
  29 static void ufs_qcom_dev_ref_clk_ctrl(struct ufs_hba *hba, bool enable);
  30
  31 static int ufs_qcom_enable_clks(struct ufs_qcom_priv *priv)
  32 {
  33         int err;
  34
  35         if (priv->is_clks_enabled)
  36                 return 0;
  37
  38         err = clk_enable_bulk(&priv->clks);
  39         if (err)
  40                 return err;
  41
  42         priv->is_clks_enabled = true;
  43
  44         return 0;
  45 }
  46
  47 static int ufs_qcom_init_clks(struct ufs_qcom_priv *priv)
  48 {
  49         int err;
  50         struct udevice *dev = priv->hba->dev;
  51
  52         err = clk_get_bulk(dev, &priv->clks);
  53         if (err)
  54                 return err;
  55
  56         return 0;
  57 }
  58
  59 static int ufs_qcom_check_hibern8(struct ufs_hba *hba)
  60 {
  61         int err, retry_count = 50;
  62         u32 tx_fsm_val = 0;
  63
  64         do {
  65                 err = ufshcd_dme_get(hba,
  66                                 UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE,
  67                                         UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)),
  68                                 &tx_fsm_val);
  69                 if (err || tx_fsm_val == TX_FSM_HIBERN8)
  70                         break;
  71
  72                 /* max. 200us */
  73                 udelay(200);
  74                 retry_count--;
  75         } while (retry_count != 0);
  76
  77         /* Check the state again */
  78         err = ufshcd_dme_get(hba,
  79                         UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE,
  80                                 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)),
  81                                 &tx_fsm_val);
  82
  83         if (err) {
  84                 dev_err(hba->dev, "%s: unable to get TX_FSM_STATE, err %d\n",
  85                         __func__, err);
  86         } else if (tx_fsm_val != TX_FSM_HIBERN8) {
  87                 err = tx_fsm_val;
  88                 dev_err(hba->dev, "%s: invalid TX_FSM_STATE = %d\n",
  89                         __func__, err);
  90         }
  91
  92         return err;
  93 }
  94
  95 static void ufs_qcom_select_unipro_mode(struct ufs_qcom_priv *priv)
  96 {
  97         ufshcd_rmwl(priv->hba, QUNIPRO_SEL, QUNIPRO_SEL, REG_UFS_CFG1);
  98
  99         if (priv->hw_ver.major >= 0x05)
 100                 ufshcd_rmwl(priv->hba, QUNIPRO_G4_SEL, 0, REG_UFS_CFG0);
 101 }
 102
 103 /*
 104  * ufs_qcom_reset - reset host controller and PHY
 105  */
 106 static int ufs_qcom_reset(struct ufs_hba *hba)
 107 {
 108         struct ufs_qcom_priv *priv = dev_get_priv(hba->dev);
 109         int ret;
 110
 111         ret = reset_assert(&priv->core_reset);
 112         if (ret) {
 113                 dev_err(hba->dev, "%s: core_reset assert failed, err = %d\n",
 114                         __func__, ret);
 115                 return ret;
 116         }
 117
 118         /*
 119          * The hardware requirement for delay between assert/deassert
 120          * is at least 3-4 sleep clock (32.7KHz) cycles, which comes to
 121          * ~125us (4/32768). To be on the safe side add 200us delay.
 122          */
 123         udelay(210);
 124
 125         ret = reset_deassert(&priv->core_reset);
 126         if (ret)
 127                 dev_err(hba->dev, "%s: core_reset deassert failed, err = %d\n",
 128                         __func__, ret);
 129
 130         udelay(1100);
 131
 132         return 0;
 133 }
 134
 135 /**
 136  * ufs_qcom_advertise_quirks - advertise the known QCOM UFS controller quirks
 137  * @hba: host controller instance
 138  *
 139  * QCOM UFS host controller might have some non standard behaviours (quirks)
 140  * than what is specified by UFSHCI specification. Advertise all such
 141  * quirks to standard UFS host controller driver so standard takes them into
 142  * account.
 143  */
 144 static void ufs_qcom_advertise_quirks(struct ufs_hba *hba)
 145 {
 146         struct ufs_qcom_priv *priv = dev_get_priv(hba->dev);
 147
 148         if (priv->hw_ver.major == 0x2)
 149                 hba->quirks |= UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION;
 150
 151         if (priv->hw_ver.major > 0x3)
 152                 hba->quirks |= UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH;
 153 }
 154
 155 /**
 156  * ufs_qcom_setup_clocks - enables/disable clocks
 157  * @hba: host controller instance
 158  * @on: If true, enable clocks else disable them.
 159  * @status: PRE_CHANGE or POST_CHANGE notify
 160  *
 161  * Returns 0 on success, non-zero on failure.
 162  */
 163 static int ufs_qcom_setup_clocks(struct ufs_hba *hba, bool on,
 164                                  enum ufs_notify_change_status status)
 165 {
 166         switch (status) {
 167         case PRE_CHANGE:
 168                 if (!on)
 169                         /* disable device ref_clk */
 170                         ufs_qcom_dev_ref_clk_ctrl(hba, false);
 171                 break;
 172         case POST_CHANGE:
 173                 if (on)
 174                         /* enable the device ref clock for HS mode*/
 175                         ufs_qcom_dev_ref_clk_ctrl(hba, true);
 176                 break;
 177         }
 178
 179         return 0;
 180 }
 181
 182 static u32 ufs_qcom_get_hs_gear(struct ufs_hba *hba)
 183 {
 184         struct ufs_qcom_priv *priv = dev_get_priv(hba->dev);
 185
 186         /*
 187          * TOFIX: v4 controllers *should* be able to support HS Gear 4
 188          * but so far pwr_mode switch is failing on v4 controllers and HS Gear 4.
 189          * only enable HS Gear > 3 for Controlers major version 5 and later.
 190          */
 191         if (priv->hw_ver.major > 0x4)
 192                 return UFS_QCOM_MAX_GEAR(ufshcd_readl(hba, REG_UFS_PARAM0));
 193
 194         /* Default is HS-G3 */
 195         return UFS_HS_G3;
 196 }
 197
 198 static int ufs_get_max_pwr_mode(struct ufs_hba *hba,
 199                                 struct ufs_pwr_mode_info *max_pwr_info)
 200 {
 201         struct ufs_qcom_priv *priv = dev_get_priv(hba->dev);
 202         u32 max_gear = ufs_qcom_get_hs_gear(hba);
 203
 204         max_pwr_info->info.gear_rx = min(max_pwr_info->info.gear_rx, max_gear);
 205         /* Qualcomm UFS only support symmetric Gear */
 206         max_pwr_info->info.gear_tx = max_pwr_info->info.gear_rx;
 207
 208         if (priv->hw_ver.major >= 0x4 && max_pwr_info->info.gear_rx > UFS_HS_G3)
 209                 ufshcd_dme_set(hba,
 210                                UIC_ARG_MIB(PA_TXHSADAPTTYPE),
 211                                PA_INITIAL_ADAPT);
 212
 213         dev_info(hba->dev, "Max HS Gear: %d\n", max_pwr_info->info.gear_rx);
 214
 215         return 0;
 216 }
 217
 218 static int ufs_qcom_power_up_sequence(struct ufs_hba *hba)
 219 {
 220         struct ufs_qcom_priv *priv = dev_get_priv(hba->dev);
 221         struct phy phy;
 222         int ret;
 223
 224         /* Reset UFS Host Controller and PHY */
 225         ret = ufs_qcom_reset(hba);
 226         if (ret)
 227                 dev_warn(hba->dev, "%s: host reset returned %d\n",
 228                          __func__, ret);
 229
 230         /* get phy */
 231         ret = generic_phy_get_by_name(hba->dev, "ufsphy", &phy);
 232         if (ret) {
 233                 dev_warn(hba->dev, "%s: Unable to get QMP ufs phy, ret = %d\n",
 234                          __func__, ret);
 235                 return ret;
 236         }
 237
 238         /* phy initialization */
 239         ret = generic_phy_init(&phy);
 240         if (ret) {
 241                 dev_err(hba->dev, "%s: phy init failed, ret = %d\n",
 242                         __func__, ret);
 243                 return ret;
 244         }
 245
 246         /* power on phy */
 247         ret = generic_phy_power_on(&phy);
 248         if (ret) {
 249                 dev_err(hba->dev, "%s: phy power on failed, ret = %d\n",
 250                         __func__, ret);
 251                 goto out_disable_phy;
 252         }
 253
 254         ufs_qcom_select_unipro_mode(priv);
 255
 256         return 0;
 257
 258 out_disable_phy:
 259         generic_phy_exit(&phy);
 260
 261         return ret;
 262 }
 263
 264 /*
 265  * The UTP controller has a number of internal clock gating cells (CGCs).
 266  * Internal hardware sub-modules within the UTP controller control the CGCs.
 267  * Hardware CGCs disable the clock to inactivate UTP sub-modules not involved
 268  * in a specific operation, UTP controller CGCs are by default disabled and
 269  * this function enables them (after every UFS link startup) to save some power
 270  * leakage.
 271  */
 272 static void ufs_qcom_enable_hw_clk_gating(struct ufs_hba *hba)
 273 {
 274         ufshcd_rmwl(hba, REG_UFS_CFG2_CGC_EN_ALL, REG_UFS_CFG2_CGC_EN_ALL,
 275                     REG_UFS_CFG2);
 276
 277         /* Ensure that HW clock gating is enabled before next operations */
 278         ufshcd_readl(hba, REG_UFS_CFG2);
 279 }
 280
 281 static int ufs_qcom_hce_enable_notify(struct ufs_hba *hba,
 282                                       enum ufs_notify_change_status status)
 283 {
 284         struct ufs_qcom_priv *priv = dev_get_priv(hba->dev);
 285         int err;
 286
 287         switch (status) {
 288         case PRE_CHANGE:
 289                 ufs_qcom_power_up_sequence(hba);
 290                 /*
 291                  * The PHY PLL output is the source of tx/rx lane symbol
 292                  * clocks, hence, enable the lane clocks only after PHY
 293                  * is initialized.
 294                  */
 295                 err = ufs_qcom_enable_clks(priv);
 296                 break;
 297         case POST_CHANGE:
 298                 /* check if UFS PHY moved from DISABLED to HIBERN8 */
 299                 err = ufs_qcom_check_hibern8(hba);
 300                 ufs_qcom_enable_hw_clk_gating(hba);
 301                 break;
 302         default:
 303                 dev_err(hba->dev, "%s: invalid status %d\n", __func__, status);
 304                 err = -EINVAL;
 305                 break;
 306         }
 307
 308         return err;
 309 }
 310
 311 /* Look for the maximum core_clk_unipro clock value */
 312 static u32 ufs_qcom_get_core_clk_unipro_max_freq(struct ufs_hba *hba)
 313 {
 314         struct ufs_qcom_priv *priv = dev_get_priv(hba->dev);
 315         ofnode node = dev_ofnode(priv->hba->dev);
 316         struct ofnode_phandle_args opp_table;
 317         int pos, ret;
 318         u32 clk = 0;
 319
 320         /* Get core_clk_unipro clock index */
 321         pos = ofnode_stringlist_search(node, "clock-names", "core_clk_unipro");
 322         if (pos < 0)
 323                 goto fallback;
 324
 325         /* Try parsing the opps */
 326         if (!ofnode_parse_phandle_with_args(node, "required-opps",
 327                                             NULL, 0, 0, &opp_table) &&
 328             ofnode_device_is_compatible(opp_table.node, "operating-points-v2")) {
 329                 ofnode opp_node;
 330
 331                 ofnode_for_each_subnode(opp_node, opp_table.node) {
 332                         u64 opp_clk;
 333                         /* opp-hw contains the OPP frequency */
 334                         ret = ofnode_read_u64_index(opp_node, "opp-hz", pos, &opp_clk);
 335                         if (ret)
 336                                 continue;
 337
 338                         /* We don't handle larger clock values, ignore */
 339                         if (opp_clk > U32_MAX)
 340                                 continue;
 341
 342                         /* Only keep the largest value */
 343                         if (opp_clk > clk)
 344                                 clk = opp_clk;
 345                 }
 346
 347                 /* If we get a valid clock, return it or check legacy*/
 348                 if (clk)
 349                         return clk;
 350         }
 351
 352         /* Legacy freq-table-hz has a pair of u32 per clocks entry, min then max */
 353         if (!ofnode_read_u32_index(node, "freq-table-hz", pos * 2 + 1, &clk) &&
 354             clk > 0)
 355                 return clk;
 356
 357 fallback:
 358         /* default for backwards compatibility */
 359         return UNIPRO_CORE_CLK_FREQ_150_MHZ * 1000 * 1000;
 360 };
 361
 362 static int ufs_qcom_set_clk_40ns_cycles(struct ufs_hba *hba,
 363                                         u32 cycles_in_1us)
 364 {
 365         struct ufs_qcom_priv *priv = dev_get_priv(hba->dev);
 366         u32 cycles_in_40ns;
 367         int err;
 368         u32 reg;
 369
 370         /*
 371          * UFS host controller V4.0.0 onwards needs to program
 372          * PA_VS_CORE_CLK_40NS_CYCLES attribute per programmed
 373          * frequency of unipro core clk of UFS host controller.
 374          */
 375         if (priv->hw_ver.major < 4)
 376                 return 0;
 377
 378         /*
 379          * Generic formulae for cycles_in_40ns = (freq_unipro/25) is not
 380          * applicable for all frequencies. For ex: ceil(37.5 MHz/25) will
 381          * be 2 and ceil(403 MHZ/25) will be 17 whereas Hardware
 382          * specification expect to be 16. Hence use exact hardware spec
 383          * mandated value for cycles_in_40ns instead of calculating using
 384          * generic formulae.
 385          */
 386         switch (cycles_in_1us) {
 387         case UNIPRO_CORE_CLK_FREQ_403_MHZ:
 388                 cycles_in_40ns = 16;
 389                 break;
 390         case UNIPRO_CORE_CLK_FREQ_300_MHZ:
 391                 cycles_in_40ns = 12;
 392                 break;
 393         case UNIPRO_CORE_CLK_FREQ_201_5_MHZ:
 394                 cycles_in_40ns = 8;
 395                 break;
 396         case UNIPRO_CORE_CLK_FREQ_150_MHZ:
 397                 cycles_in_40ns = 6;
 398                 break;
 399         case UNIPRO_CORE_CLK_FREQ_100_MHZ:
 400                 cycles_in_40ns = 4;
 401                 break;
 402         case  UNIPRO_CORE_CLK_FREQ_75_MHZ:
 403                 cycles_in_40ns = 3;
 404                 break;
 405         case UNIPRO_CORE_CLK_FREQ_37_5_MHZ:
 406                 cycles_in_40ns = 2;
 407                 break;
 408         default:
 409                 dev_err(hba->dev, "UNIPRO clk freq %u MHz not supported\n",
 410                         cycles_in_1us);
 411                 return -EINVAL;
 412         }
 413
 414         err = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_VS_CORE_CLK_40NS_CYCLES), &reg);
 415         if (err)
 416                 return err;
 417
 418         reg &= ~PA_VS_CORE_CLK_40NS_CYCLES_MASK;
 419         reg |= cycles_in_40ns;
 420
 421         return ufshcd_dme_set(hba, UIC_ARG_MIB(PA_VS_CORE_CLK_40NS_CYCLES), reg);
 422 }
 423
 424 static int ufs_qcom_set_core_clk_ctrl(struct ufs_hba *hba)
 425 {
 426         struct ufs_qcom_priv *priv = dev_get_priv(hba->dev);
 427         u32 core_clk_ctrl_reg;
 428         u32 cycles_in_1us;
 429         int err;
 430
 431         cycles_in_1us = ceil(ufs_qcom_get_core_clk_unipro_max_freq(hba),
 432                              (1000 * 1000));
 433         err = ufshcd_dme_get(hba,
 434                              UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
 435                              &core_clk_ctrl_reg);
 436         if (err)
 437                 return err;
 438
 439         /* Bit mask is different for UFS host controller V4.0.0 onwards */
 440         if (priv->hw_ver.major >= 4) {
 441                 core_clk_ctrl_reg &= ~CLK_1US_CYCLES_MASK_V4;
 442                 core_clk_ctrl_reg |= FIELD_PREP(CLK_1US_CYCLES_MASK_V4, cycles_in_1us);
 443         } else {
 444                 core_clk_ctrl_reg &= ~CLK_1US_CYCLES_MASK;
 445                 core_clk_ctrl_reg |= FIELD_PREP(CLK_1US_CYCLES_MASK, cycles_in_1us);
 446         }
 447
 448         /* Clear CORE_CLK_DIV_EN */
 449         core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT;
 450
 451         err = ufshcd_dme_set(hba,
 452                              UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
 453                              core_clk_ctrl_reg);
 454         if (err)
 455                 return err;
 456
 457         /* Configure unipro core clk 40ns attribute */
 458         return ufs_qcom_set_clk_40ns_cycles(hba, cycles_in_1us);
 459 }
 460
 461 static u32 ufs_qcom_get_local_unipro_ver(struct ufs_hba *hba)
 462 {
 463         /* HCI version 1.0 and 1.1 supports UniPro 1.41 */
 464         switch (hba->version) {
 465         case UFSHCI_VERSION_10:
 466         case UFSHCI_VERSION_11:
 467                 return UFS_UNIPRO_VER_1_41;
 468
 469         case UFSHCI_VERSION_20:
 470         case UFSHCI_VERSION_21:
 471         default:
 472                 return UFS_UNIPRO_VER_1_6;
 473         }
 474 }
 475
 476 static int ufs_qcom_link_startup_notify(struct ufs_hba *hba,
 477                                         enum ufs_notify_change_status status)
 478 {
 479         int err = 0;
 480
 481         switch (status) {
 482         case PRE_CHANGE:
 483                 err = ufs_qcom_set_core_clk_ctrl(hba);
 484                 if (err)
 485                         dev_err(hba->dev, "cfg core clk ctrl failed\n");
 486                 /*
 487                  * Some UFS devices (and may be host) have issues if LCC is
 488                  * enabled. So we are setting PA_Local_TX_LCC_Enable to 0
 489                  * before link startup which will make sure that both host
 490                  * and device TX LCC are disabled once link startup is
 491                  * completed.
 492                  */
 493                 if (ufs_qcom_get_local_unipro_ver(hba) != UFS_UNIPRO_VER_1_41)
 494                         err = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE), 0);
 495
 496                 break;
 497         default:
 498                 break;
 499         }
 500
 501         return err;
 502 }
 503
 504 static void ufs_qcom_dev_ref_clk_ctrl(struct ufs_hba *hba, bool enable)
 505 {
 506         struct ufs_qcom_priv *priv = dev_get_priv(hba->dev);
 507
 508         if (enable ^ priv->is_dev_ref_clk_enabled) {
 509                 u32 temp = readl_relaxed(hba->mmio_base + REG_UFS_CFG1);
 510
 511                 if (enable)
 512                         temp |= BIT(26);
 513                 else
 514                         temp &= ~BIT(26);
 515
 516                 /*
 517                  * If we are here to disable this clock it might be immediately
 518                  * after entering into hibern8 in which case we need to make
 519                  * sure that device ref_clk is active for specific time after
 520                  * hibern8 enter.
 521                  */
 522                 if (!enable)
 523                         udelay(10);
 524
 525                 writel_relaxed(temp, hba->mmio_base + REG_UFS_CFG1);
 526
 527                 /*
 528                  * Make sure the write to ref_clk reaches the destination and
 529                  * not stored in a Write Buffer (WB).
 530                  */
 531                 readl(hba->mmio_base + REG_UFS_CFG1);
 532
 533                 /*
 534                  * If we call hibern8 exit after this, we need to make sure that
 535                  * device ref_clk is stable for at least 1us before the hibern8
 536                  * exit command.
 537                  */
 538                 if (enable)
 539                         udelay(1);
 540
 541                 priv->is_dev_ref_clk_enabled = enable;
 542         }
 543 }
 544
 545 /**
 546  * ufs_qcom_init - bind phy with controller
 547  * @hba: host controller instance
 548  *
 549  * Powers up PHY enabling clocks and regulators.
 550  *
 551  * Returns -EPROBE_DEFER if binding fails, returns negative error
 552  * on phy power up failure and returns zero on success.
 553  */
 554 static int ufs_qcom_init(struct ufs_hba *hba)
 555 {
 556         struct ufs_qcom_priv *priv = dev_get_priv(hba->dev);
 557         int err;
 558
 559         priv->hba = hba;
 560
 561         /* setup clocks */
 562         ufs_qcom_setup_clocks(hba, true, PRE_CHANGE);
 563
 564         if (priv->hw_ver.major >= 0x4)
 565                 ufshcd_dme_set(hba,
 566                                UIC_ARG_MIB(PA_TXHSADAPTTYPE),
 567                                PA_NO_ADAPT);
 568
 569         ufs_qcom_setup_clocks(hba, true, POST_CHANGE);
 570
 571         ufs_qcom_get_controller_revision(hba, &priv->hw_ver.major,
 572                                          &priv->hw_ver.minor,
 573                                          &priv->hw_ver.step);
 574         dev_info(hba->dev, "Qcom UFS HC version: %d.%d.%d\n",
 575                  priv->hw_ver.major,
 576                  priv->hw_ver.minor,
 577                  priv->hw_ver.step);
 578
 579         err = ufs_qcom_init_clks(priv);
 580         if (err) {
 581                 dev_err(hba->dev, "failed to initialize clocks, err:%d\n", err);
 582                 return err;
 583         }
 584
 585         ufs_qcom_advertise_quirks(hba);
 586         ufs_qcom_setup_clocks(hba, true, POST_CHANGE);
 587
 588         return 0;
 589 }
 590
 591 /**
 592  * ufs_qcom_device_reset() - toggle the (optional) device reset line
 593  * @hba: per-adapter instance
 594  *
 595  * Toggles the (optional) reset line to reset the attached device.
 596  */
 597 static int ufs_qcom_device_reset(struct ufs_hba *hba)
 598 {
 599         struct ufs_qcom_priv *priv = dev_get_priv(hba->dev);
 600
 601         if (!dm_gpio_is_valid(&priv->reset))
 602                 return 0;
 603
 604         /*
 605          * The UFS device shall detect reset pulses of 1us, sleep for 10us to
 606          * be on the safe side.
 607          */
 608         dm_gpio_set_value(&priv->reset, true);
 609         udelay(10);
 610
 611         dm_gpio_set_value(&priv->reset, false);
 612         udelay(10);
 613
 614         return 0;
 615 }
 616
 617 static struct ufs_hba_ops ufs_qcom_hba_ops = {
 618         .init                   = ufs_qcom_init,
 619         .get_max_pwr_mode       = ufs_get_max_pwr_mode,
 620         .hce_enable_notify      = ufs_qcom_hce_enable_notify,
 621         .link_startup_notify    = ufs_qcom_link_startup_notify,
 622         .device_reset           = ufs_qcom_device_reset,
 623 };
 624
 625 static int ufs_qcom_probe(struct udevice *dev)
 626 {
 627         struct ufs_qcom_priv *priv = dev_get_priv(dev);
 628         int ret;
 629
 630         /* get resets */
 631         ret = reset_get_by_name(dev, "rst", &priv->core_reset);
 632         if (ret) {
 633                 dev_err(dev, "failed to get reset, ret:%d\n", ret);
 634                 return ret;
 635         }
 636
 637         ret = gpio_request_by_name(dev, "reset-gpios", 0, &priv->reset, GPIOD_IS_OUT);
 638         if (ret) {
 639                 dev_err(dev, "Warning: cannot get reset GPIO\n");
 640         }
 641
 642         ret = ufshcd_probe(dev, &ufs_qcom_hba_ops);
 643         if (ret) {
 644                 dev_err(dev, "ufshcd_probe() failed, ret:%d\n", ret);
 645                 return ret;
 646         }
 647
 648         return 0;
 649 }
 650
 651 static int ufs_qcom_bind(struct udevice *dev)
 652 {
 653         struct udevice *scsi_dev;
 654
 655         return ufs_scsi_bind(dev, &scsi_dev);
 656 }
 657
 658 static const struct udevice_id ufs_qcom_ids[] = {
 659         { .compatible = "qcom,ufshc" },
 660         {},
 661 };
 662
 663 U_BOOT_DRIVER(qcom_ufshcd) = {
 664         .name           = "qcom-ufshcd",
 665         .id             = UCLASS_UFS,
 666         .of_match       = ufs_qcom_ids,
 667         .probe          = ufs_qcom_probe,
 668         .bind           = ufs_qcom_bind,
 669         .priv_auto      = sizeof(struct ufs_qcom_priv),
 670 };