drivers/net/phy/cortina.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Cortina CS4315/CS4340 10G PHY drivers
   4  *
   5  * Copyright 2014 Freescale Semiconductor, Inc.
   6  * Copyright 2018, 2020 NXP
   7  *
   8  */
   9
  10 #include <config.h>
  11 #include <log.h>
  12 #include <malloc.h>
  13 #include <linux/ctype.h>
  14 #include <linux/delay.h>
  15 #include <linux/string.h>
  16 #include <linux/err.h>
  17 #include <phy.h>
  18 #include <cortina.h>
  19 #include <nand.h>
  20 #include <spi_flash.h>
  21 #include <mmc.h>
  22 #ifdef CONFIG_ARM64
  23 #include <asm/arch/cpu.h>
  24 #endif
  25
  26 #ifndef CONFIG_PHYLIB_10G
  27 #error The Cortina PHY needs 10G support
  28 #endif
  29
  30 #ifndef CONFIG_SYS_CORTINA_NO_FW_UPLOAD
  31 struct cortina_reg_config cortina_reg_cfg[] = {
  32         /* CS4315_enable_sr_mode */
  33         {VILLA_GLOBAL_MSEQCLKCTRL, 0x8004},
  34         {VILLA_MSEQ_OPTIONS, 0xf},
  35         {VILLA_MSEQ_PC, 0x0},
  36         {VILLA_MSEQ_BANKSELECT,    0x4},
  37         {VILLA_LINE_SDS_COMMON_SRX0_RX_CPA, 0x55},
  38         {VILLA_LINE_SDS_COMMON_SRX0_RX_LOOP_FILTER, 0x30},
  39         {VILLA_DSP_SDS_SERDES_SRX_DFE0_SELECT, 0x1},
  40         {VILLA_DSP_SDS_DSP_COEF_DFE0_SELECT, 0x2},
  41         {VILLA_LINE_SDS_COMMON_SRX0_RX_CPB, 0x2003},
  42         {VILLA_DSP_SDS_SERDES_SRX_FFE_DELAY_CTRL, 0xF047},
  43         {VILLA_MSEQ_ENABLE_MSB, 0x0000},
  44         {VILLA_MSEQ_SPARE21_LSB, 0x6},
  45         {VILLA_MSEQ_RESET_COUNT_LSB, 0x0},
  46         {VILLA_MSEQ_SPARE12_MSB, 0x0000},
  47         /*
  48          * to invert the receiver path, uncomment the next line
  49          * write (VILLA_MSEQ_SPARE12_MSB, 0x4000)
  50          *
  51          * SPARE2_LSB is used to configure the device while in sr mode to
  52          * enable power savings and to use the optical module LOS signal.
  53          * in power savings mode, the internal prbs checker can not be used.
  54          * if the optical module LOS signal is used as an input to the micro
  55          * code, then the micro code will wait until the optical module
  56          * LOS = 0 before turning on the adaptive equalizer.
  57          * Setting SPARE2_LSB bit 0 to 1 places the devie in power savings mode
  58          * while setting bit 0 to 0 disables power savings mode.
  59          * Setting SPARE2_LSB bit 2 to 0 configures the device to use the
  60          * optical module LOS signal while setting bit 2 to 1 configures the
  61          * device so that it will ignore the optical module LOS SPARE2_LSB = 0
  62          */
  63
  64         /* enable power savings, ignore optical module LOS */
  65         {VILLA_MSEQ_SPARE2_LSB, 0x5},
  66
  67         {VILLA_MSEQ_SPARE7_LSB, 0x1e},
  68         {VILLA_MSEQ_BANKSELECT, 0x4},
  69         {VILLA_MSEQ_SPARE9_LSB, 0x2},
  70         {VILLA_MSEQ_SPARE3_LSB, 0x0F53},
  71         {VILLA_MSEQ_SPARE3_MSB, 0x2006},
  72         {VILLA_MSEQ_SPARE8_LSB, 0x3FF7},
  73         {VILLA_MSEQ_SPARE8_MSB, 0x0A46},
  74         {VILLA_MSEQ_COEF8_FFE0_LSB, 0xD500},
  75         {VILLA_MSEQ_COEF8_FFE1_LSB, 0x0200},
  76         {VILLA_MSEQ_COEF8_FFE2_LSB, 0xBA00},
  77         {VILLA_MSEQ_COEF8_FFE3_LSB, 0x0100},
  78         {VILLA_MSEQ_COEF8_FFE4_LSB, 0x0300},
  79         {VILLA_MSEQ_COEF8_FFE5_LSB, 0x0300},
  80         {VILLA_MSEQ_COEF8_DFE0_LSB, 0x0700},
  81         {VILLA_MSEQ_COEF8_DFE0N_LSB, 0x0E00},
  82         {VILLA_MSEQ_COEF8_DFE1_LSB, 0x0B00},
  83         {VILLA_DSP_SDS_DSP_COEF_LARGE_LEAK, 0x2},
  84         {VILLA_DSP_SDS_SERDES_SRX_DAC_ENABLEB_LSB, 0xD000},
  85         {VILLA_MSEQ_POWER_DOWN_LSB, 0xFFFF},
  86         {VILLA_MSEQ_POWER_DOWN_MSB, 0x0},
  87         {VILLA_MSEQ_CAL_RX_SLICER, 0x80},
  88         {VILLA_DSP_SDS_SERDES_SRX_DAC_BIAS_SELECT1_MSB, 0x3f},
  89         {VILLA_GLOBAL_MSEQCLKCTRL, 0x4},
  90         {VILLA_MSEQ_OPTIONS, 0x7},
  91
  92         /* set up min value for ffe1 */
  93         {VILLA_MSEQ_COEF_INIT_SEL, 0x2},
  94         {VILLA_DSP_SDS_DSP_PRECODEDINITFFE21, 0x41},
  95
  96         /* CS4315_sr_rx_pre_eq_set_4in */
  97         {VILLA_GLOBAL_MSEQCLKCTRL, 0x8004},
  98         {VILLA_MSEQ_OPTIONS, 0xf},
  99         {VILLA_MSEQ_BANKSELECT, 0x4},
 100         {VILLA_MSEQ_PC, 0x0},
 101
 102         /* for lengths from 3.5 to 4.5inches */
 103         {VILLA_MSEQ_SERDES_PARAM_LSB, 0x0306},
 104         {VILLA_MSEQ_SPARE25_LSB, 0x0306},
 105         {VILLA_MSEQ_SPARE21_LSB, 0x2},
 106         {VILLA_MSEQ_SPARE23_LSB, 0x2},
 107         {VILLA_MSEQ_CAL_RX_DFE_EQ, 0x0},
 108
 109         {VILLA_GLOBAL_MSEQCLKCTRL, 0x4},
 110         {VILLA_MSEQ_OPTIONS, 0x7},
 111
 112         /* CS4315_rx_drive_4inch */
 113         /* for length  4inches */
 114         {VILLA_GLOBAL_VILLA2_COMPATIBLE, 0x0000},
 115         {VILLA_HOST_SDS_COMMON_STX0_TX_OUTPUT_CTRLA, 0x3023},
 116         {VILLA_LINE_SDS_COMMON_STX0_TX_OUTPUT_CTRLB, 0xc01E},
 117
 118         /* CS4315_tx_drive_4inch */
 119         /* for length  4inches */
 120         {VILLA_GLOBAL_VILLA2_COMPATIBLE, 0x0000},
 121         {VILLA_LINE_SDS_COMMON_STX0_TX_OUTPUT_CTRLA, 0x3023},
 122         {VILLA_LINE_SDS_COMMON_STX0_TX_OUTPUT_CTRLB, 0xc01E},
 123 };
 124
 125 __weak ulong *cs4340_get_fw_addr(void)
 126 {
 127         return (ulong *)CONFIG_CORTINA_FW_ADDR;
 128 }
 129
 130 void cs4340_upload_firmware(struct phy_device *phydev)
 131 {
 132         char line_temp[0x50] = {0};
 133         char reg_addr[0x50] = {0};
 134         char reg_data[0x50] = {0};
 135         int i, line_cnt = 0, column_cnt = 0;
 136         struct cortina_reg_config fw_temp;
 137         char *addr = NULL;
 138         ulong cortina_fw_addr = (ulong)cs4340_get_fw_addr();
 139
 140 #ifdef CONFIG_TFABOOT
 141         enum boot_src src = get_boot_src();
 142
 143         if (src == BOOT_SOURCE_IFC_NOR) {
 144                 addr = (char *)cortina_fw_addr;
 145         } else if (src == BOOT_SOURCE_IFC_NAND) {
 146                 int ret;
 147                 size_t fw_length = CONFIG_CORTINA_FW_LENGTH;
 148
 149                 addr = malloc(CONFIG_CORTINA_FW_LENGTH);
 150                 ret = nand_read(get_nand_dev_by_index(0),
 151                                            (loff_t)cortina_fw_addr,     &fw_length, (u_char *)addr);
 152                 if (ret == -EUCLEAN) {
 153                         printf("NAND read of Cortina firmware at 0x%lx failed %d\n",
 154                                    cortina_fw_addr, ret);
 155                 }
 156         } else if (src == BOOT_SOURCE_QSPI_NOR) {
 157                 int ret;
 158                 struct spi_flash *ucode_flash;
 159
 160                 addr = malloc(CONFIG_CORTINA_FW_LENGTH);
 161                 ucode_flash = spi_flash_probe(CONFIG_SF_DEFAULT_BUS, CONFIG_SF_DEFAULT_CS,
 162                                                                          CONFIG_SF_DEFAULT_SPEED, CONFIG_SF_DEFAULT_MODE);
 163                 if (!ucode_flash) {
 164                         puts("SF: probe for Cortina ucode failed\n");
 165                 } else {
 166                         ret = spi_flash_read(ucode_flash, cortina_fw_addr,
 167                                                                 CONFIG_CORTINA_FW_LENGTH, addr);
 168                         if (ret)
 169                                 puts("SF: read for Cortina ucode failed\n");
 170                         spi_flash_free(ucode_flash);
 171                 }
 172         } else if (src == BOOT_SOURCE_SD_MMC) {
 173                 int dev = CONFIG_SYS_MMC_ENV_DEV;
 174                 u32 cnt = CONFIG_CORTINA_FW_LENGTH / 512;
 175                 u32 blk = cortina_fw_addr / 512;
 176                 struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV);
 177
 178                 if (!mmc) {
 179                         puts("Failed to find MMC device for Cortina ucode\n");
 180                 } else {
 181                         addr = malloc(CONFIG_CORTINA_FW_LENGTH);
 182                         printf("MMC read: dev # %u, block # %u, count %u ...\n",
 183                                   dev, blk, cnt);
 184                         mmc_init(mmc);
 185 #ifdef CONFIG_BLK
 186                         (void)blk_dread(mmc_get_blk_desc(mmc), blk, cnt, addr);
 187 #else
 188                         (void)mmc->block_dev.block_read(&mmc->block_dev, blk, cnt, addr);
 189 #endif
 190                 }
 191         }
 192 #else /* CONFIG_TFABOOT */
 193 #if defined(CONFIG_SYS_CORTINA_FW_IN_NOR) || \
 194         defined(CONFIG_SYS_CORTINA_FW_IN_REMOTE)
 195
 196         addr = (char *)cortina_fw_addr;
 197 #elif defined(CONFIG_SYS_CORTINA_FW_IN_NAND)
 198         int ret;
 199         size_t fw_length = CONFIG_CORTINA_FW_LENGTH;
 200
 201         addr = malloc(CONFIG_CORTINA_FW_LENGTH);
 202         ret = nand_read(get_nand_dev_by_index(0),
 203                         (loff_t)cortina_fw_addr,
 204                         &fw_length, (u_char *)addr);
 205         if (ret == -EUCLEAN) {
 206                 printf("NAND read of Cortina firmware at 0x%lx failed %d\n",
 207                        cortina_fw_addr, ret);
 208         }
 209 #elif defined(CONFIG_SYS_CORTINA_FW_IN_SPIFLASH)
 210         int ret;
 211         struct spi_flash *ucode_flash;
 212
 213         addr = malloc(CONFIG_CORTINA_FW_LENGTH);
 214         ucode_flash = spi_flash_probe(CONFIG_SF_DEFAULT_BUS, CONFIG_SF_DEFAULT_CS,
 215                                 CONFIG_SF_DEFAULT_SPEED, CONFIG_SF_DEFAULT_MODE);
 216         if (!ucode_flash) {
 217                 puts("SF: probe for Cortina ucode failed\n");
 218         } else {
 219                 ret = spi_flash_read(ucode_flash, cortina_fw_addr,
 220                                      CONFIG_CORTINA_FW_LENGTH, addr);
 221                 if (ret)
 222                         puts("SF: read for Cortina ucode failed\n");
 223                 spi_flash_free(ucode_flash);
 224         }
 225 #elif defined(CONFIG_SYS_CORTINA_FW_IN_MMC)
 226         int dev = CONFIG_SYS_MMC_ENV_DEV;
 227         u32 cnt = CONFIG_CORTINA_FW_LENGTH / 512;
 228         u32 blk = cortina_fw_addr / 512;
 229         struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV);
 230
 231         if (!mmc) {
 232                 puts("Failed to find MMC device for Cortina ucode\n");
 233         } else {
 234                 addr = malloc(CONFIG_CORTINA_FW_LENGTH);
 235                 printf("MMC read: dev # %u, block # %u, count %u ...\n",
 236                        dev, blk, cnt);
 237                 mmc_init(mmc);
 238 #ifdef CONFIG_BLK
 239                 (void)blk_dread(mmc_get_blk_desc(mmc), blk, cnt,
 240                                                 addr);
 241 #else
 242                 (void)mmc->block_dev.block_read(&mmc->block_dev, blk, cnt,
 243                                                 addr);
 244 #endif
 245         }
 246 #endif
 247 #endif
 248
 249         while (*addr != 'Q') {
 250                 i = 0;
 251
 252                 while (*addr != 0x0a) {
 253                         line_temp[i++] = *addr++;
 254                         if (0x50 < i) {
 255                                 printf("Not found Cortina PHY ucode at 0x%p\n",
 256                                        (char *)cortina_fw_addr);
 257                                 return;
 258                         }
 259                 }
 260
 261                 addr++;  /* skip '\n' */
 262                 line_cnt++;
 263                 column_cnt = i;
 264                 line_temp[column_cnt] = '\0';
 265
 266                 if (CONFIG_CORTINA_FW_LENGTH < line_cnt)
 267                         return;
 268
 269                 for (i = 0; i < column_cnt; i++) {
 270                         if (isspace(line_temp[i++]))
 271                                 break;
 272                 }
 273
 274                 memcpy(reg_addr, line_temp, i);
 275                 memcpy(reg_data, &line_temp[i], column_cnt - i);
 276                 strim(reg_addr);
 277                 strim(reg_data);
 278                 fw_temp.reg_addr = (simple_strtoul(reg_addr, NULL, 0)) & 0xffff;
 279                 fw_temp.reg_value = (simple_strtoul(reg_data, NULL, 0)) &
 280                                      0xffff;
 281                 phy_write(phydev, 0x00, fw_temp.reg_addr, fw_temp.reg_value);
 282         }
 283 }
 284 #endif
 285
 286 int cs4340_phy_init(struct phy_device *phydev)
 287 {
 288 #ifndef CONFIG_SYS_CORTINA_NO_FW_UPLOAD
 289         int timeout = 100;  /* 100ms */
 290 #endif
 291         int reg_value;
 292
 293         /*
 294          * Cortina phy has provision to store
 295          * phy firmware in attached dedicated EEPROM.
 296          * Boards designed with EEPROM attached to Cortina
 297          * does not require FW upload.
 298          */
 299 #ifndef CONFIG_SYS_CORTINA_NO_FW_UPLOAD
 300         /* step1: BIST test */
 301         phy_write(phydev, 0x00, VILLA_GLOBAL_MSEQCLKCTRL,     0x0004);
 302         phy_write(phydev, 0x00, VILLA_GLOBAL_LINE_SOFT_RESET, 0x0000);
 303         phy_write(phydev, 0x00, VILLA_GLOBAL_BIST_CONTROL,    0x0001);
 304         while (--timeout) {
 305                 reg_value = phy_read(phydev, 0x00, VILLA_GLOBAL_BIST_STATUS);
 306                 if (reg_value & mseq_edc_bist_done) {
 307                         if (0 == (reg_value & mseq_edc_bist_fail))
 308                                 break;
 309                 }
 310                 udelay(1000);
 311         }
 312
 313         if (!timeout) {
 314                 printf("%s BIST mseq_edc_bist_done timeout!\n", __func__);
 315                 return -1;
 316         }
 317
 318         /* setp2: upload ucode */
 319         cs4340_upload_firmware(phydev);
 320 #endif
 321         reg_value = phy_read(phydev, 0x00, VILLA_GLOBAL_DWNLD_CHECKSUM_STATUS);
 322         if (reg_value) {
 323                 debug("%s checksum status failed.\n", __func__);
 324                 return -1;
 325         }
 326
 327         return 0;
 328 }
 329
 330 int cs4340_config(struct phy_device *phydev)
 331 {
 332         cs4340_phy_init(phydev);
 333         return 0;
 334 }
 335
 336 int cs4340_probe(struct phy_device *phydev)
 337 {
 338         phydev->flags = PHY_FLAG_BROKEN_RESET;
 339         return 0;
 340 }
 341
 342 int cs4340_startup(struct phy_device *phydev)
 343 {
 344         phydev->link = 1;
 345
 346         /* For now just lie and say it's 10G all the time */
 347         phydev->speed = SPEED_10000;
 348         phydev->duplex = DUPLEX_FULL;
 349         return 0;
 350 }
 351
 352 int cs4223_phy_init(struct phy_device *phydev)
 353 {
 354         int reg_value;
 355
 356         reg_value = phy_read(phydev, 0x00, CS4223_EEPROM_STATUS);
 357         if (!(reg_value & CS4223_EEPROM_FIRMWARE_LOADDONE)) {
 358                 printf("%s CS4223 Firmware not present in EERPOM\n", __func__);
 359                 return -ENOSYS;
 360         }
 361
 362         return 0;
 363 }
 364
 365 int cs4223_config(struct phy_device *phydev)
 366 {
 367         return cs4223_phy_init(phydev);
 368 }
 369
 370 int cs4223_probe(struct phy_device *phydev)
 371 {
 372         phydev->flags = PHY_FLAG_BROKEN_RESET;
 373         return 0;
 374 }
 375
 376 int cs4223_startup(struct phy_device *phydev)
 377 {
 378         phydev->link = 1;
 379         phydev->speed = SPEED_10000;
 380         phydev->duplex = DUPLEX_FULL;
 381         return 0;
 382 }
 383
 384 U_BOOT_PHY_DRIVER(cs4340) = {
 385         .name = "Cortina CS4315/CS4340",
 386         .uid = PHY_UID_CS4340,
 387         .mask = 0xfffffff0,
 388         .features = PHY_10G_FEATURES,
 389         .mmds = (MDIO_DEVS_PMAPMD | MDIO_DEVS_PCS |
 390                  MDIO_DEVS_PHYXS | MDIO_DEVS_AN |
 391                  MDIO_DEVS_VEND1 | MDIO_DEVS_VEND2),
 392         .config = &cs4340_config,
 393         .probe  = &cs4340_probe,
 394         .startup = &cs4340_startup,
 395         .shutdown = &gen10g_shutdown,
 396 };
 397
 398 U_BOOT_PHY_DRIVER(cs4223) = {
 399         .name = "Cortina CS4223",
 400         .uid = PHY_UID_CS4223,
 401         .mask = 0x0ffff00f,
 402         .features = PHY_10G_FEATURES,
 403         .mmds = (MDIO_DEVS_PMAPMD | MDIO_DEVS_PCS |
 404                  MDIO_DEVS_AN),
 405         .config = &cs4223_config,
 406         .probe  = &cs4223_probe,
 407         .startup = &cs4223_startup,
 408         .shutdown = &gen10g_shutdown,
 409 };
 410
 411 int get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id)
 412 {
 413         int phy_reg;
 414
 415         /* Cortina PHY has non-standard offset of PHY ID registers */
 416         phy_reg = bus->read(bus, addr, 0, VILLA_GLOBAL_CHIP_ID_LSB);
 417         if (phy_reg < 0)
 418                 return -EIO;
 419         *phy_id = (phy_reg & 0xffff) << 16;
 420
 421         phy_reg = bus->read(bus, addr, 0, VILLA_GLOBAL_CHIP_ID_MSB);
 422         if (phy_reg < 0)
 423                 return -EIO;
 424         *phy_id |= (phy_reg & 0xffff);
 425
 426         if ((*phy_id == PHY_UID_CS4340) || (*phy_id == PHY_UID_CS4223))
 427                 return 0;
 428
 429         /*
 430          * If Cortina PHY not detected,
 431          * try generic way to find PHY ID registers
 432          */
 433         phy_reg = bus->read(bus, addr, devad, MII_PHYSID1);
 434         if (phy_reg < 0)
 435                 return -EIO;
 436         *phy_id = (phy_reg & 0xffff) << 16;
 437
 438         phy_reg = bus->read(bus, addr, devad, MII_PHYSID2);
 439         if (phy_reg < 0)
 440                 return -EIO;
 441         *phy_id |= (phy_reg & 0xffff);
 442
 443         return 0;
 444 }