drivers/i2c/exynos_hs_i2c.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (c) 2016, Google Inc
   4  *
   5  * (C) Copyright 2002
   6  * David Mueller, ELSOFT AG, [email protected]
   7  */
   8
   9 #include <dm.h>
  10 #include <i2c.h>
  11 #include <log.h>
  12 #if IS_ENABLED(CONFIG_ARCH_EXYNOS4) || IS_ENABLED(CONFIG_ARCH_EXYNOS5)
  13 #include <asm/arch/clk.h>
  14 #include <asm/arch/cpu.h>
  15 #include <asm/arch/pinmux.h>
  16 #endif
  17 #include <asm/global_data.h>
  18 #include <asm/io.h>
  19 #include <linux/delay.h>
  20 #include <clk.h>
  21 #include "s3c24x0_i2c.h"
  22
  23 DECLARE_GLOBAL_DATA_PTR;
  24
  25 /* HSI2C-specific register description */
  26
  27 /* I2C_CTL Register bits */
  28 #define HSI2C_FUNC_MODE_I2C             (1u << 0)
  29 #define HSI2C_MASTER                    (1u << 3)
  30 #define HSI2C_RXCHON                    (1u << 6)       /* Write/Send */
  31 #define HSI2C_TXCHON                    (1u << 7)       /* Read/Receive */
  32 #define HSI2C_SW_RST                    (1u << 31)
  33
  34 /* I2C_FIFO_CTL Register bits */
  35 #define HSI2C_RXFIFO_EN                 (1u << 0)
  36 #define HSI2C_TXFIFO_EN                 (1u << 1)
  37 #define HSI2C_TXFIFO_TRIGGER_LEVEL      (0x20 << 16)
  38 #define HSI2C_RXFIFO_TRIGGER_LEVEL      (0x20 << 4)
  39
  40 /* I2C_TRAILING_CTL Register bits */
  41 #define HSI2C_TRAILING_COUNT            (0xff)
  42
  43 /* I2C_INT_EN Register bits */
  44 #define HSI2C_TX_UNDERRUN_EN            (1u << 2)
  45 #define HSI2C_TX_OVERRUN_EN             (1u << 3)
  46 #define HSI2C_RX_UNDERRUN_EN            (1u << 4)
  47 #define HSI2C_RX_OVERRUN_EN             (1u << 5)
  48 #define HSI2C_INT_TRAILING_EN           (1u << 6)
  49 #define HSI2C_INT_I2C_EN                (1u << 9)
  50
  51 #define HSI2C_INT_ERROR_MASK    (HSI2C_TX_UNDERRUN_EN |\
  52                                  HSI2C_TX_OVERRUN_EN  |\
  53                                  HSI2C_RX_UNDERRUN_EN |\
  54                                  HSI2C_RX_OVERRUN_EN  |\
  55                                  HSI2C_INT_TRAILING_EN)
  56
  57 /* I2C_CONF Register bits */
  58 #define HSI2C_AUTO_MODE                 (1u << 31)
  59 #define HSI2C_10BIT_ADDR_MODE           (1u << 30)
  60 #define HSI2C_HS_MODE                   (1u << 29)
  61
  62 /* I2C_AUTO_CONF Register bits */
  63 #define HSI2C_READ_WRITE                (1u << 16)
  64 #define HSI2C_STOP_AFTER_TRANS          (1u << 17)
  65 #define HSI2C_MASTER_RUN                (1u << 31)
  66
  67 /* I2C_TIMEOUT Register bits */
  68 #define HSI2C_TIMEOUT_EN                (1u << 31)
  69
  70 /* I2C_TRANS_STATUS register bits */
  71 #define HSI2C_MASTER_BUSY               (1u << 17)
  72 #define HSI2C_SLAVE_BUSY                (1u << 16)
  73 #define HSI2C_TIMEOUT_AUTO              (1u << 4)
  74 #define HSI2C_NO_DEV                    (1u << 3)
  75 #define HSI2C_NO_DEV_ACK                (1u << 2)
  76 #define HSI2C_TRANS_ABORT               (1u << 1)
  77 #define HSI2C_TRANS_SUCCESS             (1u << 0)
  78 #define HSI2C_TRANS_ERROR_MASK  (HSI2C_TIMEOUT_AUTO |\
  79                                  HSI2C_NO_DEV | HSI2C_NO_DEV_ACK |\
  80                                  HSI2C_TRANS_ABORT)
  81 #define HSI2C_TRANS_FINISHED_MASK (HSI2C_TRANS_ERROR_MASK | HSI2C_TRANS_SUCCESS)
  82
  83 /* I2C_FIFO_STAT Register bits */
  84 #define HSI2C_RX_FIFO_EMPTY             (1u << 24)
  85 #define HSI2C_RX_FIFO_FULL              (1u << 23)
  86 #define HSI2C_TX_FIFO_EMPTY             (1u << 8)
  87 #define HSI2C_TX_FIFO_FULL              (1u << 7)
  88 #define HSI2C_RX_FIFO_LEVEL(x)          (((x) >> 16) & 0x7f)
  89 #define HSI2C_TX_FIFO_LEVEL(x)          ((x) & 0x7f)
  90
  91 #define HSI2C_SLV_ADDR_MAS(x)           ((x & 0x3ff) << 10)
  92
  93 #define HSI2C_TIMEOUT_US 10000 /* 10 ms, finer granularity */
  94
  95 /*
  96  * Wait for transfer completion.
  97  *
  98  * This function reads the interrupt status register waiting for the INT_I2C
  99  * bit to be set, which indicates copletion of a transaction.
 100  *
 101  * @param i2c: pointer to the appropriate register bank
 102  *
 103  * @return: I2C_OK in case of successful completion, I2C_NOK_TIMEOUT in case
 104  *          the status bits do not get set in time, or an approrpiate error
 105  *          value in case of transfer errors.
 106  */
 107 static int hsi2c_wait_for_trx(struct exynos5_hsi2c *i2c)
 108 {
 109         int i = HSI2C_TIMEOUT_US;
 110
 111         while (i-- > 0) {
 112                 u32 int_status = readl(&i2c->usi_int_stat);
 113
 114                 if (int_status & HSI2C_INT_I2C_EN) {
 115                         u32 trans_status = readl(&i2c->usi_trans_status);
 116
 117                         /* Deassert pending interrupt. */
 118                         writel(int_status, &i2c->usi_int_stat);
 119
 120                         if (trans_status & HSI2C_NO_DEV_ACK) {
 121                                 debug("%s: no ACK from device\n", __func__);
 122                                 return I2C_NACK;
 123                         }
 124                         if (trans_status & HSI2C_NO_DEV) {
 125                                 debug("%s: no device\n", __func__);
 126                                 return I2C_NOK;
 127                         }
 128                         if (trans_status & HSI2C_TRANS_ABORT) {
 129                                 debug("%s: arbitration lost\n", __func__);
 130                                 return I2C_NOK_LA;
 131                         }
 132                         if (trans_status & HSI2C_TIMEOUT_AUTO) {
 133                                 debug("%s: device timed out\n", __func__);
 134                                 return I2C_NOK_TOUT;
 135                         }
 136                         return I2C_OK;
 137                 }
 138                 udelay(1);
 139         }
 140         debug("%s: transaction timeout!\n", __func__);
 141         return I2C_NOK_TOUT;
 142 }
 143
 144 static int hsi2c_get_clk_details(struct udevice *dev)
 145 {
 146         struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
 147         struct exynos5_hsi2c *hsregs = i2c_bus->hsregs;
 148         ulong clkin;
 149         unsigned int op_clk = i2c_bus->clock_frequency;
 150         unsigned int i = 0, utemp0 = 0, utemp1 = 0;
 151         unsigned int t_ftl_cycle;
 152
 153 #if IS_ENABLED(CONFIG_ARCH_EXYNOS4) || IS_ENABLED(CONFIG_ARCH_EXYNOS5)
 154         clkin = get_i2c_clk();
 155 #else
 156         struct clk clk;
 157         int ret;
 158
 159         ret = clk_get_by_name(dev, "hsi2c", &clk);
 160         if (ret < 0)
 161                 return ret;
 162         clkin = clk_get_rate(&clk);
 163 #endif
 164         /* FPCLK / FI2C =
 165          * (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) + 8 + 2 * FLT_CYCLE
 166          * uTemp0 = (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2)
 167          * uTemp1 = (TSCLK_L + TSCLK_H + 2)
 168          * uTemp2 = TSCLK_L + TSCLK_H
 169          */
 170         t_ftl_cycle = (readl(&hsregs->usi_conf) >> 16) & 0x7;
 171         utemp0 = (clkin / op_clk) - 8 - 2 * t_ftl_cycle;
 172
 173         /* CLK_DIV max is 256 */
 174         for (i = 0; i < 256; i++) {
 175                 utemp1 = utemp0 / (i + 1);
 176                 if ((utemp1 < 512) && (utemp1 > 4)) {
 177                         i2c_bus->clk_cycle = utemp1 - 2;
 178                         i2c_bus->clk_div = i;
 179                         return 0;
 180                 }
 181         }
 182         return -EINVAL;
 183 }
 184
 185 static void hsi2c_ch_init(struct s3c24x0_i2c_bus *i2c_bus)
 186 {
 187         struct exynos5_hsi2c *hsregs = i2c_bus->hsregs;
 188         unsigned int t_sr_release;
 189         unsigned int n_clkdiv;
 190         unsigned int t_start_su, t_start_hd;
 191         unsigned int t_stop_su;
 192         unsigned int t_data_su, t_data_hd;
 193         unsigned int t_scl_l, t_scl_h;
 194         u32 i2c_timing_s1;
 195         u32 i2c_timing_s2;
 196         u32 i2c_timing_s3;
 197         u32 i2c_timing_sla;
 198
 199         n_clkdiv = i2c_bus->clk_div;
 200         t_scl_l = i2c_bus->clk_cycle / 2;
 201         t_scl_h = i2c_bus->clk_cycle / 2;
 202         t_start_su = t_scl_l;
 203         t_start_hd = t_scl_l;
 204         t_stop_su = t_scl_l;
 205         t_data_su = t_scl_l / 2;
 206         t_data_hd = t_scl_l / 2;
 207         t_sr_release = i2c_bus->clk_cycle;
 208
 209         i2c_timing_s1 = t_start_su << 24 | t_start_hd << 16 | t_stop_su << 8;
 210         i2c_timing_s2 = t_data_su << 24 | t_scl_l << 8 | t_scl_h << 0;
 211         i2c_timing_s3 = n_clkdiv << 16 | t_sr_release << 0;
 212         i2c_timing_sla = t_data_hd << 0;
 213
 214         writel(HSI2C_TRAILING_COUNT, &hsregs->usi_trailing_ctl);
 215
 216         /* Clear to enable Timeout */
 217         clrsetbits_le32(&hsregs->usi_timeout, HSI2C_TIMEOUT_EN, 0);
 218
 219         /* set AUTO mode */
 220         writel(readl(&hsregs->usi_conf) | HSI2C_AUTO_MODE, &hsregs->usi_conf);
 221
 222         /* Enable completion conditions' reporting. */
 223         writel(HSI2C_INT_I2C_EN, &hsregs->usi_int_en);
 224
 225         /* Enable FIFOs */
 226         writel(HSI2C_RXFIFO_EN | HSI2C_TXFIFO_EN, &hsregs->usi_fifo_ctl);
 227
 228         /* Currently operating in Fast speed mode. */
 229         writel(i2c_timing_s1, &hsregs->usi_timing_fs1);
 230         writel(i2c_timing_s2, &hsregs->usi_timing_fs2);
 231         writel(i2c_timing_s3, &hsregs->usi_timing_fs3);
 232         writel(i2c_timing_sla, &hsregs->usi_timing_sla);
 233 }
 234
 235 /* SW reset for the high speed bus */
 236 static void exynos5_i2c_reset(struct s3c24x0_i2c_bus *i2c_bus)
 237 {
 238         struct exynos5_hsi2c *i2c = i2c_bus->hsregs;
 239         u32 i2c_ctl;
 240
 241         /* Set and clear the bit for reset */
 242         i2c_ctl = readl(&i2c->usi_ctl);
 243         i2c_ctl |= HSI2C_SW_RST;
 244         writel(i2c_ctl, &i2c->usi_ctl);
 245
 246         i2c_ctl = readl(&i2c->usi_ctl);
 247         i2c_ctl &= ~HSI2C_SW_RST;
 248         writel(i2c_ctl, &i2c->usi_ctl);
 249
 250         /* Initialize the configure registers */
 251         hsi2c_ch_init(i2c_bus);
 252 }
 253
 254 /*
 255  * Poll the appropriate bit of the fifo status register until the interface is
 256  * ready to process the next byte or timeout expires.
 257  *
 258  * In addition to the FIFO status register this function also polls the
 259  * interrupt status register to be able to detect unexpected transaction
 260  * completion.
 261  *
 262  * When FIFO is ready to process the next byte, this function returns I2C_OK.
 263  * If in course of polling the INT_I2C assertion is detected, the function
 264  * returns I2C_NOK. If timeout happens before any of the above conditions is
 265  * met - the function returns I2C_NOK_TOUT;
 266
 267  * @param i2c: pointer to the appropriate i2c register bank.
 268  * @param rx_transfer: set to True if the receive transaction is in progress.
 269  * @return: as described above.
 270  */
 271 static unsigned hsi2c_poll_fifo(struct exynos5_hsi2c *i2c, bool rx_transfer)
 272 {
 273         u32 fifo_bit = rx_transfer ? HSI2C_RX_FIFO_EMPTY : HSI2C_TX_FIFO_FULL;
 274         int i = HSI2C_TIMEOUT_US;
 275
 276         while (readl(&i2c->usi_fifo_stat) & fifo_bit) {
 277                 if (readl(&i2c->usi_int_stat) & HSI2C_INT_I2C_EN) {
 278                         /*
 279                          * There is a chance that assertion of
 280                          * HSI2C_INT_I2C_EN and deassertion of
 281                          * HSI2C_RX_FIFO_EMPTY happen simultaneously. Let's
 282                          * give FIFO status priority and check it one more
 283                          * time before reporting interrupt. The interrupt will
 284                          * be reported next time this function is called.
 285                          */
 286                         if (rx_transfer &&
 287                             !(readl(&i2c->usi_fifo_stat) & fifo_bit))
 288                                 break;
 289                         return I2C_NOK;
 290                 }
 291                 if (!i--) {
 292                         debug("%s: FIFO polling timeout!\n", __func__);
 293                         return I2C_NOK_TOUT;
 294                 }
 295                 udelay(1);
 296         }
 297         return I2C_OK;
 298 }
 299
 300 /*
 301  * Preapre hsi2c transaction, either read or write.
 302  *
 303  * Set up transfer as described in section 27.5.1.2 'I2C Channel Auto Mode' of
 304  * the 5420 UM.
 305  *
 306  * @param i2c: pointer to the appropriate i2c register bank.
 307  * @param chip: slave address on the i2c bus (with read/write bit exlcuded)
 308  * @param len: number of bytes expected to be sent or received
 309  * @param rx_transfer: set to true for receive transactions
 310  * @param: issue_stop: set to true if i2c stop condition should be generated
 311  *         after this transaction.
 312  * @return: I2C_NOK_TOUT in case the bus remained busy for HSI2C_TIMEOUT_US,
 313  *          I2C_OK otherwise.
 314  */
 315 static int hsi2c_prepare_transaction(struct exynos5_hsi2c *i2c,
 316                                      u8 chip,
 317                                      u16 len,
 318                                      bool rx_transfer,
 319                                      bool issue_stop)
 320 {
 321         u32 conf;
 322
 323         conf = len | HSI2C_MASTER_RUN;
 324
 325         if (issue_stop)
 326                 conf |= HSI2C_STOP_AFTER_TRANS;
 327
 328         /* Clear to enable Timeout */
 329         writel(readl(&i2c->usi_timeout) & ~HSI2C_TIMEOUT_EN, &i2c->usi_timeout);
 330
 331         /* Set slave address */
 332         writel(HSI2C_SLV_ADDR_MAS(chip), &i2c->i2c_addr);
 333
 334         if (rx_transfer) {
 335                 /* i2c master, read transaction */
 336                 writel((HSI2C_RXCHON | HSI2C_FUNC_MODE_I2C | HSI2C_MASTER),
 337                        &i2c->usi_ctl);
 338
 339                 /* read up to len bytes, stop after transaction is finished */
 340                 writel(conf | HSI2C_READ_WRITE, &i2c->usi_auto_conf);
 341         } else {
 342                 /* i2c master, write transaction */
 343                 writel((HSI2C_TXCHON | HSI2C_FUNC_MODE_I2C | HSI2C_MASTER),
 344                        &i2c->usi_ctl);
 345
 346                 /* write up to len bytes, stop after transaction is finished */
 347                 writel(conf, &i2c->usi_auto_conf);
 348         }
 349
 350         /* Reset all pending interrupt status bits we care about, if any */
 351         writel(HSI2C_INT_I2C_EN, &i2c->usi_int_stat);
 352
 353         return I2C_OK;
 354 }
 355
 356 /*
 357  * Wait while i2c bus is settling down (mostly stop gets completed).
 358  */
 359 static int hsi2c_wait_while_busy(struct exynos5_hsi2c *i2c)
 360 {
 361         int i = HSI2C_TIMEOUT_US;
 362
 363         while (readl(&i2c->usi_trans_status) & HSI2C_MASTER_BUSY) {
 364                 if (!i--) {
 365                         debug("%s: bus busy\n", __func__);
 366                         return I2C_NOK_TOUT;
 367                 }
 368                 udelay(1);
 369         }
 370         return I2C_OK;
 371 }
 372
 373 static int hsi2c_write(struct exynos5_hsi2c *i2c,
 374                        unsigned char chip,
 375                        unsigned char addr[],
 376                        unsigned char alen,
 377                        unsigned char data[],
 378                        unsigned short len,
 379                        bool issue_stop)
 380 {
 381         int i, rv = 0;
 382
 383         if (!(len + alen)) {
 384                 /* Writes of zero length not supported in auto mode. */
 385                 debug("%s: zero length writes not supported\n", __func__);
 386                 return I2C_NOK;
 387         }
 388
 389         rv = hsi2c_prepare_transaction
 390                 (i2c, chip, len + alen, false, issue_stop);
 391         if (rv != I2C_OK)
 392                 return rv;
 393
 394         /* Move address, if any, and the data, if any, into the FIFO. */
 395         for (i = 0; i < alen; i++) {
 396                 rv = hsi2c_poll_fifo(i2c, false);
 397                 if (rv != I2C_OK) {
 398                         debug("%s: address write failed\n", __func__);
 399                         goto write_error;
 400                 }
 401                 writel(addr[i], &i2c->usi_txdata);
 402         }
 403
 404         for (i = 0; i < len; i++) {
 405                 rv = hsi2c_poll_fifo(i2c, false);
 406                 if (rv != I2C_OK) {
 407                         debug("%s: data write failed\n", __func__);
 408                         goto write_error;
 409                 }
 410                 writel(data[i], &i2c->usi_txdata);
 411         }
 412
 413         rv = hsi2c_wait_for_trx(i2c);
 414
 415  write_error:
 416         if (issue_stop) {
 417                 int tmp_ret = hsi2c_wait_while_busy(i2c);
 418                 if (rv == I2C_OK)
 419                         rv = tmp_ret;
 420         }
 421
 422         writel(HSI2C_FUNC_MODE_I2C, &i2c->usi_ctl); /* done */
 423         return rv;
 424 }
 425
 426 static int hsi2c_read(struct exynos5_hsi2c *i2c,
 427                       unsigned char chip,
 428                       unsigned char addr[],
 429                       unsigned char alen,
 430                       unsigned char data[],
 431                       unsigned short len)
 432 {
 433         int i, rv, tmp_ret;
 434         bool drop_data = false;
 435
 436         if (!len) {
 437                 /* Reads of zero length not supported in auto mode. */
 438                 debug("%s: zero length read adjusted\n", __func__);
 439                 drop_data = true;
 440                 len = 1;
 441         }
 442
 443         if (alen) {
 444                 /* Internal register adress needs to be written first. */
 445                 rv = hsi2c_write(i2c, chip, addr, alen, NULL, 0, false);
 446                 if (rv != I2C_OK)
 447                         return rv;
 448         }
 449
 450         rv = hsi2c_prepare_transaction(i2c, chip, len, true, true);
 451
 452         if (rv != I2C_OK)
 453                 return rv;
 454
 455         for (i = 0; i < len; i++) {
 456                 rv = hsi2c_poll_fifo(i2c, true);
 457                 if (rv != I2C_OK)
 458                         goto read_err;
 459                 if (drop_data)
 460                         continue;
 461                 data[i] = readl(&i2c->usi_rxdata);
 462         }
 463
 464         rv = hsi2c_wait_for_trx(i2c);
 465
 466  read_err:
 467         tmp_ret = hsi2c_wait_while_busy(i2c);
 468         if (rv == I2C_OK)
 469                 rv = tmp_ret;
 470
 471         writel(HSI2C_FUNC_MODE_I2C, &i2c->usi_ctl); /* done */
 472         return rv;
 473 }
 474
 475 static int exynos_hs_i2c_xfer(struct udevice *dev, struct i2c_msg *msg,
 476                               int nmsgs)
 477 {
 478         struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
 479         struct exynos5_hsi2c *hsregs = i2c_bus->hsregs;
 480         int ret;
 481
 482         for (; nmsgs > 0; nmsgs--, msg++) {
 483                 if (msg->flags & I2C_M_RD) {
 484                         ret = hsi2c_read(hsregs, msg->addr, 0, 0, msg->buf,
 485                                          msg->len);
 486                 } else {
 487                         ret = hsi2c_write(hsregs, msg->addr, 0, 0, msg->buf,
 488                                           msg->len, true);
 489                 }
 490                 if (ret) {
 491                         exynos5_i2c_reset(i2c_bus);
 492                         return -EREMOTEIO;
 493                 }
 494         }
 495
 496         return 0;
 497 }
 498
 499 static int s3c24x0_i2c_set_bus_speed(struct udevice *dev, unsigned int speed)
 500 {
 501         struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
 502
 503         i2c_bus->clock_frequency = speed;
 504
 505         if (hsi2c_get_clk_details(dev))
 506                 return -EFAULT;
 507         hsi2c_ch_init(i2c_bus);
 508
 509         return 0;
 510 }
 511
 512 static int s3c24x0_i2c_probe(struct udevice *dev, uint chip, uint chip_flags)
 513 {
 514         struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
 515         uchar buf[1];
 516         int ret;
 517
 518         buf[0] = 0;
 519
 520         /*
 521          * What is needed is to send the chip address and verify that the
 522          * address was <ACK>ed (i.e. there was a chip at that address which
 523          * drove the data line low).
 524          */
 525         ret = hsi2c_read(i2c_bus->hsregs, chip, 0, 0, buf, 1);
 526
 527         return ret != I2C_OK;
 528 }
 529
 530 static int s3c_i2c_of_to_plat(struct udevice *dev)
 531 {
 532 #if IS_ENABLED(CONFIG_ARCH_EXYNOS4) || IS_ENABLED(CONFIG_ARCH_EXYNOS5)
 533         const void *blob = gd->fdt_blob;
 534 #endif
 535         struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
 536         int node;
 537
 538         node = dev_of_offset(dev);
 539
 540         i2c_bus->hsregs = dev_read_addr_ptr(dev);
 541
 542 #if IS_ENABLED(CONFIG_ARCH_EXYNOS4) || IS_ENABLED(CONFIG_ARCH_EXYNOS5)
 543         i2c_bus->id = pinmux_decode_periph_id(blob, node);
 544 #endif
 545
 546         i2c_bus->clock_frequency =
 547                 dev_read_u32_default(dev, "clock-frequency",
 548                                      I2C_SPEED_STANDARD_RATE);
 549         i2c_bus->node = node;
 550         i2c_bus->bus_num = dev_seq(dev);
 551
 552 #if IS_ENABLED(CONFIG_ARCH_EXYNOS4) || IS_ENABLED(CONFIG_ARCH_EXYNOS5)
 553         exynos_pinmux_config(i2c_bus->id, PINMUX_FLAG_HS_MODE);
 554 #endif
 555
 556         i2c_bus->active = true;
 557
 558         return 0;
 559 }
 560
 561 static const struct dm_i2c_ops exynos_hs_i2c_ops = {
 562         .xfer           = exynos_hs_i2c_xfer,
 563         .probe_chip     = s3c24x0_i2c_probe,
 564         .set_bus_speed  = s3c24x0_i2c_set_bus_speed,
 565 };
 566
 567 static const struct udevice_id exynos_hs_i2c_ids[] = {
 568         { .compatible = "samsung,exynos5-hsi2c" },
 569         { }
 570 };
 571
 572 U_BOOT_DRIVER(hs_i2c) = {
 573         .name   = "i2c_s3c_hs",
 574         .id     = UCLASS_I2C,
 575         .of_match = exynos_hs_i2c_ids,
 576         .of_to_plat = s3c_i2c_of_to_plat,
 577         .priv_auto      = sizeof(struct s3c24x0_i2c_bus),
 578         .ops    = &exynos_hs_i2c_ops,
 579 };