arch/arm/dts/stm32mp15-u-boot.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
   2 /*
   3  * Copyright : STMicroelectronics 2018
   4  */
   5
   6 / {
   7         aliases {
   8                 gpio0 = &gpioa;
   9                 gpio1 = &gpiob;
  10                 gpio2 = &gpioc;
  11                 gpio3 = &gpiod;
  12                 gpio4 = &gpioe;
  13                 gpio5 = &gpiof;
  14                 gpio6 = &gpiog;
  15                 gpio7 = &gpioh;
  16                 gpio8 = &gpioi;
  17                 gpio9 = &gpioj;
  18                 gpio10 = &gpiok;
  19                 gpio25 = &gpioz;
  20                 pinctrl0 = &pinctrl;
  21                 pinctrl1 = &pinctrl_z;
  22         };
  23
  24         binman: binman {
  25                 multiple-images;
  26         };
  27
  28         clocks {
  29                 bootph-all;
  30         };
  31
  32         /* need PSCI for sysreset during board_f */
  33         psci {
  34                 bootph-some-ram;
  35         };
  36
  37         reboot {
  38                 bootph-all;
  39                 compatible = "syscon-reboot";
  40                 regmap = <&rcc>;
  41                 offset = <0x404>;
  42                 mask = <0x1>;
  43         };
  44
  45         soc {
  46                 bootph-all;
  47
  48                 ddr: ddr@5a003000 {
  49                         bootph-all;
  50
  51                         compatible = "st,stm32mp1-ddr";
  52
  53                         reg = <0x5a003000 0x550
  54                                0x5a004000 0x234>;
  55
  56                         status = "okay";
  57                 };
  58         };
  59
  60         cpu0_opp_table: cpu0-opp-table {
  61                 compatible = "operating-points-v2";
  62                 opp-shared;
  63                 bootph-pre-ram;
  64                 opp-650000000 {
  65                         bootph-pre-ram;
  66                         opp-hz = /bits/ 64 <650000000>;
  67                         opp-microvolt = <1200000>;
  68                         opp-supported-hw = <0x1>;
  69                 };
  70                 opp-800000000 {
  71                         bootph-pre-ram;
  72                         opp-hz = /bits/ 64 <800000000>;
  73                         opp-microvolt = <1350000>;
  74                         opp-supported-hw = <0x2>;
  75                 };
  76         };
  77 };
  78
  79 &bsec {
  80         bootph-all;
  81 };
  82
  83 &clk_csi {
  84         bootph-all;
  85 };
  86
  87 &clk_hsi {
  88         bootph-all;
  89 };
  90
  91 &clk_hse {
  92         bootph-all;
  93 };
  94
  95 &clk_lsi {
  96         bootph-all;
  97 };
  98
  99 &clk_lse {
 100         bootph-all;
 101 };
 102
 103 &cpu0 {
 104         nvmem-cells = <&part_number_otp>;
 105         nvmem-cell-names = "part_number";
 106         operating-points-v2 = <&cpu0_opp_table>;
 107 };
 108
 109 &gpioa {
 110         bootph-all;
 111 };
 112
 113 &gpiob {
 114         bootph-all;
 115 };
 116
 117 &gpioc {
 118         bootph-all;
 119 };
 120
 121 &gpiod {
 122         bootph-all;
 123 };
 124
 125 &gpioe {
 126         bootph-all;
 127 };
 128
 129 &gpiof {
 130         bootph-all;
 131 };
 132
 133 &gpiog {
 134         bootph-all;
 135 };
 136
 137 &gpioh {
 138         bootph-all;
 139 };
 140
 141 &gpioi {
 142         bootph-all;
 143 };
 144
 145 &gpioj {
 146         bootph-all;
 147 };
 148
 149 &gpiok {
 150         bootph-all;
 151 };
 152
 153 &gpioz {
 154         bootph-all;
 155 };
 156
 157 &iwdg2 {
 158         bootph-all;
 159 };
 160
 161 /* pre-reloc probe = reserve video frame buffer in video_reserve() */
 162 &ltdc {
 163         bootph-some-ram;
 164 };
 165
 166 /* temp = waiting kernel update */
 167 &m4_rproc {
 168         resets = <&rcc MCU_R>,
 169                  <&rcc MCU_HOLD_BOOT_R>;
 170         reset-names = "mcu_rst", "hold_boot";
 171 };
 172
 173 &pinctrl {
 174         bootph-all;
 175 };
 176
 177 &pinctrl_z {
 178         bootph-all;
 179 };
 180
 181 &pwr_regulators {
 182         bootph-all;
 183 };
 184
 185 &rcc {
 186         bootph-all;
 187         #address-cells = <1>;
 188         #size-cells = <0>;
 189         clock-names = "hse", "hsi", "csi", "lse", "lsi";
 190         clocks = <&clk_hse>, <&clk_hsi>, <&clk_csi>,
 191                  <&clk_lse>, <&clk_lsi>;
 192 };
 193
 194 &usart1 {
 195         resets = <&rcc USART1_R>;
 196 };
 197
 198 &usart2 {
 199         resets = <&rcc USART2_R>;
 200 };
 201
 202 &usart3 {
 203         resets = <&rcc USART3_R>;
 204 };
 205
 206 &uart4 {
 207         resets = <&rcc UART4_R>;
 208 };
 209
 210 &uart5 {
 211         resets = <&rcc UART5_R>;
 212 };
 213
 214 &usart6 {
 215         resets = <&rcc USART6_R>;
 216 };
 217
 218 &uart7 {
 219         resets = <&rcc UART7_R>;
 220 };
 221
 222 &uart8{
 223         resets = <&rcc UART8_R>;
 224 };
 225
 226 #if defined(CONFIG_STM32MP15X_STM32IMAGE)
 227 &binman {
 228         u-boot-stm32 {
 229                 filename = "u-boot.stm32";
 230                 mkimage {
 231                         args = "-T stm32image -a 0xc0100000 -e 0xc0100000";
 232                         u-boot {
 233                         };
 234                 };
 235         };
 236 };
 237 #endif
 238
 239 #if defined(CONFIG_SPL)
 240 &binman {
 241         spl-stm32 {
 242                 filename = "u-boot-spl.stm32";
 243                 mkimage {
 244                         args = "-T stm32image -a 0x2ffc2500 -e 0x2ffc2500";
 245                         u-boot-spl {
 246                                 no-write-symbols;
 247                         };
 248                 };
 249         };
 250 };
 251 #endif