arch/arm/dts/fsl-ls1088a-ten64.dts

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Device Tree file for Traverse Technologies Ten64
   4  * (LS1088A) board
   5  * Based on fsl-ls1088a-rdb.dts
   6  * Copyright 2017-2020 NXP
   7  * Copyright 2019-2023 Traverse Technologies
   8  *
   9  * Author: Mathew McBride <[email protected]>
  10  */
  11
  12 /dts-v1/;
  13
  14 #include "fsl-ls1088a.dtsi"
  15
  16 #include <dt-bindings/gpio/gpio.h>
  17 #include <dt-bindings/input/input.h>
  18
  19 / {
  20         model = "Traverse Ten64";
  21         compatible = "traverse,ten64", "fsl,ls1088a";
  22
  23         aliases {
  24                 serial0 = &duart0;
  25                 serial1 = &duart1;
  26         };
  27
  28         chosen {
  29                 stdout-path = "serial0:115200n8";
  30         };
  31
  32         buttons {
  33                 compatible = "gpio-keys";
  34
  35                 /* Fired by system controller when
  36                  * external power off (e.g ATX Power Button)
  37                  * asserted
  38                  */
  39                 button-powerdn {
  40                         label = "External Power Down";
  41                         gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
  42                         linux,code = <KEY_POWER>;
  43                 };
  44
  45                 /* Rear Panel 'ADMIN' button (GPIO_H) */
  46                 button-admin {
  47                         label = "ADMIN button";
  48                         gpios = <&gpio3 8 GPIO_ACTIVE_HIGH>;
  49                         linux,code = <KEY_WPS_BUTTON>;
  50                 };
  51         };
  52
  53         leds {
  54                 compatible = "gpio-leds";
  55
  56                 led-0 {
  57                         label = "ten64:green:sfp1:down";
  58                         gpios = <&gpio3 11 GPIO_ACTIVE_HIGH>;
  59                 };
  60
  61                 led-1 {
  62                         label = "ten64:green:sfp2:up";
  63                         gpios = <&gpio3 12 GPIO_ACTIVE_HIGH>;
  64                 };
  65
  66                 led-2 {
  67                         label = "ten64:admin";
  68                         gpios = <&sfpgpio 12 GPIO_ACTIVE_HIGH>;
  69                 };
  70         };
  71
  72         sfp_xg0: dpmac2-sfp {
  73                 compatible = "sff,sfp";
  74                 i2c-bus = <&sfplower_i2c>;
  75                 tx-fault-gpios = <&sfpgpio 0 GPIO_ACTIVE_HIGH>;
  76                 tx-disable-gpios = <&sfpgpio 1 GPIO_ACTIVE_HIGH>;
  77                 mod-def0-gpios = <&sfpgpio 2 GPIO_ACTIVE_LOW>;
  78                 los-gpios = <&sfpgpio 3 GPIO_ACTIVE_HIGH>;
  79                 maximum-power-milliwatt = <2000>;
  80         };
  81
  82         sfp_xg1: dpmac1-sfp {
  83                 compatible = "sff,sfp";
  84                 i2c-bus = <&sfpupper_i2c>;
  85                 tx-fault-gpios = <&sfpgpio 4 GPIO_ACTIVE_HIGH>;
  86                 tx-disable-gpios = <&sfpgpio 5 GPIO_ACTIVE_HIGH>;
  87                 mod-def0-gpios = <&sfpgpio 6 GPIO_ACTIVE_LOW>;
  88                 los-gpios = <&sfpgpio 7 GPIO_ACTIVE_HIGH>;
  89                 maximum-power-milliwatt = <2000>;
  90         };
  91 };
  92
  93 /* XG1 - Upper SFP */
  94 &dpmac1 {
  95         sfp = <&sfp_xg1>;
  96         pcs-handle = <&pcs1>;
  97         phy-connection-type = "10gbase-r";
  98         managed = "in-band-status";
  99 };
 100
 101 /* XG0 - Lower SFP */
 102 &dpmac2 {
 103         sfp = <&sfp_xg0>;
 104         pcs-handle = <&pcs2>;
 105         phy-connection-type = "10gbase-r";
 106         managed = "in-band-status";
 107 };
 108
 109 /* DPMAC3..6 is GE4 to GE8 */
 110 &dpmac3 {
 111         phy-handle = <&mdio1_phy5>;
 112         phy-connection-type = "qsgmii";
 113         managed = "in-band-status";
 114         pcs-handle = <&pcs3_0>;
 115 };
 116
 117 &dpmac4 {
 118         phy-handle = <&mdio1_phy6>;
 119         phy-connection-type = "qsgmii";
 120         managed = "in-band-status";
 121         pcs-handle = <&pcs3_1>;
 122 };
 123
 124 &dpmac5 {
 125         phy-handle = <&mdio1_phy7>;
 126         phy-connection-type = "qsgmii";
 127         managed = "in-band-status";
 128         pcs-handle = <&pcs3_2>;
 129 };
 130
 131 &dpmac6 {
 132         phy-handle = <&mdio1_phy8>;
 133         phy-connection-type = "qsgmii";
 134         managed = "in-band-status";
 135         pcs-handle = <&pcs3_3>;
 136 };
 137
 138 /* DPMAC7..10 is GE0 to GE3 */
 139 &dpmac7 {
 140         phy-handle = <&mdio1_phy1>;
 141         phy-connection-type = "qsgmii";
 142         managed = "in-band-status";
 143         pcs-handle = <&pcs7_0>;
 144 };
 145
 146 &dpmac8 {
 147         phy-handle = <&mdio1_phy2>;
 148         phy-connection-type = "qsgmii";
 149         managed = "in-band-status";
 150         pcs-handle = <&pcs7_1>;
 151 };
 152
 153 &dpmac9 {
 154         phy-handle = <&mdio1_phy3>;
 155         phy-connection-type = "qsgmii";
 156         managed = "in-band-status";
 157         pcs-handle = <&pcs7_2>;
 158 };
 159
 160 &dpmac10 {
 161         phy-handle = <&mdio1_phy4>;
 162         phy-connection-type = "qsgmii";
 163         managed = "in-band-status";
 164         pcs-handle = <&pcs7_3>;
 165 };
 166
 167 &duart0 {
 168         status = "okay";
 169 };
 170
 171 &duart1 {
 172         status = "okay";
 173 };
 174
 175 &emdio1 {
 176         status = "okay";
 177
 178         mdio1_phy5: ethernet-phy@c {
 179                 reg = <0xc>;
 180         };
 181
 182         mdio1_phy6: ethernet-phy@d {
 183                 reg = <0xd>;
 184         };
 185
 186         mdio1_phy7: ethernet-phy@e {
 187                 reg = <0xe>;
 188         };
 189
 190         mdio1_phy8: ethernet-phy@f {
 191                 reg = <0xf>;
 192         };
 193
 194         mdio1_phy1: ethernet-phy@1c {
 195                 reg = <0x1c>;
 196         };
 197
 198         mdio1_phy2: ethernet-phy@1d {
 199                 reg = <0x1d>;
 200         };
 201
 202         mdio1_phy3: ethernet-phy@1e {
 203                 reg = <0x1e>;
 204         };
 205
 206         mdio1_phy4: ethernet-phy@1f {
 207                 reg = <0x1f>;
 208         };
 209 };
 210
 211 &esdhc {
 212         status = "okay";
 213 };
 214
 215 &i2c0 {
 216         status = "okay";
 217
 218         sfpgpio: gpio@76 {
 219                 compatible = "ti,tca9539";
 220                 reg = <0x76>;
 221                 #gpio-cells = <2>;
 222                 gpio-controller;
 223
 224                 admin_led_lower {
 225                         gpio-hog;
 226                         gpios = <13 GPIO_ACTIVE_HIGH>;
 227                         output-low;
 228                 };
 229         };
 230
 231         at97sc: tpm@29 {
 232                 compatible = "atmel,at97sc3204t";
 233                 reg = <0x29>;
 234         };
 235 };
 236
 237 &i2c2 {
 238         status = "okay";
 239
 240         rx8035: rtc@32 {
 241                 compatible = "epson,rx8035";
 242                 reg = <0x32>;
 243         };
 244 };
 245
 246 &i2c3 {
 247         status = "okay";
 248
 249         i2c-mux@70 {
 250                 compatible = "nxp,pca9540";
 251                 #address-cells = <1>;
 252                 #size-cells = <0>;
 253                 reg = <0x70>;
 254
 255                 sfpupper_i2c: i2c@0 {
 256                         #address-cells = <1>;
 257                         #size-cells = <0>;
 258                         reg = <0>;
 259                 };
 260
 261                 sfplower_i2c: i2c@1 {
 262                         #address-cells = <1>;
 263                         #size-cells = <0>;
 264                         reg = <1>;
 265                 };
 266         };
 267 };
 268
 269 &pcs_mdio1 {
 270         status = "okay";
 271 };
 272
 273 &pcs_mdio2 {
 274         status = "okay";
 275 };
 276
 277 &pcs_mdio3 {
 278         status = "okay";
 279 };
 280
 281 &pcs_mdio7 {
 282         status = "okay";
 283 };
 284
 285 &qspi {
 286         status = "okay";
 287
 288         en25s64: flash@0 {
 289                 compatible = "jedec,spi-nor";
 290                 #address-cells = <1>;
 291                 #size-cells = <1>;
 292                 reg = <0>;
 293                 spi-max-frequency = <20000000>;
 294                 spi-rx-bus-width = <4>;
 295                 spi-tx-bus-width = <4>;
 296
 297                 partitions {
 298                         compatible = "fixed-partitions";
 299                         #address-cells = <1>;
 300                         #size-cells = <1>;
 301
 302                         partition@0 {
 303                                 label = "bl2";
 304                                 reg = <0 0x100000>;
 305                         };
 306
 307                         partition@100000 {
 308                                 label = "bl3";
 309                                 reg = <0x100000 0x200000>;
 310                         };
 311
 312                         partition@300000 {
 313                                 label = "mcfirmware";
 314                                 reg = <0x300000 0x200000>;
 315                         };
 316
 317                         partition@500000 {
 318                                 label = "ubootenv";
 319                                 reg = <0x500000 0x80000>;
 320                         };
 321
 322                         partition@580000 {
 323                                 label = "dpl";
 324                                 reg = <0x580000 0x40000>;
 325                         };
 326
 327                         partition@5C0000 {
 328                                 label = "dpc";
 329                                 reg = <0x5C0000 0x40000>;
 330                         };
 331
 332                         partition@600000 {
 333                                 label = "devicetree";
 334                                 reg = <0x600000 0x40000>;
 335                         };
 336                 };
 337         };
 338
 339         nand: flash@1 {
 340                 compatible = "spi-nand";
 341                 #address-cells = <1>;
 342                 #size-cells = <1>;
 343                 reg = <1>;
 344                 spi-max-frequency = <20000000>;
 345                 spi-rx-bus-width = <4>;
 346                 spi-tx-bus-width = <4>;
 347
 348                 partitions {
 349                         compatible = "fixed-partitions";
 350                         #address-cells = <1>;
 351                         #size-cells = <1>;
 352
 353                         /* reserved for future boot direct from NAND flash
 354                          * (this would use the same layout as the 8MiB NOR flash)
 355                          */
 356                         partition@0 {
 357                                 label = "nand-boot-reserved";
 358                                 reg = <0 0x800000>;
 359                         };
 360
 361                         /* recovery / install environment */
 362                         partition@800000 {
 363                                 label = "recovery";
 364                                 reg = <0x800000 0x2000000>;
 365                         };
 366
 367                         /* ubia (first OpenWrt) - a/b names to prevent confusion with ubi0/1/etc. */
 368                         partition@2800000 {
 369                                 label = "ubia";
 370                                 reg = <0x2800000 0x6C00000>;
 371                         };
 372
 373                         /* ubib (second OpenWrt) */
 374                         partition@9400000 {
 375                                 label = "ubib";
 376                                 reg = <0x9400000 0x6C00000>;
 377                         };
 378                 };
 379         };
 380 };
 381
 382 &usb0 {
 383         status = "okay";
 384 };
 385
 386 &usb1 {
 387         status = "okay";
 388 };