arch/arm/dts/fsl-ls1088a-rdb.dts

   1 // SPDX-License-Identifier: GPL-2.0+ OR X11
   2 /*
   3  * NXP ls1088a RDB board device tree source
   4  *
   5  * Copyright 2017 NXP
   6  */
   7
   8 /dts-v1/;
   9
  10 #include "fsl-ls1088a.dtsi"
  11
  12 / {
  13         model = "NXP Layerscape 1088a RDB Board";
  14         compatible = "fsl,ls1088a-rdb", "fsl,ls1088a";
  15         aliases {
  16                 spi0 = &qspi;
  17         };
  18 };
  19
  20 &dpmac1 {
  21         status = "okay";
  22         phy-connection-type = "10gbase-r";
  23 };
  24
  25 &dpmac2 {
  26         status = "okay";
  27         phy-handle = <&mdio2_phy1>;
  28         phy-connection-type = "10gbase-r";
  29 };
  30
  31 &dpmac3 {
  32         status = "okay";
  33         phy-handle = <&mdio1_phy5>;
  34         phy-connection-type = "qsgmii";
  35 };
  36
  37 &dpmac4 {
  38         status = "okay";
  39         phy-handle = <&mdio1_phy6>;
  40         phy-connection-type = "qsgmii";
  41 };
  42
  43 &dpmac5 {
  44         status = "okay";
  45         phy-handle = <&mdio1_phy7>;
  46         phy-connection-type = "qsgmii";
  47 };
  48
  49 &dpmac6 {
  50         status = "okay";
  51         phy-handle = <&mdio1_phy8>;
  52         phy-connection-type = "qsgmii";
  53 };
  54
  55 &dpmac7 {
  56         status = "okay";
  57         phy-handle = <&mdio1_phy1>;
  58         phy-connection-type = "qsgmii";
  59 };
  60
  61 &dpmac8 {
  62         status = "okay";
  63         phy-handle = <&mdio1_phy2>;
  64         phy-connection-type = "qsgmii";
  65 };
  66
  67 &dpmac9 {
  68         status = "okay";
  69         phy-handle = <&mdio1_phy3>;
  70         phy-connection-type = "qsgmii";
  71 };
  72
  73 &dpmac10 {
  74         status = "okay";
  75         phy-handle = <&mdio1_phy4>;
  76         phy-connection-type = "qsgmii";
  77 };
  78
  79 &emdio1 {
  80         status = "okay";
  81
  82         /* Freescale F104 PHY1 */
  83         mdio1_phy1: emdio1_phy@1 {
  84                 reg = <0x1c>;
  85                 };
  86         mdio1_phy2: emdio1_phy@2 {
  87                 reg = <0x1d>;
  88                 };
  89         mdio1_phy3: emdio1_phy@3 {
  90                 reg = <0x1e>;
  91                 };
  92         mdio1_phy4: emdio1_phy@4 {
  93                 reg = <0x1f>;
  94         };
  95
  96         /* F104 PHY2 */
  97         mdio1_phy5: emdio1_phy@5 {
  98                 reg = <0x0c>;
  99         };
 100         mdio1_phy6: emdio1_phy@6 {
 101                 reg = <0x0d>;
 102         };
 103         mdio1_phy7: emdio1_phy@7 {
 104                 reg = <0x0e>;
 105         };
 106         mdio1_phy8: emdio1_phy@8 {
 107                 reg = <0x0f>;
 108         };
 109 };
 110
 111 &emdio2 {
 112         status = "okay";
 113
 114         /* Aquantia AQR105 10G PHY */
 115         mdio2_phy1: emdio2_phy@1 {
 116                 compatible = "ethernet-phy-ieee802.3-c45";
 117                 interrupts = <0 2 0x4>;
 118                 reg = <0x0>;
 119         };
 120 };
 121
 122 &i2c0 {
 123         status = "okay";
 124         bootph-all;
 125
 126         i2c-mux@77 {
 127                 compatible = "nxp,pca9547";
 128                 reg = <0x77>;
 129                 #address-cells = <1>;
 130                 #size-cells = <0>;
 131
 132                 i2c@3 {
 133                         #address-cells = <1>;
 134                         #size-cells = <0>;
 135                         reg = <0x3>;
 136
 137                         rtc@51 {
 138                                 compatible = "nxp,pcf2129";
 139                                 reg = <0x51>;
 140                         };
 141                 };
 142         };
 143 };
 144
 145 &duart0 {
 146         status = "okay";
 147 };
 148
 149 &duart1 {
 150         status = "okay";
 151 };
 152
 153 &qspi {
 154         status = "okay";
 155
 156         s25fs512s0: flash@0 {
 157                 #address-cells = <1>;
 158                 #size-cells = <1>;
 159                 compatible = "jedec,spi-nor";
 160                 spi-max-frequency = <50000000>;
 161                 reg = <0>;
 162         };
 163
 164         s25fs512s1: flash@1 {
 165                 #address-cells = <1>;
 166                 #size-cells = <1>;
 167                 compatible = "jedec,spi-nor";
 168                 spi-max-frequency = <50000000>;
 169                 reg = <1>;
 170          };
 171 };
 172
 173 &sata {
 174         status = "okay";
 175 };