arch/arm/dts/exynos78x0.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Samsung Exynos7880 SoC device tree source
   4  *
   5  * Copyright (c) 2020 Dzmitry Sankouski ([email protected])
   6  */
   7
   8 /dts-v1/;
   9 #include "skeleton.dtsi"
  10 #include "exynos78x0-pinctrl.dtsi"
  11 #include "exynos78x0-gpio.dtsi"
  12 / {
  13         compatible = "samsung,exynos7880";
  14
  15         fin_pll: xxti {
  16                 compatible = "fixed-clock";
  17                 clock-output-names = "fin_pll";
  18                 bootph-all;
  19                 #clock-cells = <0>;
  20         };
  21
  22         /* Dummy clock for uart */
  23         fin_uart: uart_dummy_fin {
  24                 compatible = "fixed-clock";
  25                 clock-output-names = "fin_uart";
  26                 clock-frequency = <132710400>;
  27                 bootph-all;
  28                 #clock-cells = <0>;
  29         };
  30
  31         uart2: serial@13820000 {
  32                 compatible = "samsung,exynos4210-uart";
  33                 reg = <0x13820000 0x100>;
  34                 bootph-all;
  35                 clocks = <&fin_uart>, <&fin_uart>; // driver uses 1st clock
  36                 clock-names = "uart", "clk_uart_baud0";
  37                 pinctrl-names = "default";
  38                 pinctrl-0 = <&uart2_bus>;
  39         };
  40
  41         gpioi2c0: i2c-0 {
  42                 #address-cells = <1>;
  43                 #size-cells = <0>;
  44                 compatible = "i2c-gpio";
  45                 status = "disabled";
  46                 gpios = <
  47                         &gpc1 0 0 /* sda */
  48                         &gpc1 1 0 /* scl */
  49                 >;
  50                 i2c-gpio,delay-us = <5>;
  51
  52                 s2mu004@3d {
  53                         compatible = "samsung,s2mu004mfd";
  54                 };
  55         };
  56
  57         /* ALIVE */
  58         pinctrl_0: pinctrl@139F0000 {
  59                 compatible = "samsung,exynos78x0-pinctrl";
  60                 reg = <0x139F0000 0x1000>;
  61         };
  62
  63         /* DISP/AUD */
  64         pinctrl_2: pinctrl@148C0000 {
  65                 compatible = "samsung,exynos78x0-pinctrl";
  66                 reg = <0x148C0000 0x1000>;
  67         };
  68
  69         /* FSYS0 */
  70         pinctrl_4: pinctrl@13750000 {
  71                 compatible = "samsung,exynos78x0-pinctrl";
  72                 reg = <0x13750000 0x1000>;
  73         };
  74
  75         /* ALIVE */
  76         gpio_0: gpio@139F0000 {
  77                 compatible = "samsung,exynos78x0-gpio";
  78                 reg = <0x139F0000 0x1000>;
  79         };
  80
  81         /* DISP/AUD */
  82         gpio_2: gpio@148C0000 {
  83                 compatible = "samsung,exynos78x0-gpio";
  84                 reg = <0x148C0000 0x1000>;
  85         };
  86
  87         /* FSYS0 */
  88         gpio_4: gpio@13750000 {
  89                 compatible = "samsung,exynos78x0-gpio";
  90                 reg = <0x13750000 0x1000>;
  91         };
  92
  93         /* TOP */
  94         gpio_6: gpio@139B0000 {
  95                 compatible = "samsung,exynos78x0-gpio";
  96                 reg = <0x139B0000 0x1000>;
  97         };
  98 };