arch/arm/dts/am335x-icev2.dts

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2016 Texas Instruments Incorporated - https://www.ti.com/
   4  */
   5
   6 /*
   7  * AM335x ICE V2 board
   8  * https://www.ti.com/tool/tmdsice3359
   9  */
  10
  11 /dts-v1/;
  12
  13 #include "am33xx.dtsi"
  14
  15 / {
  16         model = "TI AM3359 ICE-V2";
  17         compatible = "ti,am3359-icev2", "ti,am33xx";
  18
  19         chosen {
  20                 stdout-path = &uart3;
  21                 tick-timer = &timer2;
  22         };
  23
  24         memory@80000000 {
  25                 device_type = "memory";
  26                 reg = <0x80000000 0x10000000>; /* 256 MB */
  27         };
  28
  29         vbat: fixedregulator0 {
  30                 compatible = "regulator-fixed";
  31                 regulator-name = "vbat";
  32                 regulator-min-microvolt = <5000000>;
  33                 regulator-max-microvolt = <5000000>;
  34                 regulator-boot-on;
  35         };
  36
  37         vtt_fixed: fixedregulator1 {
  38                 compatible = "regulator-fixed";
  39                 regulator-name = "vtt";
  40                 regulator-min-microvolt = <1500000>;
  41                 regulator-max-microvolt = <1500000>;
  42                 gpio = <&gpio0 18 GPIO_ACTIVE_HIGH>;
  43                 regulator-always-on;
  44                 regulator-boot-on;
  45                 enable-active-high;
  46         };
  47
  48         leds-iio {
  49                 compatible = "gpio-leds";
  50                 led-out0 {
  51                         label = "out0";
  52                         gpios = <&tpic2810 0 GPIO_ACTIVE_HIGH>;
  53                         default-state = "off";
  54                 };
  55
  56                 led-out1 {
  57                         label = "out1";
  58                         gpios = <&tpic2810 1 GPIO_ACTIVE_HIGH>;
  59                         default-state = "off";
  60                 };
  61
  62                 led-out2 {
  63                         label = "out2";
  64                         gpios = <&tpic2810 2 GPIO_ACTIVE_HIGH>;
  65                         default-state = "off";
  66                 };
  67
  68                 led-out3 {
  69                         label = "out3";
  70                         gpios = <&tpic2810 3 GPIO_ACTIVE_HIGH>;
  71                         default-state = "off";
  72                 };
  73
  74                 led-out4 {
  75                         label = "out4";
  76                         gpios = <&tpic2810 4 GPIO_ACTIVE_HIGH>;
  77                         default-state = "off";
  78                 };
  79
  80                 led-out5 {
  81                         label = "out5";
  82                         gpios = <&tpic2810 5 GPIO_ACTIVE_HIGH>;
  83                         default-state = "off";
  84                 };
  85
  86                 led-out6 {
  87                         label = "out6";
  88                         gpios = <&tpic2810 6 GPIO_ACTIVE_HIGH>;
  89                         default-state = "off";
  90                 };
  91
  92                 led-out7 {
  93                         label = "out7";
  94                         gpios = <&tpic2810 7 GPIO_ACTIVE_HIGH>;
  95                         default-state = "off";
  96                 };
  97         };
  98
  99         /* Tricolor status LEDs */
 100         leds1 {
 101                 compatible = "gpio-leds";
 102                 pinctrl-names = "default";
 103                 pinctrl-0 = <&user_leds>;
 104
 105                 led0 {
 106                         label = "status0:red:cpu0";
 107                         gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>;
 108                         default-state = "off";
 109                         linux,default-trigger = "cpu0";
 110                 };
 111
 112                 led1 {
 113                         label = "status0:green:usr";
 114                         gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>;
 115                         default-state = "off";
 116                 };
 117
 118                 led2 {
 119                         label = "status0:yellow:usr";
 120                         gpios = <&gpio3 9 GPIO_ACTIVE_HIGH>;
 121                         default-state = "off";
 122                 };
 123
 124                 led3 {
 125                         label = "status1:red:mmc0";
 126                         gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>;
 127                         default-state = "off";
 128                         linux,default-trigger = "mmc0";
 129                 };
 130
 131                 led4 {
 132                         label = "status1:green:usr";
 133                         gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>;
 134                         default-state = "off";
 135                 };
 136
 137                 led5 {
 138                         label = "status1:yellow:usr";
 139                         gpios = <&gpio0 19 GPIO_ACTIVE_HIGH>;
 140                         default-state = "off";
 141                 };
 142         };
 143 };
 144
 145 &am33xx_pinmux {
 146         user_leds: user_leds {
 147                 pinctrl-single,pins = <
 148                         AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT, MUX_MODE7) /* (J18) gmii1_txd3.gpio0[16] */
 149                         AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT, MUX_MODE7) /* (K15) gmii1_txd2.gpio0[17] */
 150                         AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT, MUX_MODE7) /* (A15) xdma_event_intr0.gpio0[19] */
 151                         AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT, MUX_MODE7) /* (D14) xdma_event_intr1.gpio0[20] */
 152                         AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_OUTPUT, MUX_MODE7) /* (U9) gpmc_csn1.gpio1[30] */
 153                         AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT, MUX_MODE7) /* (K18) gmii1_txclk.gpio3[9] */
 154                 >;
 155         };
 156
 157         mmc0_pins_default: mmc0_pins_default {
 158                 pinctrl-single,pins = <
 159                         AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0)
 160                         AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0)
 161                         AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0)
 162                         AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0)
 163                         AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0)
 164                         AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0)
 165                         AM33XX_IOPAD(0x960, PIN_INPUT_PULLUP | MUX_MODE5) /* (C15) spi0_cs1.mmc0_sdcd */
 166                 >;
 167         };
 168
 169         i2c0_pins_default: i2c0_pins_default {
 170                 pinctrl-single,pins = <
 171                         AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT, MUX_MODE0)
 172                         AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT, MUX_MODE0)
 173                 >;
 174         };
 175
 176         spi0_pins_default: spi0_pins_default {
 177                 pinctrl-single,pins = <
 178                         AM33XX_IOPAD(0x950, PIN_INPUT_PULLUP | MUX_MODE0) /* (A17) spi0_sclk.spi0_sclk */
 179                         AM33XX_IOPAD(0x954, PIN_INPUT_PULLUP | MUX_MODE0) /* (B17) spi0_d0.spi0_d0 */
 180                         AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE0) /* (B16) spi0_d1.spi0_d1 */
 181                         AM33XX_IOPAD(0x95c, PIN_INPUT_PULLUP | MUX_MODE0) /* (A16) spi0_cs0.spi0_cs0 */
 182                 >;
 183         };
 184
 185         uart3_pins_default: uart3_pins_default {
 186                 pinctrl-single,pins = <
 187                         AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLUP, MUX_MODE1) /* (L17) gmii1_rxd3.uart3_rxd */
 188                         AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_OUTPUT_PULLUP, MUX_MODE1) /* (L16) gmii1_rxd2.uart3_txd */
 189                 >;
 190         };
 191
 192         cpsw_default: cpsw_default {
 193                 pinctrl-single,pins = <
 194                         /* Slave 1, RMII mode */
 195                         AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLUP, MUX_MODE1)        /* mii1_crs.rmii1_crs_dv */
 196                         AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLUP, MUX_MODE0)
 197                         AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLUP, MUX_MODE1)
 198                         AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE1)
 199                         AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLUP, MUX_MODE1)      /* mii1_rxerr.rmii1_rxerr */
 200                         AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE1)    /* mii1_txd0.rmii1_txd0 */
 201                         AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE1)    /* mii1_txd1.rmii1_txd1 */
 202                         AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE1)   /* mii1_txen.rmii1_txen */
 203                         /* Slave 2, RMII mode */
 204                         AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE3)      /* gpmc_wait0.rmii2_crs_dv */
 205                         AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLUP, MUX_MODE1)        /* mii1_col.rmii2_refclk */
 206                         AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLUP, MUX_MODE3)        /* gpmc_a11.rmii2_rxd0 */
 207                         AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLUP, MUX_MODE3)        /* gpmc_a10.rmii2_rxd1 */
 208                         AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE3)        /* gpmc_wpn.rmii2_rxerr */
 209                         AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE3)      /* gpmc_a5.rmii2_txd0 */
 210                         AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLDOWN, MUX_MODE3)      /* gpmc_a4.rmii2_txd1 */
 211                         AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE3)      /* gpmc_a0.rmii2_txen */
 212                 >;
 213         };
 214
 215         cpsw_sleep: cpsw_sleep {
 216                 pinctrl-single,pins = <
 217                         /* Slave 1 reset value */
 218                         AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE7)
 219                         AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
 220                         AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
 221                         AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
 222                         AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7)
 223                         AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
 224                         AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
 225                         AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7)
 226
 227                         /* Slave 2 reset value */
 228                         AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLDOWN, MUX_MODE7)
 229                         AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE7)
 230                         AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE7)
 231                         AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE7)
 232                         AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLDOWN, MUX_MODE7)
 233                         AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_INPUT_PULLDOWN, MUX_MODE7)
 234                         AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_INPUT_PULLDOWN, MUX_MODE7)
 235                         AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_INPUT_PULLDOWN, MUX_MODE7)
 236                 >;
 237         };
 238
 239         davinci_mdio_default: davinci_mdio_default {
 240                 pinctrl-single,pins = <
 241                         /* MDIO */
 242                         AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0)
 243                         AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0)
 244                 >;
 245         };
 246
 247         davinci_mdio_sleep: davinci_mdio_sleep {
 248                 pinctrl-single,pins = <
 249                         /* MDIO reset value */
 250                         AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7)
 251                         AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7)
 252                 >;
 253         };
 254 };
 255
 256 &i2c0 {
 257         pinctrl-names = "default";
 258         pinctrl-0 = <&i2c0_pins_default>;
 259
 260         status = "okay";
 261         clock-frequency = <400000>;
 262
 263         tps: power-controller@2d {
 264                 reg = <0x2d>;
 265         };
 266
 267         tpic2810: gpio@60 {
 268                 compatible = "ti,tpic2810";
 269                 reg = <0x60>;
 270                 gpio-controller;
 271                 #gpio-cells = <2>;
 272         };
 273 };
 274
 275 &spi0 {
 276         status = "okay";
 277         pinctrl-names = "default";
 278         pinctrl-0 = <&spi0_pins_default>;
 279
 280         sn65hvs882@1 {
 281                 compatible = "pisosr-gpio";
 282                 gpio-controller;
 283                 #gpio-cells = <2>;
 284
 285                 load-gpios = <&gpio3 18 GPIO_ACTIVE_LOW>;
 286
 287                 reg = <1>;
 288                 spi-max-frequency = <1000000>;
 289                 spi-cpol;
 290         };
 291
 292         spi_nor: flash@0 {
 293                 #address-cells = <1>;
 294                 #size-cells = <1>;
 295                 compatible = "winbond,w25q64", "jedec,spi-nor";
 296                 spi-max-frequency = <80000000>;
 297                 m25p,fast-read;
 298                 reg = <0>;
 299
 300                 partition@0 {
 301                         label = "u-boot-spl";
 302                         reg = <0x0 0x80000>;
 303                         read-only;
 304                 };
 305
 306                 partition@1 {
 307                         label = "u-boot";
 308                         reg = <0x80000 0x100000>;
 309                         read-only;
 310                 };
 311
 312                 partition@2 {
 313                         label = "u-boot-env";
 314                         reg = <0x180000 0x20000>;
 315                         read-only;
 316                 };
 317
 318                 partition@3 {
 319                         label = "misc";
 320                         reg = <0x1A0000 0x660000>;
 321                 };
 322         };
 323 };
 324
 325 #include "tps65910.dtsi"
 326
 327 &tps {
 328         vcc1-supply = <&vbat>;
 329         vcc2-supply = <&vbat>;
 330         vcc3-supply = <&vbat>;
 331         vcc4-supply = <&vbat>;
 332         vcc5-supply = <&vbat>;
 333         vcc6-supply = <&vbat>;
 334         vcc7-supply = <&vbat>;
 335         vccio-supply = <&vbat>;
 336
 337         regulators {
 338                 vrtc_reg: regulator@0 {
 339                         regulator-always-on;
 340                 };
 341
 342                 vio_reg: regulator@1 {
 343                         regulator-always-on;
 344                 };
 345
 346                 vdd1_reg: regulator@2 {
 347                         regulator-name = "vdd_mpu";
 348                         regulator-min-microvolt = <912500>;
 349                         regulator-max-microvolt = <1326000>;
 350                         regulator-boot-on;
 351                         regulator-always-on;
 352                 };
 353
 354                 vdd2_reg: regulator@3 {
 355                         regulator-name = "vdd_core";
 356                         regulator-min-microvolt = <912500>;
 357                         regulator-max-microvolt = <1144000>;
 358                         regulator-boot-on;
 359                         regulator-always-on;
 360                 };
 361
 362                 vdd3_reg: regulator@4 {
 363                         regulator-always-on;
 364                 };
 365
 366                 vdig1_reg: regulator@5 {
 367                         regulator-always-on;
 368                 };
 369
 370                 vdig2_reg: regulator@6 {
 371                         regulator-always-on;
 372                 };
 373
 374                 vpll_reg: regulator@7 {
 375                         regulator-always-on;
 376                 };
 377
 378                 vdac_reg: regulator@8 {
 379                         regulator-always-on;
 380                 };
 381
 382                 vaux1_reg: regulator@9 {
 383                         regulator-always-on;
 384                 };
 385
 386                 vaux2_reg: regulator@10 {
 387                         regulator-always-on;
 388                 };
 389
 390                 vaux33_reg: regulator@11 {
 391                         regulator-always-on;
 392                 };
 393
 394                 vmmc_reg: regulator@12 {
 395                         regulator-min-microvolt = <1800000>;
 396                         regulator-max-microvolt = <3300000>;
 397                         regulator-always-on;
 398                 };
 399         };
 400 };
 401
 402 &mmc1 {
 403         status = "okay";
 404         vmmc-supply = <&vmmc_reg>;
 405         bus-width = <4>;
 406         pinctrl-names = "default";
 407         pinctrl-0 = <&mmc0_pins_default>;
 408 };
 409
 410 &gpio0 {
 411         /* Do not idle the GPIO used for holding the VTT regulator */
 412         ti,no-reset-on-init;
 413         ti,no-idle-on-init;
 414
 415         p7 {
 416                 gpio-hog;
 417                 gpios = <7 GPIO_ACTIVE_HIGH>;
 418                 output-high;
 419                 line-name = "FET_SWITCH_CTRL";
 420         };
 421 };
 422
 423 &uart3 {
 424         pinctrl-names = "default";
 425         pinctrl-0 = <&uart3_pins_default>;
 426         status = "okay";
 427 };
 428
 429 &gpio3 {
 430         pr1-mii-ctl-hog {
 431                 gpio-hog;
 432                 gpios = <4 GPIO_ACTIVE_HIGH>;
 433                 output-high;
 434                 line-name = "PR1_MII_CTRL";
 435         };
 436
 437         mux-mii-hog {
 438                 gpio-hog;
 439                 gpios = <10 GPIO_ACTIVE_HIGH>;
 440                 /* ETH1 mux: Low for MII-PRU, high for RMII-CPSW */
 441                 output-high;
 442                 line-name = "MUX_MII_CTRL";
 443         };
 444 };
 445
 446 &cpsw_emac0 {
 447         phy-handle = <&ethphy0>;
 448         phy-mode = "rmii";
 449         dual_emac_res_vlan = <1>;
 450 };
 451
 452 &cpsw_emac1 {
 453         phy-handle = <&ethphy1>;
 454         phy-mode = "rmii";
 455         dual_emac_res_vlan = <2>;
 456 };
 457
 458 &mac {
 459         pinctrl-names = "default", "sleep";
 460         pinctrl-0 = <&cpsw_default>;
 461         pinctrl-1 = <&cpsw_sleep>;
 462         status = "okay";
 463         dual_emac;
 464 };
 465
 466 &phy_sel {
 467         rmii-clock-ext;
 468 };
 469
 470 &davinci_mdio {
 471         pinctrl-names = "default", "sleep";
 472         pinctrl-0 = <&davinci_mdio_default>;
 473         pinctrl-1 = <&davinci_mdio_sleep>;
 474         status = "okay";
 475         reset-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>;
 476         reset-delay-us = <2>;   /* PHY datasheet states 1uS min */
 477
 478         ethphy0: ethernet-phy@1 {
 479                 reg = <1>;
 480         };
 481
 482         ethphy1: ethernet-phy@3 {
 483                 reg = <3>;
 484         };
 485 };
 486